*** Running vivado with args -log mgt_axi_fifo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mgt_axi_fifo.tcl ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source mgt_axi_fifo.tcl -notrace Command: synth_design -top mgt_axi_fifo -part xc7vx330tffg1157-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx330t' INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3673126 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2609.438 ; gain = 18.906 ; free physical = 31119 ; free virtual = 53590 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'mgt_axi_fifo' [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/synth/mgt_axi_fifo.vhd:79] WARNING: [Synth 8-3819] Generic 'GLOBAL_DATE' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_TIME' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'INFRASTRUCTURE_LIB_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'INFRASTRUCTURE_LIB_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPS_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPBUS_LIB_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPBUS_LIB_SHA' not present in instantiated entity will be ignored Parameter C_COMMON_CLOCK bound to: 0 - type: integer Parameter C_SELECT_XPM bound to: 0 - type: integer Parameter C_COUNT_TYPE bound to: 0 - type: integer Parameter C_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_DEFAULT_VALUE bound to: BlankString - type: string Parameter C_DIN_WIDTH bound to: 18 - type: integer Parameter C_DOUT_RST_VAL bound to: 0 - type: string Parameter C_DOUT_WIDTH bound to: 18 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer Parameter C_HAS_BACKUP bound to: 0 - type: integer Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_INT_CLK bound to: 0 - type: integer Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer Parameter C_HAS_OVERFLOW bound to: 0 - type: integer Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_RD_RST bound to: 0 - type: integer Parameter C_HAS_RST bound to: 1 - type: integer Parameter C_HAS_SRST bound to: 0 - type: integer Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer Parameter C_HAS_VALID bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 0 - type: integer Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer Parameter C_HAS_WR_RST bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer Parameter C_MEMORY_TYPE bound to: 1 - type: integer Parameter C_MIF_FILE_NAME bound to: BlankString - type: string Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer Parameter C_OVERFLOW_LOW bound to: 0 - type: integer Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer Parameter C_PRELOAD_REGS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE bound to: 4kx4 - type: string Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 1022 - type: integer Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 1021 - type: integer Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer Parameter C_RD_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_RD_DEPTH bound to: 1024 - type: integer Parameter C_RD_FREQ bound to: 1 - type: integer Parameter C_RD_PNTR_WIDTH bound to: 10 - type: integer Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer Parameter C_USE_DOUT_RST bound to: 1 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer Parameter C_VALID_LOW bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_DATA_COUNT_WIDTH bound to: 10 - type: integer Parameter C_WR_DEPTH bound to: 1024 - type: integer Parameter C_WR_FREQ bound to: 1 - type: integer Parameter C_WR_PNTR_WIDTH bound to: 10 - type: integer Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer Parameter C_MSGON_VAL bound to: 1 - type: integer Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer Parameter C_EN_SAFETY_CKT bound to: 1 - type: integer Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_INTERFACE_TYPE bound to: 1 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer Parameter C_HAS_MASTER_CE bound to: 0 - type: integer Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer Parameter C_HAS_AXIS_TID bound to: 0 - type: integer Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer Parameter C_HAS_AXIS_TLAST bound to: 1 - type: integer Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer Parameter C_AXIS_TDATA_WIDTH bound to: 32 - type: integer Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer Parameter C_AXIS_TUSER_WIDTH bound to: 3 - type: integer Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer Parameter C_WACH_TYPE bound to: 0 - type: integer Parameter C_WDCH_TYPE bound to: 0 - type: integer Parameter C_WRCH_TYPE bound to: 0 - type: integer Parameter C_RACH_TYPE bound to: 0 - type: integer Parameter C_RDCH_TYPE bound to: 0 - type: integer Parameter C_AXIS_TYPE bound to: 0 - type: integer Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 12 - type: integer Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 11 - type: integer Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 12 - type: integer Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 12 - type: integer Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 11 - type: integer Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 11 - type: integer Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx36 - type: string Parameter C_USE_ECC_WACH bound to: 0 - type: integer Parameter C_USE_ECC_WDCH bound to: 0 - type: integer Parameter C_USE_ECC_WRCH bound to: 0 - type: integer Parameter C_USE_ECC_RACH bound to: 0 - type: integer Parameter C_USE_ECC_RDCH bound to: 0 - type: integer Parameter C_USE_ECC_AXIS bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer Parameter C_DIN_WIDTH_AXIS bound to: 36 - type: integer Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 15 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 13 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1021 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 13 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 13 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1021 - type: integer Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1021 - type: integer Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer INFO: [Synth 8-3491] module 'fifo_generator_v13_2_5' declared at '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38604' bound to instance 'U0' of component 'fifo_generator_v13_2_5' [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/synth/mgt_axi_fifo.vhd:557] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (1#1) [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (14#1) [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-256] done synthesizing module 'mgt_axi_fifo' (29#1) [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/synth/mgt_axi_fifo.vhd:79] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:46 . Memory (MB): peak = 2866.688 ; gain = 276.156 ; free physical = 29885 ; free virtual = 52358 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:47 . Memory (MB): peak = 2866.688 ; gain = 276.156 ; free physical = 29837 ; free virtual = 52309 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:47 . Memory (MB): peak = 2866.688 ; gain = 276.156 ; free physical = 29837 ; free virtual = 52309 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2866.688 ; gain = 0.000 ; free physical = 29828 ; free virtual = 52300 INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_ooc.xdc] for cell 'U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/mgt_axi_fifo_synth_1/dont_touch.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/mgt_axi_fifo_synth_1/dont_touch.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mgt_axi_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/mgt_axi_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mgt_axi_fifo_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/mgt_axi_fifo_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2930.719 ; gain = 0.000 ; free physical = 29806 ; free virtual = 52286 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2930.719 ; gain = 0.000 ; free physical = 29799 ; free virtual = 52279 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:00:57 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 29678 ; free virtual = 52159 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx330tffg1157-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:00:57 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 29677 ; free virtual = 52158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/mgt_axi_fifo_synth_1/dont_touch.xdc, line 9). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for U0/inst_fifo_gen/\gaxis_fifo.gaxisf.axisf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst . (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:57 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 29660 ; free virtual = 52140 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 10 | 10 both_stages_valid | 11 | 11 stage2_valid | 01 | 01 --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:37 ; elapsed = 00:00:57 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 29656 ; free virtual = 52137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 2 +---XORs : 2 Input 10 Bit XORs := 2 2 Input 1 Bit XORs := 60 +---Registers : 36 Bit Registers := 1 10 Bit Registers := 13 5 Bit Registers := 6 4 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 25 +---Muxes : 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 10 5 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 8 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 1120 (col length:140) BRAMs: 1500 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:59 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 29564 ; free virtual = 52053 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:01:05 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 31067 ; free virtual = 53552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:45 ; elapsed = 00:01:06 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 31059 ; free virtual = 53544 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:45 ; elapsed = 00:01:06 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 31068 ; free virtual = 53553 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |fifo_generator_v13_2_5 | inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/SAFETY_CKT_GEN.RSTA_SHFT_REG_reg[4] | 4 | 2 | NO | NO | YES | 2 | 0 | +-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |LUT1 | 18| |2 |LUT2 | 29| |3 |LUT3 | 12| |4 |LUT4 | 34| |5 |LUT5 | 10| |6 |LUT6 | 9| |7 |MUXCY | 20| |8 |RAMB36E1 | 1| |9 |SRL16E | 2| |10 |FDRE | 208| |11 |FDSE | 13| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32413 ; free virtual = 54894 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:44 ; elapsed = 00:01:05 . Memory (MB): peak = 2930.719 ; gain = 276.156 ; free physical = 32466 ; free virtual = 54947 Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:01:09 . Memory (MB): peak = 2930.719 ; gain = 340.188 ; free physical = 32466 ; free virtual = 54947 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2930.719 ; gain = 0.000 ; free physical = 32564 ; free virtual = 55045 INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2954.742 ; gain = 0.000 ; free physical = 32502 ; free virtual = 54983 INFO: [Project 1-111] Unisim Transformation Summary: A total of 8 instances were transformed. (MUXCY,XORCY) => CARRY4: 8 instances INFO: [Common 17-83] Releasing license: Synthesis 30 Infos, 18 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:22 . Memory (MB): peak = 2954.742 ; gain = 372.215 ; free physical = 32563 ; free virtual = 55045 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/mgt_axi_fifo_synth_1/mgt_axi_fifo.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP mgt_axi_fifo, cache-ID = e6e89a065e68cad4 INFO: [Coretcl 2-1174] Renamed 30 cell refs. INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/0/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/mgt_axi_fifo_synth_1/mgt_axi_fifo.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file mgt_axi_fifo_utilization_synth.rpt -pb mgt_axi_fifo_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sat Mar 8 22:16:52 2025...