Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Sun Mar 9 03:32:05 2025 | Host : efex-heavyduty-vm1.cern.ch running 64-bit unknown | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.2-v1.7.0-E030ECB/reports/hierarchical_utilization.txt | Design : top_efex_processor | Device : 7vx550tffg1927-2 | Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ | top_efex_processor | (top) | 189986(54.85%) | 175947(50.79%) | 0(0.00%) | 14039(8.06%) | 273217(39.44%) | 717(60.76%) | 83(3.52%) | 96(3.33%) | | (top_efex_processor) | (top) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 283(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_PATH_IF.data_path_Module | data_path_block | 118690(34.26%) | 104823(30.26%) | 0(0.00%) | 13867(7.96%) | 180241(26.02%) | 8(0.68%) | 0(0.00%) | 96(3.33%) | | (DATA_PATH_IF.data_path_Module) | data_path_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Sorting_Module | IPBusTopSortingModule | 3226(0.93%) | 3213(0.93%) | 0(0.00%) | 13(0.01%) | 6817(0.98%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Sorting_Module) | IPBusTopSortingModule | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_Delay | GeneralDelay__parameterized6 | 25(0.01%) | 13(0.01%) | 0(0.00%) | 12(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_SORTING_REGISTERS | ipbus_ctrlreg_v__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_eg | TopSortingModule | 1582(0.46%) | 1581(0.46%) | 0(0.00%) | 1(0.01%) | 3341(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_eg) | TopSortingModule | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 290(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5908 | 222(0.06%) | 221(0.06%) | 0(0.00%) | 1(0.01%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5908 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5927 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5928 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5909 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5909 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5925 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5926 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5910 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 437(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5910 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5923 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5924 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0_5911 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0_5911 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5921 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5922 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5912 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5912 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5919 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5920 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5913 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5913 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5917 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5918 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5914 | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 438(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5914 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5915 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5916 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_tau | TopSortingModule_5887 | 1575(0.45%) | 1575(0.45%) | 0(0.00%) | 0(0.00%) | 3335(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_tau) | TopSortingModule_5887 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 288(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5888 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5888 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5906 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5907 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5889 | 215(0.06%) | 215(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5889 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5904 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5905 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5890 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5890 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5902 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5903 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5900 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5901 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5891 | 225(0.06%) | 225(0.06%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5891 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5898 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5899 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5892 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5892 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5896 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5897 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5893 | 225(0.06%) | 225(0.06%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5893 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5894 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5895 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | algorithm_block | IPBusTopAlgoModule | 95753(27.64%) | 94397(27.25%) | 0(0.00%) | 1356(0.78%) | 135900(19.62%) | 8(0.68%) | 0(0.00%) | 96(3.33%) | | (algorithm_block) | IPBusTopAlgoModule | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_STAGE | AlgoInputStage | 5600(1.62%) | 5600(1.62%) | 0(0.00%) | 0(0.00%) | 19485(2.81%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (INPUT_STAGE) | AlgoInputStage | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 105(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].EnergyConverterH | EnergyConverter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1603 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1604 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1605 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1606 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1607 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1608 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1609 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1610 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1611 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1612 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].EnergyConverterH | EnergyConverter_1613 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1614 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1615 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1616 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1617 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1618 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1619 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1620 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1621 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1622 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1623 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].EnergyConverterH | EnergyConverter_1624 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1625 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1626 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1627 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1628 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1629 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1630 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1631 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1632 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1633 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1634 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].EnergyConverterH | EnergyConverter_1635 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1636 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1637 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1638 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1639 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1640 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1642 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1643 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1644 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1645 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].EnergyConverterH | EnergyConverter_1646 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1647 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1648 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1649 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1650 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1651 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1652 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1653 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1654 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1655 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1656 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].EnergyConverterH | EnergyConverter_1657 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1658 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1659 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1660 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1661 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1662 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1663 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1664 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1665 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1666 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1667 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].EnergyConverterH | EnergyConverter_1668 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1669 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1670 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1671 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1672 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1673 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1674 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1675 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1676 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1677 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1678 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].EnergyConverterH | EnergyConverter_1679 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1680 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1681 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1682 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1683 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1684 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1685 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1686 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1687 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1688 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1689 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].EnergyConverterH | EnergyConverter_1690 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1691 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1692 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1693 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1694 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1695 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1696 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1697 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1698 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1699 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1700 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].EnergyConverterH | EnergyConverter_1701 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1702 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1703 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1704 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1705 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1706 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1707 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1708 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1709 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1711 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].EnergyConverterH | EnergyConverter_1712 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1713 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1714 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1715 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1716 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1717 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1718 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1719 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1720 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1721 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1722 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].EnergyConverterH | EnergyConverter_1723 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1724 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1725 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1726 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1727 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1728 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1729 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1730 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1731 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1732 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1733 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].EnergyConverterH | EnergyConverter_1734 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1735 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1736 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1737 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1738 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1739 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1740 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1741 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1742 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1743 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1744 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].EnergyConverterH | EnergyConverter_1745 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1746 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1747 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1748 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1749 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1750 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1751 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1752 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1753 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1754 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1755 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].EnergyConverterH | EnergyConverter_1756 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1757 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1758 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1759 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1760 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1761 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1762 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1763 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1764 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1765 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1766 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].EnergyConverterH | EnergyConverter_1767 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1768 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1769 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1770 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1771 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1772 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1773 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1774 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1775 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1776 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1777 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].EnergyConverterH | EnergyConverter_1778 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1779 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1780 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1781 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1782 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1783 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1784 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1785 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1786 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1787 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1788 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].EnergyConverterH | EnergyConverter_1789 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1790 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1791 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1792 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1793 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1794 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1795 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1796 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1797 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1798 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1799 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].EnergyConverterH | EnergyConverter_1800 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1801 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1802 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1803 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1804 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1805 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1806 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1807 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1808 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1809 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1810 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].EnergyConverterH | EnergyConverter_1811 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1812 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1813 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1814 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1815 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1816 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1817 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1818 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1819 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1820 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1821 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].EnergyConverterH | EnergyConverter_1822 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1823 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1824 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1825 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1826 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1827 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1828 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1829 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1830 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1831 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1832 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].EnergyConverterH | EnergyConverter_1833 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1834 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1835 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1836 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1837 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1838 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1839 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1840 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1841 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1842 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1843 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].EnergyConverterH | EnergyConverter_1844 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1845 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1846 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1847 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1848 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1849 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1850 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1851 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1852 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1853 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1854 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].EnergyConverterH | EnergyConverter_1855 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1856 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1857 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1858 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1859 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1860 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1861 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1862 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1863 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1864 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1865 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].EnergyConverterH | EnergyConverter_1866 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1867 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1868 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1869 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1870 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1871 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1872 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1873 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1874 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1875 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1876 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].EnergyConverterH | EnergyConverter_1877 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1878 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1879 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1880 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1881 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1882 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1883 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1884 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1885 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1886 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1887 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].EnergyConverterH | EnergyConverter_1888 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1889 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1890 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1891 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1892 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1893 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1894 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1895 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1896 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1897 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1898 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].EnergyConverterH | EnergyConverter_1899 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1900 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1901 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1902 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1903 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1904 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1905 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1906 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1907 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1908 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1909 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].EnergyConverterH | EnergyConverter_1910 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1911 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1912 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1913 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1914 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1915 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1916 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1917 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1918 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1919 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1920 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].EnergyConverterH | EnergyConverter_1921 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1922 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1923 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1924 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1925 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1926 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1927 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1928 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1929 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1930 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1931 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].EnergyConverterH | EnergyConverter_1932 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1933 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1934 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1935 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1936 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1937 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1938 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1939 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1940 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1941 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1942 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].EnergyConverterH | EnergyConverter_1943 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1944 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1945 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1946 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1947 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1948 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1949 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1950 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1951 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1952 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1953 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].EnergyConverterH | EnergyConverter_1954 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1955 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1956 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1957 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1958 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1959 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1960 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1961 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1962 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1963 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1964 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].EnergyConverterH | EnergyConverter_1965 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1966 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1967 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1968 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1969 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1970 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1971 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1972 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1973 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1974 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1975 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].EnergyConverterH | EnergyConverter_1976 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1977 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1978 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1979 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1980 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1981 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1982 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1983 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1984 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1985 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1986 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].EnergyConverterH | EnergyConverter_1987 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1988 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1989 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1990 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1991 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1992 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1993 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1994 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1995 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1996 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1997 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].EnergyConverterH | EnergyConverter_1998 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1999 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2000 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2001 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2002 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2003 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2004 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2005 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2006 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2007 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2008 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].EnergyConverterH | EnergyConverter_2009 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2010 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2011 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2012 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2013 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2014 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2015 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2016 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2017 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2018 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2019 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].EnergyConverterH | EnergyConverter_2020 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2021 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2022 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2023 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2024 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2025 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2026 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2027 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2028 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2029 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2030 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].EnergyConverterH | EnergyConverter_2031 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2032 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2033 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2034 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2035 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2036 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2037 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2038 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2039 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2040 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2041 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].EnergyConverterH | EnergyConverter_2042 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2043 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2044 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2045 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2046 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2047 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2048 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2049 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2050 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2051 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2052 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].EnergyConverterH | EnergyConverter_2053 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2054 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2055 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2056 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2057 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2058 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2059 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2060 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2061 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2062 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2063 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].EnergyConverterH | EnergyConverter_2064 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2065 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2066 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2067 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2068 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2069 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2070 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2071 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2072 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2073 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2074 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].EnergyConverterH | EnergyConverter_2075 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2076 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2077 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2078 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2079 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2080 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2081 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2082 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2084 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2085 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].EnergyConverterH | EnergyConverter_2086 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2087 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2088 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2089 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2090 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2091 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2092 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2093 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2094 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2095 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2096 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].EnergyConverterH | EnergyConverter_2097 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2098 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2099 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2100 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2101 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2102 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2103 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2104 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2105 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2106 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2107 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].EnergyConverterH | EnergyConverter_2108 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2109 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2110 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2111 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2112 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2113 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2114 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2115 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2116 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2117 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2118 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].EnergyConverterH | EnergyConverter_2119 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2120 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2121 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2122 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2123 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2124 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2125 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2126 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2127 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2128 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2129 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].EnergyConverterH | EnergyConverter_2130 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2131 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2132 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2133 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2134 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2135 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2136 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2137 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2138 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2139 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2140 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].EnergyConverterH | EnergyConverter_2141 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2142 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2143 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2144 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2145 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2146 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2147 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2148 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2149 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2150 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2151 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].EnergyConverterH | EnergyConverter_2152 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2153 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2154 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2155 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2156 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2157 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2158 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2159 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2160 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2161 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2162 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].EnergyConverterH | EnergyConverter_2163 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2164 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2165 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2166 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2167 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2168 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2169 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2170 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2171 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2172 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2173 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].EnergyConverterH | EnergyConverter_2174 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2175 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2176 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2177 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2178 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2179 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2180 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2181 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2183 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2184 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].EnergyConverterH | EnergyConverter_2185 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2186 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2187 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2188 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2189 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2190 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2191 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2192 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2193 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2194 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2195 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].EnergyConverterH | EnergyConverter_2196 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2197 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2198 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2199 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2200 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2201 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2202 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2203 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2204 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2205 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2206 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].EnergyConverterH | EnergyConverter_2207 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2208 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2209 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2210 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2211 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2212 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2213 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2214 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2215 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2216 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2217 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].EnergyConverterH | EnergyConverter_2218 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2219 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2220 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2221 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2222 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2223 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2224 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2225 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2227 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2228 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].EnergyConverterH | EnergyConverter_2229 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2230 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2231 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2232 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2233 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2234 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2235 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2236 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2237 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2238 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2239 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].EnergyConverterH | EnergyConverter_2240 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2241 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2242 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2243 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2244 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2245 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2246 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2247 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2248 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2249 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2250 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].EnergyConverterH | EnergyConverter_2251 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2252 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2253 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2254 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2255 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2256 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2257 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2258 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2259 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2260 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2261 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_PARAMETER_RAM | AlgoParameterRAM_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (IPBUS_ALGO_PARAMETER_RAM) | AlgoParameterRAM_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_PARAMETER_RAM | AlgoParameterRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | AlgoParameterRAM_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | AlgoParameterRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized8 | 5442(1.57%) | 5442(1.57%) | 0(0.00%) | 0(0.00%) | 2059(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LOAD_GENERATOR | LoadGenerator | 126(0.04%) | 124(0.04%) | 0(0.00%) | 2(0.01%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RATE_MONITOR | AlgoRateMonitor | 1923(0.56%) | 1922(0.55%) | 0(0.00%) | 1(0.01%) | 3215(0.46%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RATE_MONITOR) | AlgoRateMonitor | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized7 | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | NORMALISATION_CNT | counter | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_EG | counter_1507 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_TAU | counter_1508 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_EG | counter_1509 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_TAU | counter_1510 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_EG | counter_1511 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_TAU | counter_1512 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_EG | counter_1513 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_TAU | counter_1514 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_EG | counter_1515 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_TAU | counter_1516 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_EG | counter_1517 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_TAU | counter_1518 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_EG | counter_1519 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_TAU | counter_1520 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_EG | counter_1521 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_TAU | counter_1522 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_EG | counter_1523 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_TAU | counter_1524 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_EG | counter_1525 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_TAU | counter_1526 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_EG | counter_1527 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_TAU | counter_1528 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_EG | counter_1529 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_TAU | counter_1530 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_EG | counter_1531 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_TAU | counter_1532 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_EG | counter_1533 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_TAU | counter_1534 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_EG | counter_1535 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_TAU | counter_1536 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_EG | counter_1537 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_TAU | counter_1538 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_EG | counter_1539 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_TAU | counter_1540 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_EG | counter_1541 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_TAU | counter_1542 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_EG | counter_1543 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_TAU | counter_1544 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_EG | counter_1545 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_TAU | counter_1546 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_EG | counter_1547 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_TAU | counter_1548 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_EG | counter_1549 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_TAU | counter_1550 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_EG | counter_1551 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_TAU | counter_1552 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_EG | counter_1553 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_TAU | counter_1554 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_EG | counter_1555 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_TAU | counter_1556 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_EG | counter_1557 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_TAU | counter_1558 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_EG | counter_1559 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_TAU | counter_1560 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_EG | counter_1561 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_TAU | counter_1562 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_EG | counter_1563 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_TAU | counter_1564 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_EG | counter_1565 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_TAU | counter_1566 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_EG | counter_1567 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_TAU | counter_1568 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_EG | counter_1569 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_TAU | counter_1570 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_EG | counter_1571 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_TAU | counter_1572 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_EG | counter_1573 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_TAU | counter_1574 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_EG | counter_1575 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_TAU | counter_1576 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_EG | counter_1577 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_TAU | counter_1578 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_EG | counter_1579 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_TAU | counter_1580 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_EG | counter_1581 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_TAU | counter_1582 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_EG | counter_1583 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_TAU | counter_1584 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_EG | counter_1585 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_TAU | counter_1586 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_EG | counter_1587 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_TAU | counter_1588 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_EG | counter_1589 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_TAU | counter_1590 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_EG | counter_1591 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_TAU | counter_1592 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_EG | counter_1593 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_TAU | counter_1594 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_EG | counter_1595 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_TAU | counter_1596 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_EG | counter_1597 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_TAU | counter_1598 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_EG | counter_1599 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_TAU | counter_1600 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_EG | counter_1601 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_TAU | counter_1602 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOP_ALGO_MODULE | TopAlgoModule | 77760(22.45%) | 76407(22.06%) | 0(0.00%) | 1353(0.78%) | 103315(14.91%) | 0(0.00%) | 0(0.00%) | 96(3.33%) | | (TOP_ALGO_MODULE) | TopAlgoModule | 75486(21.79%) | 75486(21.79%) | 0(0.00%) | 0(0.00%) | 89(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[0].AGLO_CORE_EG | AlgoCore_eg__xdcDup__1 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7496(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[0].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__1 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5665 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_5666 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5667 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_5668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_5669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_5669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5789 | 0(0.00%) | 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0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_5856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_5857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_5858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_5859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_5860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_5861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_5862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_5863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_5864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_5865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_5866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_5867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_5868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_5869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_5870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_5871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_5872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_5873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_5874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_5875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_5876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_5877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_5878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_5879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_5880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_5881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_5882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_5883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_5884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_5885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_5886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_5670 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_5670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5744 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_5671 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_5671 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5672 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5672 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5675 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5675 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_5676 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_5677 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5678 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__1 | 150(0.04%) | 71(0.02%) | 0(0.00%) | 79(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_5430 | 113(0.03%) | 64(0.02%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_5453 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5653 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5657 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_5454 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_5455 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_5456 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_5457 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_5458 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_5459 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_5460 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_5461 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_5462 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_5463 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5464 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5635 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5637 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5639 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5643 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5465 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5606 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5607 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5610 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5611 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5614 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5615 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5616 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5617 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5618 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5619 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_5466 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5601 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_5467 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5588 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5589 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5591 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_5468 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5576 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5577 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_5469 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5565 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5567 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_5470 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5553 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_5471 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5540 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5541 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_5472 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_5473 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5517 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5518 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5520 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5521 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_5474 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5505 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5508 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5509 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_5475 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_5476 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_5477 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5496 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_5478 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5493 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_5479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_5480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_5481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_5482 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5487 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_5483 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5484 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_5431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_5432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_5433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_5434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_5435 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_5440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5441 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_5442 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_5443 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_5444 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_5445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_5446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_5447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_5448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_5449 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_5450 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5451 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_5452 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_5436 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[1].AGLO_CORE_EG | AlgoCore_eg__xdcDup__2 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7503(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[1].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__2 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5208 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_5209 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5210 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_5211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_5346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_5347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_5349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_5350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_5351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_5353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_5354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_5365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_5366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | 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stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5287 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_5214 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_5214 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5215 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5215 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5218 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 283(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5218 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_5219 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_5220 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5221 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__2 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_4973 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4996 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5196 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5199 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4997 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4998 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4999 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_5000 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_5001 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_5002 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_5003 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_5004 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_5005 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_5006 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5007 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5177 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5178 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5180 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5182 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5185 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5186 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5008 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5156 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5160 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5162 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_5009 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_5010 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5132 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5134 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_5011 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5119 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5120 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5123 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_5012 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5107 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5110 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5111 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_5013 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5098 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5099 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_5014 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5083 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5084 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5086 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_5015 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5071 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5072 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_5016 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5060 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5061 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5063 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5064 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_5017 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5048 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5049 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5051 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_5018 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5045 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_5019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_5020 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_5021 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_5023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_5024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_5025 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5030 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_5026 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5027 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4976 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4978 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4984 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4985 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4986 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4987 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4992 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4993 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4994 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4995 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4979 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[2].AGLO_CORE_EG | AlgoCore_eg__xdcDup__3 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7497(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[2].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__3 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4751 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_4752 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4753 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD85 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD86 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD88 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4865 | 0(0.00%) | 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0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_4756 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4830 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_4757 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 263(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_4757 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4758 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4758 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4761 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4761 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_4762 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_4763 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4764 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__3 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_4516 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4539 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4743 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4540 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4541 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4542 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4543 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4544 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4545 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4546 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4547 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4548 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4549 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4550 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4721 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4725 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4551 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4693 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4695 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4697 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4702 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4703 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4705 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4687 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4553 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4675 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4554 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4662 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4555 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4653 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4556 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4639 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4557 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_4558 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4614 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4615 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4617 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4618 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_4559 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4603 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4604 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4606 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4607 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_4560 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4591 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4594 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_4561 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4588 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_4562 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4585 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_4563 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4582 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_4564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_4565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_4567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_4568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4573 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_4569 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4519 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4521 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4527 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4528 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4529 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4530 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4535 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4536 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4537 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4538 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4522 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[3].AGLO_CORE_EG | AlgoCore_eg__xdcDup__4 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7492(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[3].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__4 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4294 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_4295 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4296 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD89 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD90 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD91 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD92 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD93 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_4297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_4432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_4433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_4435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_4436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_4437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_4438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_4439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_4440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_4441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_4444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_4445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_4446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_4447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_4448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_4449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_4450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_4451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_4452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_4453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_4454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_4455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_4456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_4457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_4458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_4459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_4460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_4461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_4462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_4463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_4464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_4465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 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stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | 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0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_4299 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4373 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_4300 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_4300 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4301 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4301 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4304 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4304 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_4305 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_4306 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4307 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__4 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__4 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_4059 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4082 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4282 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4283 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4285 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4286 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4083 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4084 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4085 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4086 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4087 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4088 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4089 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4090 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4091 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4092 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4093 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4264 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4266 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4267 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4268 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4094 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4244 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4245 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4096 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4097 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4205 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4098 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4194 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4196 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4099 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4182 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4185 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4100 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4169 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4170 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4173 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_4101 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4160 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_4102 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4146 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_4103 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4134 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4137 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_4104 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_4105 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_4106 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4125 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_4107 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_4108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_4109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_4110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_4111 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_4112 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4062 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4064 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4070 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4071 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4072 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4073 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4078 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4079 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4080 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4081 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4065 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[4].AGLO_CORE_EG | AlgoCore_eg__xdcDup__5 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7493(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[4].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__5 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3837 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_3838 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3839 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_3840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_4000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_4001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_4002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_4003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_4004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_4005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_4006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_4007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_4008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_3842 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_3842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3916 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_3843 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_3843 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3844 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3844 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3847 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3847 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_3848 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_3849 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3850 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__5 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__5 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_3602 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_3625 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_3626 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_3627 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_3628 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_3629 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_3630 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_3631 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_3632 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_3633 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_3634 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_3635 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3636 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3807 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3809 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3810 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3811 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3812 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3815 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3637 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3781 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3782 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3785 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3786 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3787 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3789 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3790 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_3638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_3639 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3760 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3761 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3764 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_3640 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3748 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3749 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_3641 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_3642 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3725 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_3643 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_3644 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3703 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_3645 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3693 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_3646 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_3647 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_3648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_3649 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_3650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_3651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_3652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_3653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_3654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3659 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_3655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_3604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_3605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_3606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_3607 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_3612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3613 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_3614 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_3615 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_3616 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_3617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_3618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_3619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_3621 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_3622 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3623 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3624 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[5].AGLO_CORE_EG | AlgoCore_eg__xdcDup__6 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7493(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[5].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__6 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3380 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_3381 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3382 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | 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Adder__sblockDup__1_3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_3385 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3459 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_3386 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_3386 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3387 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3387 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3390 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3390 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_3391 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_3392 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3393 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__6 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_3145 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_3168 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3368 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_3169 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_3170 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_3171 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_3172 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_3173 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_3174 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_3175 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_3176 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_3177 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_3178 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3179 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3352 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3353 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3354 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3355 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3356 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3357 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3180 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3321 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3324 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3326 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3328 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3329 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3330 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_3181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_3182 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3303 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3304 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3306 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3307 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_3183 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3291 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3294 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3295 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_3184 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3279 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3280 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3282 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3283 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_3185 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3267 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3268 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_3186 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3256 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3258 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3259 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_3187 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3244 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_3188 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3232 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3233 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_3189 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3223 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3224 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_3190 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_3191 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_3192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_3193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_3197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3202 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_3198 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3199 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_3148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_3150 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3156 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_3157 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_3158 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_3159 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_3161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_3164 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_3165 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3166 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3167 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[6].AGLO_CORE_EG | AlgoCore_eg__xdcDup__7 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7492(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[6].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__7 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_2923 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_2924 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_2925 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_2928 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3002 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_2929 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_2929 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_2930 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_2930 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_2933 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_2933 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_2934 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_2935 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_2936 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__7 | 150(0.04%) | 71(0.02%) | 0(0.00%) | 79(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__7 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_2688 | 113(0.03%) | 64(0.02%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_2711 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2911 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2914 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2915 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_2712 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_2713 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_2714 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_2715 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_2716 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_2717 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_2718 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_2719 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_2720 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_2721 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2722 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2893 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2895 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2896 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2897 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2899 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2900 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2901 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2723 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2864 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2865 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2866 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2869 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2871 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2872 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2873 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2875 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2876 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_2724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2859 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_2725 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2846 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2847 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2849 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_2726 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2834 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2835 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2837 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_2727 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2822 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2823 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_2728 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2810 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_2729 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2799 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2802 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_2730 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2786 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2787 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2789 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2790 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_2731 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_2732 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2764 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2767 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_2733 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2760 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_2734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2757 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_2735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2754 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_2736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_2740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_2741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_2690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_2691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_2693 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2699 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_2700 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_2701 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_2702 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_2707 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_2708 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2709 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2710 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_2694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[7].AGLO_CORE_EG | AlgoCore_eg | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7492(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[7].AGLO_CORE_EG) | AlgoCore_eg | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 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0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_2664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_2674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_2679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_2682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_2684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_2685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2545 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt | 150(0.04%) | 71(0.02%) | 0(0.00%) | 79(0.05%) | 3870(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1 | 113(0.03%) | 64(0.02%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2467 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2470 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2471 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_2275 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_2276 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_2277 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_2278 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_2279 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_2280 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_2281 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_2282 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2448 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2449 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2451 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2452 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2453 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2454 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2455 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2456 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2457 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2283 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2421 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2422 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2425 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2427 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2428 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2429 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2431 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_2284 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2403 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_2285 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2390 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2391 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2393 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2394 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_2286 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2378 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2379 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_2287 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2366 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_2288 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2354 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2355 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2357 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_2289 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2342 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_2290 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2335 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_2291 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2319 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_2292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2313 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_2293 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2310 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_2294 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2307 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_2295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_2296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_2297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2301 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_2298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_2263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2264 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_2265 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_2266 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_2267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_2268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_2269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_2271 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_2272 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2273 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2274 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_SHIFT_REGISTER | AlgoShiftRegister | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12336(1.78%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_eg | SerialSorter | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 481(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_eg) | SerialSorter | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1502 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1503 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1504 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1505 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1506 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_tau | SerialSorter_1413 | 295(0.09%) | 295(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_tau) | SerialSorter_1413 | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1497 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1498 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1499 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1500 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1501 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_eg | SerialSorter_1414 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_eg) | SerialSorter_1414 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1492 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1493 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1494 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1495 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1496 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_tau | SerialSorter_1415 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_tau) | SerialSorter_1415 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1487 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1488 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1489 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1490 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1491 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_eg | SerialSorter_1416 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_eg) | SerialSorter_1416 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1482 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1483 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1484 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1485 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1486 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_tau | SerialSorter_1417 | 296(0.09%) | 296(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_tau) | SerialSorter_1417 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1477 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1478 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1479 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1480 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1481 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_eg | SerialSorter_1418 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_eg) | SerialSorter_1418 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1472 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1473 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1474 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1475 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1476 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_tau | SerialSorter_1419 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_tau) | SerialSorter_1419 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1467 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1468 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1469 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1470 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1471 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_eg | SerialSorter_1420 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_eg) | SerialSorter_1420 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1462 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1463 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1464 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1465 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1466 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_tau | SerialSorter_1421 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_tau) | SerialSorter_1421 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1457 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1458 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1459 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1460 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1461 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_eg | SerialSorter_1422 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_eg) | SerialSorter_1422 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1452 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1453 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1454 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1455 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1456 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_tau | SerialSorter_1423 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_tau) | SerialSorter_1423 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1447 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1448 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1449 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1450 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1451 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_eg | SerialSorter_1424 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_eg) | SerialSorter_1424 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1442 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1443 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1444 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1445 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1446 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_tau | SerialSorter_1425 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_tau) | SerialSorter_1425 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1437 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1438 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1439 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1440 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1441 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_eg | SerialSorter_1426 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_eg) | SerialSorter_1426 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1432 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1433 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1434 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1435 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1436 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_tau | SerialSorter_1427 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_tau) | SerialSorter_1427 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1428 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1429 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1430 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1431 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_alignment_block | data_alignment | 19690(5.68%) | 7192(2.08%) | 0(0.00%) | 12498(7.17%) | 37512(5.41%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_alignment_block) | data_alignment | 180(0.05%) | 180(0.05%) | 0(0.00%) | 0(0.00%) | 848(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[0].bc_align_b | quad_bc_alignment | 117(0.03%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[0].bc_align_b) | quad_bc_alignment | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1409 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1410 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1411 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1412 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[11].bc_align_b | quad_bc_alignment_601 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[11].bc_align_b) | quad_bc_alignment_601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1402 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1403 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1404 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1405 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[12].bc_align_b | quad_bc_alignment_602 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[12].bc_align_b) | quad_bc_alignment_602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1394 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1395 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1396 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1397 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[13].bc_align_b | quad_bc_alignment_603 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[13].bc_align_b) | quad_bc_alignment_603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1386 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1387 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1388 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1389 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[14].bc_align_b | quad_bc_alignment_604 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[14].bc_align_b) | quad_bc_alignment_604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1378 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1379 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1380 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1381 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[15].bc_align_b | quad_bc_alignment_605 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[15].bc_align_b) | quad_bc_alignment_605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1370 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1371 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1372 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1373 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[1].bc_align_b | quad_bc_alignment_606 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[1].bc_align_b) | quad_bc_alignment_606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1362 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1363 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1364 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1365 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[2].bc_align_b | quad_bc_alignment_607 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[2].bc_align_b) | quad_bc_alignment_607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1354 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1355 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1356 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1357 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[3].bc_align_b | quad_bc_alignment_608 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[3].bc_align_b) | quad_bc_alignment_608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1346 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1347 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1348 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1349 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[4].bc_align_b | quad_bc_alignment_609 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[4].bc_align_b) | quad_bc_alignment_609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1338 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1339 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1340 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1341 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[5].bc_align_b | quad_bc_alignment_610 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[5].bc_align_b) | quad_bc_alignment_610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1330 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1331 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1332 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1333 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[6].bc_align_b | quad_bc_alignment_611 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[6].bc_align_b) | quad_bc_alignment_611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1322 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1323 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1324 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1325 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[7].bc_align_b | quad_bc_alignment_612 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[7].bc_align_b) | quad_bc_alignment_612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1314 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1315 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1316 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1317 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[8].bc_align_b | quad_bc_alignment_613 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[8].bc_align_b) | quad_bc_alignment_613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1306 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1307 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1308 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1309 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[9].bc_align_b | quad_bc_alignment_614 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[9].bc_align_b) | quad_bc_alignment_614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1298 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1299 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1300 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1301 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[0].bc_align_a | quad_bc_alignment_615 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[0].bc_align_a) | quad_bc_alignment_615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1290 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1291 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1292 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1293 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[11].bc_align_a | quad_bc_alignment_617 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[11].bc_align_a) | quad_bc_alignment_617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1279 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1280 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1281 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1282 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[12].bc_align_a | quad_bc_alignment_618 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[12].bc_align_a) | quad_bc_alignment_618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1271 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1272 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1273 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1274 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[13].bc_align_a | quad_bc_alignment_619 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[13].bc_align_a) | quad_bc_alignment_619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1263 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1264 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1265 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1266 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[14].bc_align_a | quad_bc_alignment_620 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[14].bc_align_a) | quad_bc_alignment_620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1255 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1256 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1257 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1258 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[15].bc_align_a | quad_bc_alignment_621 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[15].bc_align_a) | quad_bc_alignment_621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1247 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1248 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1249 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1250 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[1].bc_align_a | quad_bc_alignment_622 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[1].bc_align_a) | quad_bc_alignment_622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1239 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1240 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1241 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1242 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[2].bc_align_a | quad_bc_alignment_623 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[2].bc_align_a) | quad_bc_alignment_623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1231 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1232 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1233 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1234 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[3].bc_align_a | quad_bc_alignment_624 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[3].bc_align_a) | quad_bc_alignment_624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1223 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1224 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1225 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1226 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[4].bc_align_a | quad_bc_alignment_625 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[4].bc_align_a) | quad_bc_alignment_625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1215 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1216 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1217 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1218 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[5].bc_align_a | quad_bc_alignment_626 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[5].bc_align_a) | quad_bc_alignment_626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1207 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1208 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1209 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1210 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[6].bc_align_a | quad_bc_alignment_627 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[6].bc_align_a) | quad_bc_alignment_627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1199 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1200 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1201 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1202 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[7].bc_align_a | quad_bc_alignment_628 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[7].bc_align_a) | quad_bc_alignment_628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1191 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1192 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1193 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1194 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[8].bc_align_a | quad_bc_alignment_629 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[8].bc_align_a) | quad_bc_alignment_629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1183 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1184 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1185 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1186 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[9].bc_align_a | quad_bc_alignment_630 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[9].bc_align_a) | quad_bc_alignment_630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1176 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1177 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1178 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo | pseudo_orbit_gen | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo_b | pseudo_orbit_gen_631 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u0 | top_synch | 273(0.08%) | 24(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u0) | top_synch | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1166 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1167 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1168 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1169 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1170 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1170 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1171 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u1 | crc_checker | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u1) | crc_checker | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1165 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u0 | top_synch_632 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u0) | top_synch_632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1160 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1161 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1162 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1163 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1163 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1164 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u1 | crc_checker_633 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u1) | crc_checker_633 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1158 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u0 | top_synch_634 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u0) | top_synch_634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1153 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1154 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1155 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1156 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1156 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1157 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u1 | crc_checker_635 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u1) | crc_checker_635 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1151 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u0 | top_synch_636 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u0) | top_synch_636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1145 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1146 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1147 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1148 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1149 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1149 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1150 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u1 | crc_checker_637 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u1) | crc_checker_637 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1144 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u0 | top_synch_638 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u0) | top_synch_638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1139 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1140 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1141 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1142 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1142 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1143 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u1 | crc_checker_639 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u1) | crc_checker_639 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1137 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u0 | top_synch_640 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u0) | top_synch_640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1132 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1133 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1134 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1135 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1135 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1136 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u1 | crc_checker_641 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u1) | crc_checker_641 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1130 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u0 | top_synch_642 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u0) | top_synch_642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1124 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1125 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1126 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1127 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1128 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1128 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1129 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u1 | crc_checker_643 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u1) | crc_checker_643 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1123 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u0 | top_synch_644 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u0) | top_synch_644 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1117 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1118 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1119 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1120 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1121 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1121 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1122 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u1 | crc_checker_645 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u1) | crc_checker_645 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1116 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u0 | top_synch_646 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u0) | top_synch_646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1110 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1111 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1112 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1113 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1114 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1114 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1115 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u1 | crc_checker_647 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u1) | crc_checker_647 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1109 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u0 | top_synch_648 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u0) | top_synch_648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1104 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1105 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1106 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1107 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1107 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1108 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u1 | crc_checker_649 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u1) | crc_checker_649 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1102 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u0 | top_synch_650 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u0) | top_synch_650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1097 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1098 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1099 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1100 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1100 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1101 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u1 | crc_checker_651 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u1) | crc_checker_651 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1095 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u0 | top_synch_652 | 274(0.08%) | 25(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u0) | top_synch_652 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1089 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1090 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1091 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1092 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1093 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1093 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1094 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u1 | crc_checker_653 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u1) | crc_checker_653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1088 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u0 | top_synch_654 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u0) | top_synch_654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1083 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1084 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1085 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1086 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1086 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1087 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u1 | crc_checker_655 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u1) | crc_checker_655 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1081 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u0 | top_synch_656 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u0) | top_synch_656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1076 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1077 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1078 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1079 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1079 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1080 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u1 | crc_checker_657 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u1) | crc_checker_657 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1074 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u0 | top_synch_658 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u0) | top_synch_658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1068 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1069 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1070 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1071 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1072 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1072 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1073 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u1 | crc_checker_659 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u1) | crc_checker_659 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1067 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u0 | top_synch_660 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u0) | top_synch_660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1061 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1062 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1063 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1064 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1065 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1065 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1066 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u1 | crc_checker_661 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u1) | crc_checker_661 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1060 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u0 | top_synch_662 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u0) | top_synch_662 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1054 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1055 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1056 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1057 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1058 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1058 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1059 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u1 | crc_checker_663 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u1) | crc_checker_663 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1053 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u0 | top_synch_664 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u0) | top_synch_664 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1047 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1048 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1049 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1050 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1051 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1051 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1052 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u1 | crc_checker_665 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u1) | crc_checker_665 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1046 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u0 | top_synch_666 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u0) | top_synch_666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1040 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1041 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1042 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1043 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1044 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1044 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1045 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u1 | crc_checker_667 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u1) | crc_checker_667 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1039 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u0 | top_synch_668 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u0) | top_synch_668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1033 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1034 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1035 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1036 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1037 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1037 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1038 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u1 | crc_checker_669 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u1) | crc_checker_669 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1032 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u0 | top_synch_670 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u0) | top_synch_670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1026 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1027 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1028 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1029 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1030 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1030 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1031 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u1 | crc_checker_671 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u1) | crc_checker_671 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1025 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u0 | top_synch_672 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u0) | top_synch_672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1020 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1021 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1022 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1023 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1023 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1024 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u1 | crc_checker_673 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u1) | crc_checker_673 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1018 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u0 | top_synch_674 | 274(0.08%) | 25(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u0) | top_synch_674 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1012 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1013 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1014 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1015 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1016 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1016 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1017 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u1 | crc_checker_675 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u1) | crc_checker_675 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1011 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u0 | top_synch_676 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u0) | top_synch_676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1005 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1006 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1007 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1008 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1009 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1009 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1010 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u1 | crc_checker_677 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u1) | crc_checker_677 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1004 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u0 | top_synch_678 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u0) | top_synch_678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_999 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1000 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1001 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1002 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1002 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1003 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u1 | crc_checker_679 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u1) | crc_checker_679 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_997 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u0 | top_synch_680 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u0) | top_synch_680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_991 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_992 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_993 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_994 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_995 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_995 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_996 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u1 | crc_checker_681 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u1) | crc_checker_681 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_990 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u0 | top_synch_682 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u0) | top_synch_682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_984 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_985 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_986 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_987 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_988 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_988 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_989 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u1 | crc_checker_683 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u1) | crc_checker_683 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_983 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u0 | top_synch_684 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u0) | top_synch_684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_977 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_978 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_979 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_980 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_981 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_981 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_982 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u1 | crc_checker_685 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u1) | crc_checker_685 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_976 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u0 | top_synch_686 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u0) | top_synch_686 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_971 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_972 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_973 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_974 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_974 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_975 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u1 | crc_checker_687 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u1) | crc_checker_687 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_969 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u0 | top_synch_688 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u0) | top_synch_688 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_963 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_964 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_965 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_966 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_967 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_967 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_968 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u1 | crc_checker_689 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u1) | crc_checker_689 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_962 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u0 | top_synch_690 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u0) | top_synch_690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_956 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_957 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_958 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_959 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_960 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_960 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_961 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u1 | crc_checker_691 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u1) | crc_checker_691 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_955 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u0 | top_synch_692 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u0) | top_synch_692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_949 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_950 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_951 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_952 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_953 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_953 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_954 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u1 | crc_checker_693 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u1) | crc_checker_693 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_948 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u0 | top_synch_694 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u0) | top_synch_694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_942 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_943 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_944 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_945 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_946 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_946 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_947 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u1 | crc_checker_695 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u1) | crc_checker_695 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_941 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u0 | top_synch_696 | 273(0.08%) | 24(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u0) | top_synch_696 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_935 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_936 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_937 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_938 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_939 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_939 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_940 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u1 | crc_checker_697 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u1) | crc_checker_697 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_934 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[44].u0 | top_synch_702 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[44].u0) | top_synch_702 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_925 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_926 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_927 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_928 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_928 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_929 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[44].u1 | crc_checker_703 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[44].u1) | crc_checker_703 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_923 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[45].u0 | top_synch_704 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[45].u0) | top_synch_704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_917 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_918 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_919 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_920 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_921 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_921 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_922 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[45].u1 | crc_checker_705 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[45].u1) | crc_checker_705 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_916 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[46].u0 | top_synch_706 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[46].u0) | top_synch_706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_911 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_912 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_913 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_914 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_914 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_915 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[46].u1 | crc_checker_707 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[46].u1) | crc_checker_707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_909 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[47].u0 | top_synch_708 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[47].u0) | top_synch_708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_904 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_905 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_906 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_907 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_907 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_908 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[47].u1 | crc_checker_709 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[47].u1) | crc_checker_709 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_902 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u0 | top_synch_710 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u0) | top_synch_710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_896 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_897 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_898 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_899 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_900 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_900 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_901 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u1 | crc_checker_711 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u1) | crc_checker_711 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_895 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u0 | top_synch_712 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u0) | top_synch_712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_889 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_890 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_891 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_892 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_893 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_893 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_894 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u1 | crc_checker_713 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u1) | crc_checker_713 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_888 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u0 | top_synch_714 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u0) | top_synch_714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_882 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_883 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_884 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_885 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_886 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_886 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_887 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u1 | crc_checker_715 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u1) | crc_checker_715 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_881 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u0 | top_synch_716 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u0) | top_synch_716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_875 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_876 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_877 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_878 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_879 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_879 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_880 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u1 | crc_checker_717 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u1) | crc_checker_717 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_874 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u0 | top_synch_718 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u0) | top_synch_718 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_869 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_870 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_871 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_872 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_872 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_873 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u1 | crc_checker_719 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u1) | crc_checker_719 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_867 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u0 | top_synch_720 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u0) | top_synch_720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_861 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_862 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_863 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_864 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_865 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_865 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_866 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u1 | crc_checker_721 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u1) | crc_checker_721 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_860 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u0 | top_synch_722 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u0) | top_synch_722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_854 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_855 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_856 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_857 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_858 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_858 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_859 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u1 | crc_checker_723 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u1) | crc_checker_723 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_853 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u0 | top_synch_724 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u0) | top_synch_724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_847 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_848 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_849 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_850 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_851 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_851 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_852 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u1 | crc_checker_725 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u1) | crc_checker_725 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_846 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u0 | top_synch_726 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u0) | top_synch_726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_840 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_841 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_842 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_843 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_844 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_844 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_845 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u1 | crc_checker_727 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u1) | crc_checker_727 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_839 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u0 | top_synch_728 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u0) | top_synch_728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_833 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_834 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_835 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_836 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_837 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_837 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_838 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u1 | crc_checker_729 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u1) | crc_checker_729 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_832 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u0 | top_synch_730 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u0) | top_synch_730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_827 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_828 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_829 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_830 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_830 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_831 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u1 | crc_checker_731 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u1) | crc_checker_731 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_825 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u0 | top_synch_732 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u0) | top_synch_732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_820 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_821 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_822 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_823 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_823 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_824 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u1 | crc_checker_733 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u1) | crc_checker_733 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_818 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u0 | top_synch_734 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u0) | top_synch_734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_812 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_813 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_814 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_815 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_816 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_816 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_817 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u1 | crc_checker_735 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u1) | crc_checker_735 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_811 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u0 | top_synch_736 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u0) | top_synch_736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_806 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_807 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_808 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_809 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_809 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_810 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u1 | crc_checker_737 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u1) | crc_checker_737 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_804 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u0 | top_synch_738 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u0) | top_synch_738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_799 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_800 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_801 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_802 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_802 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_803 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u1 | crc_checker_739 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u1) | crc_checker_739 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_797 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u0 | top_synch_740 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u0) | top_synch_740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_792 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_793 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_794 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_795 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_795 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_796 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u1 | crc_checker_741 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u1) | crc_checker_741 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_790 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u0 | top_synch_742 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u0) | top_synch_742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_784 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_785 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_786 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_787 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_788 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_788 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_789 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u1 | crc_checker_743 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u1) | crc_checker_743 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_783 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u0 | top_synch_744 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u0) | top_synch_744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_777 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_779 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_780 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_781 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_781 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_782 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u1 | crc_checker_745 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u1) | crc_checker_745 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_776 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u0 | top_synch_746 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u0) | top_synch_746 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_771 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_772 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_773 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_774 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_774 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_775 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u1 | crc_checker_747 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u1) | crc_checker_747 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_769 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u0 | top_synch_748 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u0) | top_synch_748 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_764 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_765 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_766 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_767 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_767 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_768 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u1 | crc_checker_749 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u1) | crc_checker_749 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_762 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u0 | top_synch_750 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u0) | top_synch_750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_756 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_757 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_758 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_759 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_760 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_760 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_761 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u1 | crc_checker_751 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u1) | crc_checker_751 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_755 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u0 | top_synch_752 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u0) | top_synch_752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u1 | crc_checker_753 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u1) | crc_checker_753 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_754 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bcn_cntr | local_bcn_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_A1 | io_delay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_io_delay_selectio_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_A2 | io_delay_HD6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_io_delay_selectio_wiz_HD7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_B1 | io_delay_HD8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_io_delay_selectio_wiz_HD9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_B2 | io_delay_HD10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_io_delay_selectio_wiz_HD11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_BC_A | io_delay2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay2_io_delay2_selectio_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_BC_B | io_delay2_HD18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay2_io_delay2_selectio_wiz_HD19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_BC_C | io_delay2_HD20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay2_io_delay2_selectio_wiz_HD21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_C1 | io_delay_HD12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_io_delay_selectio_wiz_HD13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_C2 | io_delay_HD14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_io_delay_selectio_wiz_HD15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.Merging_Module | IPBusTopMergingModule | 3425(0.99%) | 3344(0.97%) | 0(0.00%) | 81(0.05%) | 10410(1.50%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (GLOBAL_MERGE.Merging_Module) | IPBusTopMergingModule | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_MERGING_REGISTERS | ipbus_ctrlreg_v__parameterized10 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOBMerging | TopSortingModule__parameterized0 | 678(0.20%) | 678(0.20%) | 0(0.00%) | 0(0.00%) | 1540(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOBMerging) | TopSortingModule__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 459(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_599 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_600 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized1 | 229(0.07%) | 229(0.07%) | 0(0.00%) | 0(0.00%) | 458(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_597 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_598 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized1_595 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 460(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized1_595 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo | 109(0.03%) | 109(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_596 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_SYNCH_OFFSET | TOB_synch | 2292(0.66%) | 2292(0.66%) | 0(0.00%) | 0(0.00%) | 8432(1.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inputRAM_1 | ipbus_sorting_outputRAM_wrapper__xdcDup__1 | 59(0.02%) | 43(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_1) | ipbus_sorting_outputRAM_wrapper__xdcDup__1 | 59(0.02%) | 43(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_4_HD497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_4_synth_HD498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inputRAM_2 | ipbus_sorting_outputRAM_wrapper__xdcDup__2 | 74(0.02%) | 58(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_2) | ipbus_sorting_outputRAM_wrapper__xdcDup__2 | 74(0.02%) | 58(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_4_HD504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_4_synth_HD505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inputRAM_3 | ipbus_sorting_outputRAM_wrapper__xdcDup__3 | 69(0.02%) | 53(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_3) | ipbus_sorting_outputRAM_wrapper__xdcDup__3 | 69(0.02%) | 53(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_4_HD511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_4_synth_HD512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inputRAM_4 | ipbus_sorting_outputRAM_wrapper__xdcDup__4 | 56(0.02%) | 40(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_4) | ipbus_sorting_outputRAM_wrapper__xdcDup__4 | 56(0.02%) | 40(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_4_HD518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_4_synth_HD519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | outputRAM | ipbus_sorting_outputRAM_wrapper | 41(0.01%) | 24(0.01%) | 0(0.00%) | 17(0.01%) | 48(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (outputRAM) | ipbus_sorting_outputRAM_wrapper | 41(0.01%) | 24(0.01%) | 0(0.00%) | 17(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.tx_phase_adjust | efex_topo_tx | 186(0.05%) | 182(0.05%) | 0(0.00%) | 4(0.01%) | 227(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GLOBAL_MERGE.tx_phase_adjust) | efex_topo_tx | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 78(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Latome_crc | osum_crc9d32 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_topo_sm | efex_topo_frame_sm | 178(0.05%) | 178(0.05%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_TX_RX | MGT_4_quad_gen | 9993(2.88%) | 9993(2.88%) | 0(0.00%) | 0(0.00%) | 17936(2.59%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__1 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__1 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__1 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_593 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD539 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD540 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD540 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD541 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD541 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD544 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD544 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD545 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD547 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD548 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD552 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD552 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD553 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD554 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD555 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD557 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD558 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD559 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD560 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD561 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD562 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD563 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD564 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD565 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD565 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD566 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD572 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD572 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD574 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD575 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD575 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD576 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD578 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD583 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD583 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD584 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD590 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD590 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD592 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD593 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD593 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD594 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD596 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD597 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD601 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD601 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD602 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD604 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD608 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD608 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD610 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD611 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD611 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD612 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD614 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD615 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD619 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD619 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD620 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD622 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD626 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD630 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[10].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__11 | 621(0.18%) | 621(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__11 | 621(0.18%) | 621(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__11 | 621(0.18%) | 621(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_590 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD723 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD724 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD724 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD725 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD725 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD728 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD728 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD729 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD731 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD736 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD736 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD738 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD739 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD742 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD743 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD745 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD746 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD748 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD749 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD749 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD750 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD756 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD756 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD758 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD759 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD759 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD760 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD762 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD767 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD767 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD768 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD774 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD774 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD776 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD777 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD777 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD780 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD781 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD785 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD785 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD786 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD792 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD792 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD794 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD795 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD795 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD796 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD798 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD799 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD803 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD803 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD804 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD810 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD812 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD814 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[14].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__12 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__12 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__12 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__12 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_587 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD815 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD816 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD816 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD817 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD817 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD820 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD820 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD821 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD823 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD824 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD828 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD828 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD830 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD831 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD832 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD833 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD834 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD835 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD836 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD837 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD839 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD840 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD841 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD841 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD842 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD848 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD848 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD850 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD851 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD851 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD852 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD854 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD855 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD859 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD859 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD860 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD862 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD866 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD866 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD868 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD869 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD869 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD870 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD872 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD873 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD877 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD877 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD878 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD880 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD884 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD884 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD886 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD887 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD887 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD888 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD890 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD891 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD895 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD895 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD896 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD902 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD904 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD906 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[15].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__13 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__13 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__13 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__13 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_584 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD907 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD908 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD908 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD909 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD909 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD911 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD912 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD912 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD913 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD915 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD916 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD920 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD920 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD921 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD922 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD923 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD924 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD926 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD927 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD928 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD929 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD930 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD931 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD932 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD933 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD933 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD934 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD936 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD940 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD940 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD942 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD943 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD943 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD944 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD946 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD947 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD951 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD951 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD952 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD954 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD958 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD958 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD960 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD961 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD961 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD962 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD964 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD969 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD969 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD970 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD972 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD976 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD976 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD978 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD979 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD979 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD980 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD982 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD983 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD987 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD987 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD988 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD994 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD995 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD996 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD997 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD998 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[17].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__14 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__14 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__14 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__14 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_581 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD999 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1000 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1000 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1001 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1004 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1004 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1005 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1007 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1008 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1012 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1012 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1013 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1014 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1015 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1018 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1019 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1020 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1021 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1022 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1023 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1024 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1025 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1025 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1026 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1028 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1032 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1032 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1034 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1035 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1035 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1036 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1038 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1043 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1043 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1044 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1050 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1050 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1052 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1053 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1053 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1054 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1056 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1057 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1061 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1061 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1062 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1064 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1068 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1068 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1070 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1071 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1071 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1072 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1074 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1079 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1079 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1080 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1086 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1088 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1089 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1090 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[18].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__15 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__15 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__15 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__15 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_578 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1091 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1092 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1092 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1093 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1093 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1096 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1096 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1097 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1099 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1100 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1104 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1104 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1105 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1106 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1109 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1110 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1111 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1112 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1113 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1116 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1117 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1117 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1118 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1120 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1124 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1124 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1127 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1127 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1128 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1130 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1135 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1135 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1136 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1142 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1142 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1144 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1145 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1145 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1146 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1148 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1153 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1153 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1154 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1156 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1160 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1160 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1162 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1163 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1163 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1164 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1166 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1167 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1171 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1171 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1172 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1178 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1179 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1180 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1182 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[19].mgt_1quad_Rx_Tx | mgt_selection_wrapper | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_575 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[1].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__2 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__2 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__2 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__2 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_572 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1183 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1184 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1184 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1185 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1185 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1187 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1188 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1188 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1189 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1191 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1196 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1196 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1198 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1199 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1201 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1202 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1203 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1204 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1205 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1208 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1209 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1209 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1210 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1216 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1216 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1218 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1219 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1219 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1220 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1222 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1223 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1227 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1227 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1228 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1234 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1234 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1236 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1237 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1237 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1238 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1240 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1241 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1245 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1245 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1246 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1252 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1252 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1254 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1255 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1255 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1256 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1258 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1259 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1263 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1263 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1264 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1266 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1270 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1272 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1274 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[2].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__3 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__3 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__3 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_569 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1275 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1276 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1276 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1277 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1277 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1279 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1280 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1280 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1281 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1283 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1288 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1288 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1289 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1290 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1291 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1293 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1294 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1295 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1296 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1297 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1299 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1300 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1301 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1301 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1302 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1304 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1308 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1308 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1310 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1311 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1311 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1312 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1314 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1319 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1319 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1320 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1326 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1326 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1328 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1329 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1329 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1330 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1332 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1337 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1337 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1338 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1340 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1344 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1344 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1346 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1347 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1347 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1348 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1350 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1351 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1355 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1355 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1356 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1362 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1363 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1366 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[3].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__4 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__4 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__4 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__4 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_566 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1367 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1368 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1368 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1369 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1372 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1372 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1373 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1375 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1376 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1380 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1380 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1382 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1383 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1384 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1385 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1386 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1387 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1388 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1389 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1390 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1391 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1392 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1393 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1393 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1394 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1396 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1400 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1400 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1402 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1403 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1403 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1404 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1406 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1407 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1411 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1411 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1412 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1414 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1418 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1418 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1420 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1421 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1421 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1422 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1424 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1425 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1429 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1429 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1430 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1436 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1436 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1438 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1439 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1439 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1440 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1442 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1443 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1447 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1447 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1448 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1450 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1454 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1455 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1456 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1457 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1458 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[4].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__5 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__5 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__5 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__5 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_563 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1459 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1460 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1460 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1461 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1461 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1463 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1464 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1464 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1465 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1467 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1472 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1472 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1473 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1474 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1475 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1476 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1477 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1478 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1479 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1480 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1481 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1482 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1483 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1484 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1485 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1485 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1486 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1488 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1492 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1492 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1494 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1495 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1495 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1498 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1503 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1503 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1504 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1510 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1510 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1512 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1513 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1513 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1514 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1516 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1517 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1521 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1521 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1522 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1524 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1528 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1528 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1530 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1531 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1531 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1532 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1534 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1535 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1539 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1539 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1540 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1546 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1548 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1549 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1550 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[5].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__6 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__6 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__6 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_560 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1551 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1552 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1552 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1553 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1553 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1556 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1556 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1557 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1559 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1560 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1564 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1564 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1565 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1566 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1567 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1569 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1570 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1571 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1572 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1573 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1574 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1575 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1576 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1577 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1577 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1578 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1584 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1584 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1586 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1587 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1587 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1588 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1590 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1591 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1595 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1595 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1596 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1602 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1602 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1604 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1605 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1605 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1606 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1608 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1613 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1613 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1614 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1616 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1620 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1620 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1622 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1623 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1623 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1624 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1626 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1631 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1631 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1632 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1638 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1639 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1642 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[6].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__7 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__7 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__7 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_557 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1643 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1644 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1644 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1645 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1645 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1647 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1648 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1648 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1649 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1651 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1652 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1656 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1656 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1657 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1658 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1659 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1661 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1662 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1663 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1664 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1665 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1667 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1669 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1669 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1670 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1676 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1676 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1678 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1679 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1679 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1680 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1682 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1687 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1687 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1688 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1694 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1694 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1696 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1697 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1697 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1698 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1700 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1705 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1705 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1706 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1712 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1714 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1715 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1715 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1716 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1718 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1723 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1723 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1724 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1730 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1733 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1734 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[7].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__8 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__8 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__8 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_554 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1735 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1736 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1736 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1737 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1737 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1740 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1740 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1741 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1743 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1748 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1748 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1749 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1750 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1751 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1753 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1754 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1756 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1757 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1758 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1759 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1760 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1761 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1761 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1762 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1764 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1768 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1768 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1770 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1771 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1771 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1772 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1774 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1779 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1779 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1780 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1782 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1786 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1786 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1788 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1789 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1789 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1790 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1792 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1797 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1797 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1798 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1804 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1804 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1806 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1807 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1807 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1808 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1810 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1815 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1815 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1816 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1822 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1823 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1824 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1826 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[8].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__9 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__9 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__9 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__9 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_551 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1827 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1828 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1828 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1829 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1829 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1831 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1832 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1832 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1833 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1835 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1836 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1840 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1840 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1841 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1842 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1843 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1846 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1847 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1848 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1849 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1851 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1852 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1853 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1853 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1854 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1860 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1860 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1862 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1863 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1863 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1864 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1866 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1871 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1871 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1872 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1878 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1878 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1880 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1881 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1881 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1882 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1884 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1889 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1889 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1890 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1896 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1896 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1898 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1899 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1899 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1900 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1902 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1907 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1907 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1908 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1914 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1915 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1916 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1917 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1918 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[9].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__10 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__10 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__10 | 627(0.18%) | 627(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__10 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD631 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD632 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD632 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD633 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD633 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD635 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD636 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD636 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD637 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD639 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD644 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD644 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD646 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD647 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD649 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD652 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD656 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD657 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD657 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD658 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD664 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD664 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD666 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD667 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD667 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD670 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD675 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD675 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD676 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD682 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD682 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD684 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD685 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD685 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD686 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD688 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD693 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD693 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD694 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD700 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD700 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD702 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD703 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD703 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD704 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD706 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD711 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD711 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD712 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD718 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD721 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD722 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_ipb | mgt_slaves | 35795(10.33%) | 35795(10.33%) | 0(0.00%) | 0(0.00%) | 8589(1.24%) | 512(43.39%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[0].quad | mgt_quad_slaves__xdcDup__1 | 2463(0.71%) | 2463(0.71%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[0].quad) | mgt_quad_slaves__xdcDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__1 | 568(0.16%) | 568(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_545 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_546 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_547 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_548 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__1 | 527(0.15%) | 527(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__1 | 519(0.15%) | 519(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_549 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__2 | 567(0.16%) | 567(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_540 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_541 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_542 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_543 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__2 | 526(0.15%) | 526(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__2 | 518(0.15%) | 518(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_544 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__3 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_535 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_536 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_537 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_538 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__3 | 579(0.17%) | 579(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__3 | 571(0.16%) | 571(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_539 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__4 | 667(0.19%) | 667(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_530 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_531 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_532 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_533 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__4 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__4 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_534 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_523 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_525 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[10].quad | mgt_quad_slaves__xdcDup__11 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 395(0.06%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[10].quad) | mgt_quad_slaves__xdcDup__11 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__41 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_519 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_520 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_521 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__41 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_522 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__42 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_515 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_516 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_517 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__42 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__42 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_518 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__43 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_511 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_512 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_513 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__43 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__43 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_514 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__44 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_507 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_508 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_509 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__44 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__44 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_510 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_502 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_504 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_505 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[14].quad | mgt_quad_slaves__xdcDup__12 | 1287(0.37%) | 1287(0.37%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[14].quad) | mgt_quad_slaves__xdcDup__12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__57 | 391(0.11%) | 391(0.11%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_495 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_496 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_497 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_498 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__57 | 350(0.10%) | 350(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__57 | 342(0.10%) | 342(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_499 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__58 | 437(0.13%) | 437(0.13%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_490 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_491 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_492 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_493 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__58 | 396(0.11%) | 396(0.11%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__58 | 388(0.11%) | 388(0.11%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_494 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__59 | 347(0.10%) | 347(0.10%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_485 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_486 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_487 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_488 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__59 | 306(0.09%) | 306(0.09%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__59 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_489 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__60 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_480 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_481 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_482 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_483 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__60 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__60 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_484 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_473 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_475 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_477 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_478 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_479 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[15].quad | mgt_quad_slaves__xdcDup__13 | 320(0.09%) | 320(0.09%) | 0(0.00%) | 0(0.00%) | 526(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[15].quad) | mgt_quad_slaves__xdcDup__13 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__61 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_468 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_469 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_470 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_471 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__61 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__61 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_472 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__62 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_463 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_464 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_465 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_466 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__62 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__62 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_467 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__63 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_458 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_459 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_460 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_461 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__63 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__63 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_462 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__64 | 77(0.02%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_453 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_454 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_455 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_456 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__64 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__64 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_457 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_446 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_448 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_450 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_451 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_452 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[17].quad | mgt_quad_slaves__xdcDup__14 | 1663(0.48%) | 1663(0.48%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[17].quad) | mgt_quad_slaves__xdcDup__14 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__69 | 563(0.16%) | 563(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_441 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_442 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_443 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_444 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__69 | 521(0.15%) | 521(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__69 | 513(0.15%) | 513(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_445 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__70 | 390(0.11%) | 390(0.11%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_436 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_437 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_438 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_439 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__70 | 348(0.10%) | 348(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__70 | 339(0.10%) | 339(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_440 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__71 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_431 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_432 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_433 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_434 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__71 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__71 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_435 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__72 | 571(0.16%) | 571(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_426 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_427 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_428 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_429 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__72 | 523(0.15%) | 523(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__72 | 515(0.15%) | 515(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_430 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_419 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_421 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_425 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[18].quad | mgt_quad_slaves__xdcDup__15 | 1198(0.35%) | 1198(0.35%) | 0(0.00%) | 0(0.00%) | 534(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[18].quad) | mgt_quad_slaves__xdcDup__15 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__73 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_414 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_415 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_416 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_417 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__73 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__73 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_418 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__74 | 329(0.09%) | 329(0.09%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_409 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_410 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_411 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_412 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__74 | 288(0.08%) | 288(0.08%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__74 | 280(0.08%) | 280(0.08%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_413 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__75 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_404 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_405 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_406 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_407 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__75 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__75 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_408 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__76 | 687(0.20%) | 687(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_399 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_400 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_401 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_402 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__76 | 639(0.18%) | 639(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__76 | 631(0.18%) | 631(0.18%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_403 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_392 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_394 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_396 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_397 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_398 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[19].quad | mgt_quad_slaves | 693(0.20%) | 693(0.20%) | 0(0.00%) | 0(0.00%) | 530(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[19].quad) | mgt_quad_slaves | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__77 | 454(0.13%) | 454(0.13%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_387 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_388 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_389 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_390 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__77 | 407(0.12%) | 407(0.12%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__77 | 399(0.12%) | 399(0.12%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD1998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD1999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_391 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__78 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_382 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_383 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_384 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_385 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__78 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__78 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_386 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__79 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_377 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_378 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_379 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_380 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__79 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__79 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_381 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_372 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_373 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_374 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_375 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_376 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_365 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_368 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[1].quad | mgt_quad_slaves__xdcDup__2 | 2482(0.72%) | 2482(0.72%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[1].quad) | mgt_quad_slaves__xdcDup__2 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__5 | 651(0.19%) | 651(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_360 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_361 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_362 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_363 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__5 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__5 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_364 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__6 | 650(0.19%) | 650(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_355 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_356 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_357 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_358 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__6 | 609(0.18%) | 609(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__6 | 601(0.17%) | 601(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_359 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__7 | 561(0.16%) | 561(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_350 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_351 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_352 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_353 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__7 | 519(0.15%) | 519(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__7 | 511(0.15%) | 511(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_354 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__8 | 603(0.17%) | 603(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_345 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_346 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_347 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_348 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__8 | 555(0.16%) | 555(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__8 | 547(0.16%) | 547(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_349 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_338 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_340 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_342 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_344 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[2].quad | mgt_quad_slaves__xdcDup__3 | 3042(0.88%) | 3042(0.88%) | 0(0.00%) | 0(0.00%) | 554(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[2].quad) | mgt_quad_slaves__xdcDup__3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__9 | 654(0.19%) | 654(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_333 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_334 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_335 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_336 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__9 | 613(0.18%) | 613(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__9 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_337 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__10 | 588(0.17%) | 588(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_328 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_329 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_330 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_331 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__10 | 547(0.16%) | 547(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__10 | 539(0.16%) | 539(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_332 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__11 | 875(0.25%) | 875(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_323 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_324 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_325 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_326 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__11 | 834(0.24%) | 834(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__11 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_327 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__12 | 879(0.25%) | 879(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_318 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_319 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_320 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_321 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__12 | 831(0.24%) | 831(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__12 | 823(0.24%) | 823(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_322 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_311 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_313 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_317 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[3].quad | mgt_quad_slaves__xdcDup__4 | 3601(1.04%) | 3601(1.04%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[3].quad) | mgt_quad_slaves__xdcDup__4 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__13 | 886(0.26%) | 886(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_306 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_307 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_308 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_309 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__13 | 844(0.24%) | 844(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__13 | 835(0.24%) | 835(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_310 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__14 | 883(0.25%) | 883(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_301 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_302 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_303 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_304 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__14 | 842(0.24%) | 842(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__14 | 834(0.24%) | 834(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_305 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__15 | 897(0.26%) | 897(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_296 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_297 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_298 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_299 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__15 | 856(0.25%) | 856(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__15 | 848(0.24%) | 848(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_300 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__16 | 890(0.26%) | 890(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_291 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_292 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_293 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_294 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__16 | 842(0.24%) | 842(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__16 | 834(0.24%) | 834(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_295 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_284 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_286 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_288 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_289 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_290 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[4].quad | mgt_quad_slaves__xdcDup__5 | 3708(1.07%) | 3708(1.07%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[4].quad) | mgt_quad_slaves__xdcDup__5 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__17 | 888(0.26%) | 888(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_279 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_280 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_281 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_282 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__17 | 845(0.24%) | 845(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__17 | 837(0.24%) | 837(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_283 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__18 | 960(0.28%) | 960(0.28%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_274 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_275 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_276 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_277 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__18 | 917(0.26%) | 917(0.26%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__18 | 908(0.26%) | 908(0.26%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_278 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__19 | 887(0.26%) | 887(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_269 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_270 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_271 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_272 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__19 | 844(0.24%) | 844(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__19 | 835(0.24%) | 835(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_273 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__20 | 924(0.27%) | 924(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_264 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_265 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_266 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_267 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__20 | 874(0.25%) | 874(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__20 | 865(0.25%) | 865(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_268 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_257 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_259 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_261 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[5].quad | mgt_quad_slaves__xdcDup__6 | 3723(1.07%) | 3723(1.07%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[5].quad) | mgt_quad_slaves__xdcDup__6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__21 | 952(0.27%) | 952(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_252 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_253 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_254 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_255 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__21 | 909(0.26%) | 909(0.26%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__21 | 900(0.26%) | 900(0.26%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_256 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__22 | 931(0.27%) | 931(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_247 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_248 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_249 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_250 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__22 | 888(0.26%) | 888(0.26%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__22 | 879(0.25%) | 879(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_251 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__23 | 892(0.26%) | 892(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_242 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_243 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_244 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_245 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__23 | 851(0.25%) | 851(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__23 | 842(0.24%) | 842(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_246 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__24 | 900(0.26%) | 900(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_237 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_238 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_239 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_240 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__24 | 850(0.25%) | 850(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__24 | 841(0.24%) | 841(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_241 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_230 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_232 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[6].quad | mgt_quad_slaves__xdcDup__7 | 3516(1.02%) | 3516(1.02%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[6].quad) | mgt_quad_slaves__xdcDup__7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__25 | 863(0.25%) | 863(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_225 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_226 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_227 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_228 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__25 | 822(0.24%) | 822(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__25 | 814(0.23%) | 814(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_229 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__26 | 865(0.25%) | 865(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_220 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_221 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_222 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_223 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__26 | 824(0.24%) | 824(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__26 | 816(0.24%) | 816(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_224 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__27 | 869(0.25%) | 869(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_215 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_216 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_217 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_218 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__27 | 828(0.24%) | 828(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__27 | 820(0.24%) | 820(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_219 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__28 | 874(0.25%) | 874(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_210 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_211 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_212 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_213 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__28 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__28 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_214 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_203 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_205 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[7].quad | mgt_quad_slaves__xdcDup__8 | 2994(0.86%) | 2994(0.86%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[7].quad) | mgt_quad_slaves__xdcDup__8 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__29 | 868(0.25%) | 868(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_198 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_199 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_200 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_201 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__29 | 827(0.24%) | 827(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__29 | 819(0.24%) | 819(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_202 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__30 | 862(0.25%) | 862(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_193 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_194 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_195 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_196 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__30 | 821(0.24%) | 821(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__30 | 813(0.23%) | 813(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_197 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__31 | 578(0.17%) | 578(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_188 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_189 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_190 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_191 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__31 | 537(0.16%) | 537(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__31 | 529(0.15%) | 529(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_192 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__32 | 639(0.18%) | 639(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_183 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_184 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_185 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_186 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__32 | 591(0.17%) | 591(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__32 | 583(0.17%) | 583(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_187 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_176 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_178 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_180 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_182 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[8].quad | mgt_quad_slaves__xdcDup__9 | 2493(0.72%) | 2493(0.72%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[8].quad) | mgt_quad_slaves__xdcDup__9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__33 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_171 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_172 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_173 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_174 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__33 | 571(0.16%) | 571(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__33 | 563(0.16%) | 563(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_175 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__34 | 691(0.20%) | 691(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_166 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_167 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_168 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_169 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__34 | 650(0.19%) | 650(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__34 | 642(0.19%) | 642(0.19%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_170 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__35 | 564(0.16%) | 564(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_161 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_162 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_163 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_164 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__35 | 523(0.15%) | 523(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__35 | 515(0.15%) | 515(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_165 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__36 | 591(0.17%) | 591(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_156 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_157 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_158 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_159 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__36 | 543(0.16%) | 543(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__36 | 535(0.15%) | 535(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_160 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_149 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_151 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_155 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[9].quad | mgt_quad_slaves__xdcDup__10 | 2540(0.73%) | 2540(0.73%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[9].quad) | mgt_quad_slaves__xdcDup__10 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__37 | 573(0.17%) | 573(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_144 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_145 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_146 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_147 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__37 | 532(0.15%) | 532(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__37 | 524(0.15%) | 524(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_148 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__38 | 547(0.16%) | 547(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_139 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_140 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_141 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_142 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__38 | 506(0.15%) | 506(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__38 | 498(0.14%) | 498(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_143 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__39 | 692(0.20%) | 692(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_134 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_135 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_136 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_137 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__39 | 651(0.19%) | 651(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__39 | 643(0.19%) | 643(0.19%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_138 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__40 | 695(0.20%) | 695(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_131 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_132 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_133 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__40 | 647(0.19%) | 647(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__40 | 639(0.18%) | 639(0.18%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_125 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_127 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READOUT_IF.Readout_block | Readout_logic_top | 15318(4.42%) | 15252(4.40%) | 0(0.00%) | 66(0.04%) | 51499(7.43%) | 172(14.58%) | 83(3.52%) | 0(0.00%) | | (READOUT_IF.Readout_block) | Readout_logic_top | 16(0.01%) | 15(0.01%) | 0(0.00%) | 1(0.01%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_ECR_debug_counter | cntr_generic | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_L1A_debug_counter | cntr_generic_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_RAW_busy | cntr_generic_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOB_LO_fifo_tidemark | tide_mark_block | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOB_busy | cntr_generic_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOBs_readout | TOBs_rdout | 6323(1.83%) | 6260(1.81%) | 0(0.00%) | 63(0.04%) | 15268(2.20%) | 112(9.49%) | 33(1.40%) | 0(0.00%) | | (U0_TOBs_readout) | TOBs_rdout | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_FIFO_BCN_L1A | FIFO_47b_512_HD3658 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_5_HD3659 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_5_synth_HD3660 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top_HD3661 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo_HD3662 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs_HD3663 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs_HD3663 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray_HD3664 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2_HD3665 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic_HD3666 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as_HD3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as_HD3668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as_HD3668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1_HD3669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2_HD3670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr_HD3672 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic_HD3673 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as_HD3674 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as_HD3675 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as_HD3675 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_HD3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0_HD3677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr_HD3678 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory_HD3679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_4_HD3680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_4_synth_HD3681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top_HD3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr_HD3683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width_HD3684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper_HD3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo_HD3686 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo_HD3686 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst_HD3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single_HD3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2_HD3689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1_HD3690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_flag_fsm | busy_flag_fsm_98 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_TOB_SPY_mem | ipbus_dpram_99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3_100 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOB_sorting_gen.U1_TOBs_sorting | T_TOBs_sorting | 135(0.04%) | 127(0.04%) | 0(0.00%) | 8(0.01%) | 529(0.08%) | 6(0.51%) | 0(0.00%) | 0(0.00%) | | (U1_TOB_sorting_gen.U1_TOBs_sorting) | T_TOBs_sorting | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_eg | SIPO_TOPO_TOBs_unit | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 206(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_eg) | SIPO_TOPO_TOBs_unit | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 199(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOB_BCN_Delay | GeneralDelay | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO_123 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U3_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO_123 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b_124 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_T_TOB_DRP | DPR_209b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_209b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_209b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_209b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_209b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_209b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_209b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_209b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_209b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_209b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_209b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U5_T_TOBs_fifo | FIFO_209b_512 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_209b_512_fifo_generator_v13_2_5 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_209b_512_fifo_generator_v13_2_5_synth | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_209b_512_fifo_generator_top | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_209b_512_fifo_generator_ramfifo | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_209b_512_rd_logic | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_209b_512_dc_ss | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_209b_512_updn_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_209b_512_rd_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_209b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_209b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_209b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_209b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_209b_512_wr_logic | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_209b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_209b_512_wr_status_flags_ss | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_209b_512_wr_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_209b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_209b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_209b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_209b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_209b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_209b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_209b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_209b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_209b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_209b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_209b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_209b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_209b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_209b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_209b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U1_gen_sync_280 | gen_sync_280M_101 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOBs_eg_sorting | XTOBs_sorting__xdcDup__1 | 685(0.20%) | 656(0.19%) | 0(0.00%) | 29(0.02%) | 4716(0.68%) | 48(4.07%) | 16(0.68%) | 0(0.00%) | | (U2_XTOBs_eg_sorting) | XTOBs_sorting__xdcDup__1 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 1967(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit_113 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_252b_512_HD3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_252b_512_HD4244 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4245 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4246 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4247 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4248 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4249 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4249 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4250 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4251 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4252 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_252b_512_rd_dc_as_HD4253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4254 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4258 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4259 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4262 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4264 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4265 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4266 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4267 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4268 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4269 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4270 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4277 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4277 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4278 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4279 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4279 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_252b_512_HD3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_252b_512_HD4284 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4285 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4286 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4287 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4288 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4289 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4289 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4290 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4291 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4292 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4294 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4294 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4295 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4298 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4299 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4302 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4302 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4304 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4305 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4306 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4307 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4308 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4309 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4310 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4317 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4317 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4318 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4319 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4319 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_252b_512_HD3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_252b_512_HD4324 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4325 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4326 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4327 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4328 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4329 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4329 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4330 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4331 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4332 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4334 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4334 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4335 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4338 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4339 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4342 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4342 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4344 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4345 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4346 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4347 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4348 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4349 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4350 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4357 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4357 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4358 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4359 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4359 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_252b_512_HD3884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_252b_512_HD4364 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4365 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4366 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4367 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4368 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4369 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4369 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4370 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4371 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4372 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4374 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4374 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4375 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4378 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4379 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4382 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4384 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4385 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4386 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4387 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4388 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4389 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4390 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4397 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4397 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4398 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4399 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4399 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_252b_512_HD3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_252b_512_HD4404 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4405 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4406 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4407 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4408 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4409 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4409 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4410 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4411 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4412 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4414 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4414 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_252b_512_rd_handshaking_flags_HD4417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4418 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4419 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_252b_512_wr_pf_as_HD4420 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4422 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4422 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4425 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4426 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4427 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4428 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4429 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4430 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4437 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4437 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4438 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4439 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4439 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_252b_512_HD3910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_252b_512_HD4444 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4445 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4446 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4447 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4448 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4449 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4449 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4450 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4451 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4452 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4454 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4454 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4455 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4458 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4459 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4462 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4462 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4464 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4465 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4466 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4467 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4468 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4469 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4470 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4477 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4477 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4478 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4479 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4479 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_252b_512_HD3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_252b_512_HD4484 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4485 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4486 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4487 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4488 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4489 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4489 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4490 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4491 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4492 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4494 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4494 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4495 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4498 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4499 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4502 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4504 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4505 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4506 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4507 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4508 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4509 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4510 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4517 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4517 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4518 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4519 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4519 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_252b_512_HD3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_252b_512_HD4524 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4525 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4526 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4527 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4528 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4529 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4529 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4530 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4531 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4532 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4534 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4534 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4535 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4538 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4539 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4542 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4542 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4545 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4546 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4547 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4548 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4549 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4550 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4557 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4557 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4558 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4559 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4559 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO_121 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO_121 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b_122 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_BCN_Delay | GeneralDelay__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOBs_tau_sorting | XTOBs_sorting | 677(0.20%) | 652(0.19%) | 0(0.00%) | 25(0.01%) | 4939(0.71%) | 48(4.07%) | 16(0.68%) | 0(0.00%) | | (U3_XTOBs_tau_sorting) | XTOBs_sorting | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1966(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 195(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_252b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_252b_512 | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5 | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_252b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 197(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_252b_512_HD3754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_252b_512_HD3964 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD3965 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD3966 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3967 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3968 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3969 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3969 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3970 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3971 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3972 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3974 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3974 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3978 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3979 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3982 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3982 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3984 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3985 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3986 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD3987 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD3988 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3989 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3990 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3997 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3997 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3998 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3999 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3999 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_252b_512_HD3767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_252b_512_HD4004 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4005 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4006 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4007 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4008 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4009 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4009 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4010 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4011 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4012 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4014 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4014 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4015 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4018 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4019 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4022 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4022 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4024 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4025 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4026 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4027 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4028 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4029 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4030 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4037 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4037 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4038 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4039 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4039 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_252b_512_HD3780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_252b_512_HD4044 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4045 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4046 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4047 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4048 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4049 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4049 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4050 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4051 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4052 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4054 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4054 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4055 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4058 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4059 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4062 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4062 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4064 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4065 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4066 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4067 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4068 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4069 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4070 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4077 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4077 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4078 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4079 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4079 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_252b_512_HD3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_252b_512_HD4084 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4085 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4086 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4087 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4088 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4089 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4089 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4090 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4091 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4092 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4094 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4094 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4098 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4099 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_252b_512_wr_pf_as_HD4100 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4102 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4104 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4105 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4106 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4107 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4108 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4109 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4110 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4117 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4117 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4118 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4119 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4119 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 197(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_252b_512_HD3806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_252b_512_HD4124 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4125 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4126 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4127 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4128 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4129 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4129 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4130 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4131 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4132 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4134 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4134 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4138 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4139 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4142 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4142 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4145 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4146 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4147 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4148 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4149 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4150 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4157 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4157 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4158 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4159 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4159 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_252b_512_HD3819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_252b_512_HD4164 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4165 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4166 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4167 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4168 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4169 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4169 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4170 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4171 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4172 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4174 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4174 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4175 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4178 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4179 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4182 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4182 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4185 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4186 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4187 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4188 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4189 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4190 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4197 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4197 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4198 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4199 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4199 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_252b_512_HD3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_252b_512_HD4204 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4205 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4206 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4207 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4208 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4209 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4209 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4210 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4211 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4212 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4214 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4214 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4215 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4218 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4219 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4222 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4222 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4224 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4225 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4226 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4227 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4228 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4229 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4230 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4237 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4237 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4238 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4239 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4239 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_rd_mux_fsm | fsm_TOBs_to_muxPISO | 4503(1.30%) | 4503(1.30%) | 0(0.00%) | 0(0.00%) | 4443(0.64%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U6_rd_mux_fsm) | fsm_TOBs_to_muxPISO | 4482(1.29%) | 4482(1.29%) | 0(0.00%) | 0(0.00%) | 4414(0.64%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_TOB_payld_length | cntr_generic__parameterized2_104 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_T_TOB_cntr | cntr_generic__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_eg_cntr | cntr_generic__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_tau_cntr | cntr_generic__parameterized1_105 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO | FIFO_33b_8192_HD3692 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_5_HD3693 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_5_synth_HD3694 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top_HD3695 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo_HD3696 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs_HD3697 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs_HD3697 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray_HD3698 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2_HD3699 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic_HD3700 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as_HD3701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as_HD3702 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as_HD3702 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2_HD3703 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3_HD3704 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr_HD3706 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic_HD3707 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as_HD3708 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_33b_8192_wr_dc_as_HD3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as_HD3710 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as_HD3710 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_HD3711 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1_HD3712 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr_HD3713 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory_HD3714 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_4_HD3715 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_4_synth_HD3716 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top_HD3717 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr_HD3718 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec_HD3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0_HD3720 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0_HD3721 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width_HD3722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper_HD3723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0_HD3724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0_HD3725 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1_HD3726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1_HD3727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2_HD3728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2_HD3729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3_HD3730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3_HD3731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4_HD3732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4_HD3733 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5_HD3734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5_HD3735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6_HD3736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6_HD3737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo_HD3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_TOB_Link_output_FIFO_FSM | FIFO_to_MGT_TOB_FSM | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_clk_closs_pulse | clk_closs_pulse_fsm_102 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_frame_counter | cntr_up_dn_generic_103 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_raw_duration_counter | cntr_generic_9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_tob_duration_counter | cntr_generic_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_real_time_40m_counter | cntr_generic_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_tob_bcn_tidemark | tide_mark_block_12 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_xtob_data_tidemark | tide_mark_block_13 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_bcn_l1a_valid_checker | bcn_l1a_valid_checker | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 350(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U17_bcn_l1a_valid_checker) | bcn_l1a_valid_checker | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 222(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_mismatch_cntr_block | cntr_generic__parameterized4 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_parity_err_cntr_block | cntr_generic__parameterized4_95 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_mismatch_cntr_block | cntr_generic__parameterized4_96 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_parity_err_cntr_block | cntr_generic__parameterized4_97 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_LO_fifo_tidemark | tide_mark_block_14 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_bcn_tidemark | tide_mark_block_15 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_data_tidemark | tide_mark_block_16 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_readout | RAW_data_rdout | 8302(2.40%) | 8300(2.40%) | 0(0.00%) | 2(0.01%) | 34496(4.98%) | 60(5.08%) | 50(2.12%) | 0(0.00%) | | (U1_RAW_readout) | RAW_data_rdout | 86(0.02%) | 85(0.02%) | 0(0.00%) | 1(0.01%) | 15106(2.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U1_gen_sync_280 | gen_sync_280M | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U2_PISO_RAW | PISO_RAW_data | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U3_DPRAM_RAW_Data | DPR_36b_1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U4_FIFO_RAW_Data | FIFO_36b_512 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[10].U2_PISO_RAW | PISO_RAW_data_47 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U4_FIFO_RAW_Data | FIFO_36b_512_HD4996 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD4997 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD4998 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4999 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5000 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5001 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5005 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5005 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5007 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5008 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5009 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5010 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5011 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5011 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5013 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5014 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5015 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[11].U2_PISO_RAW | PISO_RAW_data_48 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U4_FIFO_RAW_Data | FIFO_36b_512_HD5024 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5025 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5026 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5027 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5028 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5029 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5033 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5033 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5035 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5036 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5037 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5038 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5039 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5039 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5041 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5043 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[12].U2_PISO_RAW | PISO_RAW_data_49 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U4_FIFO_RAW_Data | FIFO_36b_512_HD5052 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5053 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5054 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5055 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5056 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5057 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5061 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5061 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5063 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5064 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5065 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5066 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5067 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5067 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5069 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5071 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[13].U2_PISO_RAW | PISO_RAW_data_50 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U4_FIFO_RAW_Data | FIFO_36b_512_HD5080 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5081 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5082 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5083 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5084 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5085 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5089 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5089 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5092 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5093 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5094 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5095 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5095 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5097 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5098 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5099 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[14].U2_PISO_RAW | PISO_RAW_data_51 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U4_FIFO_RAW_Data | FIFO_36b_512_HD5108 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5109 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5110 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5111 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5112 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5113 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5117 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5117 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5119 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5120 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5121 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5122 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5123 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5123 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5125 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5127 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[15].U2_PISO_RAW | PISO_RAW_data_52 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U4_FIFO_RAW_Data | FIFO_36b_512_HD5136 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5137 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5138 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5139 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5140 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5141 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5145 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5145 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5148 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5149 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5150 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5151 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5151 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5155 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[16].U2_PISO_RAW | PISO_RAW_data_53 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U4_FIFO_RAW_Data | FIFO_36b_512_HD5164 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5165 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5166 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5167 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5168 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5169 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5173 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5173 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5175 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5176 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5177 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5178 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5179 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5179 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5182 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5183 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[17].U2_PISO_RAW | PISO_RAW_data_54 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U4_FIFO_RAW_Data | FIFO_36b_512_HD5192 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5193 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5194 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5195 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5196 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5197 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5201 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5201 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5203 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5204 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5205 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5206 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5207 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5207 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5211 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[18].U2_PISO_RAW | PISO_RAW_data_55 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U4_FIFO_RAW_Data | FIFO_36b_512_HD5220 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5221 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5222 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5223 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5224 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5225 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5229 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5229 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5231 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5232 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5233 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5234 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5235 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5235 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5239 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[19].U2_PISO_RAW | PISO_RAW_data_56 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U4_FIFO_RAW_Data | FIFO_36b_512_HD5248 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5249 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5250 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5251 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5252 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5253 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5257 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5257 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5259 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5260 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5261 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5262 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5263 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5263 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5265 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5266 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5267 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[1].U2_PISO_RAW | PISO_RAW_data_57 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U4_FIFO_RAW_Data | FIFO_36b_512_HD5276 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5277 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5278 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5279 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5280 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5281 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5285 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5285 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5287 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5288 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5289 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5290 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5291 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5291 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5293 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5294 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5295 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[20].U2_PISO_RAW | PISO_RAW_data_58 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U4_FIFO_RAW_Data | FIFO_36b_512_HD5304 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5305 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5306 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5307 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5308 | 79(0.02%) | 79(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5309 | 46(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5311 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5312 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5313 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5313 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5316 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5317 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5318 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5319 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5319 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5321 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5323 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[21].U2_PISO_RAW | PISO_RAW_data_59 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U4_FIFO_RAW_Data | FIFO_36b_512_HD5332 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5333 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5334 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5335 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5336 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5337 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5341 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5341 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5344 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5345 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5346 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5347 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5347 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5350 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5351 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[22].U2_PISO_RAW | PISO_RAW_data_60 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U4_FIFO_RAW_Data | FIFO_36b_512_HD5360 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5361 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5362 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5363 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5364 | 80(0.02%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5365 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5367 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5368 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5369 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5372 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5373 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5374 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5375 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5375 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5377 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5378 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5379 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[23].U2_PISO_RAW | PISO_RAW_data_61 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U4_FIFO_RAW_Data | FIFO_36b_512_HD5388 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5389 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5390 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5391 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5392 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5393 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5397 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5397 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5399 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5400 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5401 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5402 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5403 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5403 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5405 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5407 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[24].U2_PISO_RAW | PISO_RAW_data_62 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U4_FIFO_RAW_Data | FIFO_36b_512_HD5416 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5417 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5418 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5419 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5420 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5421 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5425 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5425 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5427 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5428 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5429 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5430 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5431 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5431 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5433 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5434 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5435 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[25].U2_PISO_RAW | PISO_RAW_data_63 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U4_FIFO_RAW_Data | FIFO_36b_512_HD5444 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5445 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5446 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5447 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5448 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5449 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5453 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5453 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5455 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5456 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5457 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5458 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5459 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5459 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5463 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[26].U2_PISO_RAW | PISO_RAW_data_64 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U4_FIFO_RAW_Data | FIFO_36b_512_HD5472 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5473 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5474 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5475 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5476 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5477 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5481 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5481 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5483 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5484 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5485 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5486 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5487 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5487 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5489 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5490 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5491 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[27].U2_PISO_RAW | PISO_RAW_data_65 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U4_FIFO_RAW_Data | FIFO_36b_512_HD5500 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5501 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5502 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5503 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5504 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5505 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5509 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5509 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5511 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5512 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5513 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5514 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5515 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5515 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5517 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5518 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5519 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[28].U2_PISO_RAW | PISO_RAW_data_66 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U4_FIFO_RAW_Data | FIFO_36b_512_HD5528 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5529 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5530 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5531 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5532 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5533 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5537 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5537 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5539 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5540 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5541 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5542 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5543 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5543 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5547 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[29].U2_PISO_RAW | PISO_RAW_data_67 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U4_FIFO_RAW_Data | FIFO_36b_512_HD5556 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5557 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5558 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5559 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5560 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5561 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5565 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5565 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5567 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5568 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5569 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5570 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5571 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5571 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5573 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5574 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5575 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[2].U2_PISO_RAW | PISO_RAW_data_68 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U4_FIFO_RAW_Data | FIFO_36b_512_HD5584 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5585 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5586 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5587 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5588 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5589 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5593 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5593 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5596 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5597 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5598 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5599 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5599 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5601 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5602 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5603 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[30].U2_PISO_RAW | PISO_RAW_data_69 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U4_FIFO_RAW_Data | FIFO_36b_512_HD5612 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5613 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5614 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5615 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5616 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5617 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5621 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5621 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5623 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5624 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5625 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5626 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5627 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5627 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5631 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[31].U2_PISO_RAW | PISO_RAW_data_70 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U4_FIFO_RAW_Data | FIFO_36b_512_HD5640 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5641 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5642 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5643 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5644 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5645 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5649 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5649 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5651 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5652 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5653 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5654 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5655 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5655 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5657 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5659 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[32].U2_PISO_RAW | PISO_RAW_data_71 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U4_FIFO_RAW_Data | FIFO_36b_512_HD5668 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5669 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5670 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5671 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5672 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5673 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5677 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5677 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5680 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5681 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5682 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5683 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5683 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5685 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5686 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5687 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[33].U2_PISO_RAW | PISO_RAW_data_72 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U4_FIFO_RAW_Data | FIFO_36b_512_HD5696 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5697 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5698 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5699 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5700 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5701 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5705 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5708 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5709 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5710 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5711 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5711 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5715 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[34].U2_PISO_RAW | PISO_RAW_data_73 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U4_FIFO_RAW_Data | FIFO_36b_512_HD5724 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5725 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5726 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5727 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5728 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5729 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5733 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5733 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5736 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5737 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5738 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5739 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5739 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5743 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[35].U2_PISO_RAW | PISO_RAW_data_74 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U4_FIFO_RAW_Data | FIFO_36b_512_HD5752 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5753 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5754 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5755 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5756 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5757 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5761 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5761 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5764 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5765 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5766 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5767 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5767 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5769 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5771 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[36].U2_PISO_RAW | PISO_RAW_data_75 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U4_FIFO_RAW_Data | FIFO_36b_512_HD5780 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5781 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5782 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5783 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5784 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5785 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5789 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5789 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5792 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5793 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5794 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5795 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5795 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5797 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5799 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[37].U2_PISO_RAW | PISO_RAW_data_76 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U4_FIFO_RAW_Data | FIFO_36b_512_HD5808 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5809 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5810 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5811 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5812 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5813 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5817 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5817 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5820 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5821 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5822 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5823 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5823 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5827 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[38].U2_PISO_RAW | PISO_RAW_data_77 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U4_FIFO_RAW_Data | FIFO_36b_512_HD5836 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5837 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5838 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5839 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5840 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5841 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5845 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5845 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5847 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5848 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5849 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5850 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5851 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5851 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5853 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5854 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5855 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[39].U2_PISO_RAW | PISO_RAW_data_78 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U4_FIFO_RAW_Data | FIFO_36b_512_HD5864 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5865 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5866 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5867 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5868 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5869 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5873 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5873 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5875 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5876 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5877 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5878 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5879 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5879 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5881 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5882 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5883 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[3].U2_PISO_RAW | PISO_RAW_data_79 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U4_FIFO_RAW_Data | FIFO_36b_512_HD5892 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5893 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5894 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5895 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5896 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5897 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5901 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5904 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5905 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5906 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5907 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5907 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5909 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5911 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[40].U2_PISO_RAW | PISO_RAW_data_80 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U4_FIFO_RAW_Data | FIFO_36b_512_HD5920 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5921 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5922 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5923 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5924 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5925 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5929 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5929 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5931 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5932 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5933 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5934 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5935 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5935 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5937 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5938 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5939 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[41].U2_PISO_RAW | PISO_RAW_data_81 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U4_FIFO_RAW_Data | FIFO_36b_512_HD5948 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5949 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5950 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5951 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5952 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5953 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5957 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5957 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5959 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5960 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5961 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5962 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5963 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5963 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5966 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5967 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[42].U2_PISO_RAW | PISO_RAW_data_82 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U4_FIFO_RAW_Data | FIFO_36b_512_HD5976 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5977 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5978 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5979 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5980 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5981 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5985 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5985 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5987 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5988 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5989 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5990 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5991 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5991 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5993 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5994 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5995 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[43].U2_PISO_RAW | PISO_RAW_data_83 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U4_FIFO_RAW_Data | FIFO_36b_512_HD6004 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6005 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6006 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6007 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6008 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6009 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6013 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6013 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6015 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6016 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6017 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6018 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6019 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6019 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6021 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6022 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6023 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[44].U2_PISO_RAW | PISO_RAW_data_84 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U4_FIFO_RAW_Data | FIFO_36b_512_HD6032 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6033 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6034 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6035 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6036 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6037 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6041 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6041 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6043 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6044 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6045 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6046 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6047 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6047 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6049 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6050 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6051 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[45].U2_PISO_RAW | PISO_RAW_data_85 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U4_FIFO_RAW_Data | FIFO_36b_512_HD6060 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6061 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6062 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6063 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6064 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6065 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6069 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6069 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6071 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6072 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6073 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6074 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6075 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6075 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6077 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6078 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6079 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[46].U2_PISO_RAW | PISO_RAW_data_86 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U4_FIFO_RAW_Data | FIFO_36b_512_HD6088 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6089 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6090 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6091 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6092 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6093 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6097 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6097 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6099 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6100 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6101 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6102 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6103 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6103 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6105 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6106 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6107 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[47].U2_PISO_RAW | PISO_RAW_data_87 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U4_FIFO_RAW_Data | FIFO_36b_512_HD6116 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6117 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6118 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6119 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6120 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6121 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6125 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6125 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6127 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6128 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6129 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6130 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6131 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6131 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6133 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6134 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6135 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[48].U2_PISO_RAW | PISO_RAW_data_88 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U4_FIFO_RAW_Data | FIFO_36b_512_HD6144 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6145 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6146 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6147 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6148 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6149 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6153 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6153 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6155 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6156 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6157 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6158 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6159 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6159 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6162 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6163 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[4].U2_PISO_RAW | PISO_RAW_data_89 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U4_FIFO_RAW_Data | FIFO_36b_512_HD6172 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6173 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6174 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6175 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6176 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6177 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6181 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6181 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6184 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6185 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6186 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6187 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6187 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6189 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6190 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6191 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[5].U2_PISO_RAW | PISO_RAW_data_90 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U4_FIFO_RAW_Data | FIFO_36b_512_HD6200 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6201 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6202 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6203 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6204 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6205 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6209 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6209 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6212 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6213 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6214 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6215 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6215 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6217 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6219 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[6].U2_PISO_RAW | PISO_RAW_data_91 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U4_FIFO_RAW_Data | FIFO_36b_512_HD6228 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6229 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6230 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6231 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6232 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6233 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6237 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6237 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6240 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6241 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6242 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6243 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6243 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6245 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6247 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[7].U2_PISO_RAW | PISO_RAW_data_92 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U4_FIFO_RAW_Data | FIFO_36b_512_HD6256 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6257 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6258 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6259 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6260 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6261 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6265 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6265 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6267 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6268 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6269 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6270 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6271 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6271 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6274 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6275 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[8].U2_PISO_RAW | PISO_RAW_data_93 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U4_FIFO_RAW_Data | FIFO_36b_512_HD6284 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6285 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6286 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6287 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6288 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6289 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6293 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6293 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6295 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6296 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6297 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6298 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6299 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6299 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6301 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6302 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6303 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[9].U2_PISO_RAW | PISO_RAW_data_94 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U4_FIFO_RAW_Data | FIFO_36b_512_HD6312 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6313 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6314 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6315 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6316 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6317 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6321 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6324 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6325 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6326 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6327 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6327 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6329 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6330 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6331 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U10_RAW_frame_counter | cntr_up_dn_generic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U10_clk_closs_pulse | clk_closs_pulse_fsm | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_RAW_SPY_mem | ipbus_dpram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_busy_flag_fsm | busy_flag_fsm | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_FIFO_link_err | FIFO_54b_512 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_54b_512_fifo_generator_v13_2_5 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_54b_512_fifo_generator_v13_2_5_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_54b_512_fifo_generator_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbi.bi | FIFO_54b_512_fifo_generator_v13_2_5_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | FIFO_54b_512_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | FIFO_54b_512_builtin_top_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | FIFO_54b_512_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | FIFO_54b_512_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U5_RAW_fsm | fsm_RAW_data_wr_to_DPR | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U5_RAW_fsm) | fsm_RAW_data_wr_to_DPR | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_10b | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_link_err | link_errors_ORed | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5b_gen_full_flag | RAW_fifo_full_flag_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_FIFO_BCN_L1A | FIFO_47b_512 | 98(0.03%) | 98(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_5 | 98(0.03%) | 98(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_5_synth | 98(0.03%) | 98(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top | 98(0.03%) | 98(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo | 98(0.03%) | 98(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_47b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_rd_RAW_mux_fsm | fsm_RAW_to_muxPISO | 801(0.23%) | 801(0.23%) | 0(0.00%) | 0(0.00%) | 2086(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U7_rd_RAW_mux_fsm) | fsm_RAW_to_muxPISO | 774(0.22%) | 774(0.22%) | 0(0.00%) | 0(0.00%) | 2074(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_raw_payld_length | cntr_generic__parameterized2 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_RAW_Link_output_FIFO | FIFO_33b_8192 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_5 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_5_synth | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_33b_8192_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_4 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_4_synth | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_RAW_Link_output_FIFO_FSM | FIFO_to_MGT_RAW_FSM | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_rdout_ipb_slave | readout_ipb_slave | 519(0.15%) | 519(0.15%) | 0(0.00%) | 0(0.00%) | 961(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U4_rdout_ipb_slave) | readout_ipb_slave | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_Test_Cntl_Reg | ipbus_ctrlreg_v__parameterized2_17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_pulsed_register | ipbus_ctrlreg_v__parameterized2_18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_top_level_counters | ipbus_ctrlreg_v__parameterized4 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_ttc_parity_L1A_BCN | ipbus_ctrlreg_v__parameterized5 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_slave | slave_TOB_readout | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 544(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U11_LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_30 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_31 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U18_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_33 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOB_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_34 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_EG_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_35 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_TAU_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_SLICES_TO_RD | ipbus_ctrlreg_v__parameterized2_37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_trigger_slice | ipbus_ctrlreg_v__parameterized2_38 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_TOB_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_TOB_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_40 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_41 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_42 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_EG_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_TAU_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_44 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_EG_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_TAU_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_46 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_RAW_slave | slave_RAW_readout | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U15_RAW_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_19 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_RAW_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_23 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_Link_output_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_27 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9A_RAW_FIFO_FULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_28 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9B_RAW_FIFO_FULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_29 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | proc_FPGAs | 6026(1.74%) | 6007(1.73%) | 0(0.00%) | 19(0.01%) | 2662(0.38%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_node_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | ipbus_ctrl | 6013(1.74%) | 5994(1.73%) | 0(0.00%) | 19(0.01%) | 2609(0.38%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (U_2) | ipbus_ctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 4501(1.30%) | 4501(1.30%) | 0(0.00%) | 0(0.00%) | 370(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 191(0.06%) | 191(0.06%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 4322(1.25%) | 4322(1.25%) | 0(0.00%) | 0(0.00%) | 235(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 1510(0.44%) | 1491(0.43%) | 0(0.00%) | 19(0.01%) | 2239(0.32%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 194(0.06%) | 193(0.06%) | 0(0.00%) | 1(0.01%) | 224(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 180(0.05%) | 180(0.05%) | 0(0.00%) | 0(0.00%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 107(0.03%) | 91(0.03%) | 0(0.00%) | 16(0.01%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 143(0.04%) | 143(0.04%) | 0(0.00%) | 0(0.00%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 235(0.07%) | 235(0.07%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_5 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_resources | clk_resources | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_resources) | clk_resources | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Inputclk40M | ClockWizard | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | ClockWizard_ClockWizard_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk40_gen | clk_wiz_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_1_clk_wiz_1_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 20(0.01%) | 19(0.01%) | 0(0.00%) | 1(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 4(0.01%) | 3(0.01%) | 0(0.00%) | 1(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | slaves | 559(0.16%) | 559(0.16%) | 0(0.00%) | 0(0.00%) | 1289(0.19%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | bcmuxvalue_sync | ipbus_ctrlreg_v__parameterized2 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 425(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig | ipbus_ctrlreg_v__parameterized2_0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32 | 273(0.08%) | 273(0.08%) | 0(0.00%) | 0(0.00%) | 304(0.04%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bc_delay | ipbus_ctrlreg_v__parameterized1_1 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bus_delay | ipbus_ctrlreg_v__parameterized1_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_synch | ipbus_ctrlreg_v__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_orbit_length | ipbus_ctrlreg_v__parameterized2_4 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 367(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 366(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining