*** Running vivado with args -log io_delay2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source io_delay2.tcl WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source io_delay2.tcl -notrace Command: synth_design -top io_delay2 -part xc7vx550tffg1927-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 2332717 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2675.500 ; gain = 69.719 ; free physical = 19892 ; free virtual = 57067 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'io_delay2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.v:58] Parameter SYS_W bound to: 1 - type: integer Parameter DEV_W bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'io_delay2_selectio_wiz' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_selectio_wiz.v:56] Parameter SYS_W bound to: 1 - type: integer Parameter DEV_W bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:32998] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: FALSE - type: string Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: LVDS - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:32998] INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35073] Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: VAR_LOAD - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: double Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (2#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35073] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13724] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'FDRE' (3#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:13724] INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (4#1) [/opt/Xilinx/Vivado/2020.2/scripts/rt/data/unisim_comp.v:35060] INFO: [Synth 8-6155] done synthesizing module 'io_delay2_selectio_wiz' (5#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_selectio_wiz.v:56] INFO: [Synth 8-6155] done synthesizing module 'io_delay2' (6#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2718.406 ; gain = 112.625 ; free physical = 20608 ; free virtual = 57784 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2736.219 ; gain = 130.438 ; free physical = 20653 ; free virtual = 57829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2736.219 ; gain = 130.438 ; free physical = 20653 ; free virtual = 57829 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.156 ; gain = 0.000 ; free physical = 20642 ; free virtual = 57817 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_ooc.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/io_delay2_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/io_delay2_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'inst' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'inst' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/io_delay2_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/io_delay2_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2829.000 ; gain = 0.000 ; free physical = 20532 ; free virtual = 57707 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2831.969 ; gain = 2.969 ; free physical = 20520 ; free virtual = 57695 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20557 ; free virtual = 57733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20557 ; free virtual = 57732 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/io_delay2_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20556 ; free virtual = 57732 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20557 ; free virtual = 57733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20554 ; free virtual = 57732 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20336 ; free virtual = 57515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20336 ; free virtual = 57515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20329 ; free virtual = 57508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20531 ; free virtual = 57710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20529 ; free virtual = 57708 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20523 ; free virtual = 57703 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20522 ; free virtual = 57702 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20522 ; free virtual = 57702 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20522 ; free virtual = 57702 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 1| |3 |FDRE | 1| |4 |IBUFDS | 1| +------+-----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20523 ; free virtual = 57702 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 2831.969 ; gain = 130.438 ; free physical = 20592 ; free virtual = 57771 Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.969 ; gain = 226.188 ; free physical = 20591 ; free virtual = 57771 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.969 ; gain = 0.000 ; free physical = 20586 ; free virtual = 57766 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.719 ; gain = 0.000 ; free physical = 20579 ; free virtual = 57758 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 2842.719 ; gain = 244.941 ; free physical = 20632 ; free virtual = 57811 INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/io_delay2_synth_1/io_delay2.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP io_delay2, cache-ID = 9a5eecd1d0bb3ced INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/io_delay2_synth_1/io_delay2.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file io_delay2_utilization_synth.rpt -pb io_delay2_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sun Mar 9 00:47:02 2025...