*** Running vivado with args -log top_efex_processor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_efex_processor.tcl WARNING: Default location for XILINX_HLS not found ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace source /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:Msg-0] Project efex_processor.2 has flavour = 2, the generic variable FLAVOUR will be set to 2 INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.2-v1.7.0-E030ECB... INFO: [Hog:Msg-0] Opening project efex_processor.2... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'. INFO: [Hog:Msg-0] Checking efex_processor.2 list files... INFO: [Hog:Msg-0] Retrieved Vivado project files... INFO: [Hog:Msg-0] Design List Files matches project. Nothing to do. INFO: [Hog:Msg-0] Simulation List Files matches project. Nothing to do. INFO: [Hog:Msg-0] Constraint List Files matches project. Nothing to do. INFO: [Hog:Msg-0] /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Top//efex_processor.2/hog.conf matches project. Nothing to do WARNING: [Hog:Msg-0] /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Top//efex_processor.2/sim.conf not found. Skipping properties check INFO: [Hog:Msg-0] Design List files and hog.conf match project. All ok! INFO: [Hog:Msg-0] Simulation list files match project. All ok! INFO: [Hog:Msg-0] Simulation config files match project. All ok! INFO: [Hog:Msg-0] All done. INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Git describe for e030ecb is: v1.7.0-E030ECB INFO: [Hog:Msg-0] Found last SHA for efex_processor.2: e030ecb INFO: [Hog:Msg-0] Creating XML directory /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml and replacing placeholders with xml version 01070000... WARNING: [Hog:CopyXMLsFromListFile-0] Error while trying to run python: couldn't execute "python": no such file or directory WARNING: [Hog:CopyXMLsFromListFile-0] IPbus executable gen_ipbus_addr_decode not found or not working, will not verify IPbus address tables. INFO: [Hog:CopyXMLsFromListFile-0] 17 lines read from ./Top//efex_processor.2/list/xml.lst INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/L1CaloEfexProcessor.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_common_id_version.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_infrastructure.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_mgt_channel.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_mgt_quad.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_mgt_top.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_lib_version.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/xml/efex_algorithm.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/xml/efex_sorting.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/xml/efex_merging.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/xml/efex_readout.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/xml/efex_raw_readout.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] Copying /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/xml/efex_tob_readout.xml to /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/xml... INFO: [Hog:CopyXMLsFromListFile-0] 13 file/s copied INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:WriteGenerics-0] Passing parameters/generics to project's top module... INFO: [Hog:WriteGenerics-0] Setting parameters/generics... INFO: [Hog:Msg-0] Opening version file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/versions.txt... ------------------------- PRE SYNTHESIS ------------------------- 09/03/2025 at 00:47:35 Firmware date and time: 08032025, 00141112 Project flavour: 2 Global SHA: e030ecb, VER: 1.7.0 Constraints SHA: e030ecb9, VER: 1.7.0 IPbus XML SHA: 6995bf6, VER: 1.7.0 Top SHA: 544c0a0, VER: 0.8.0 Hog SHA: 219f277, VER: 8.15.4 --- Libraries --- TOB_rdout_lib SHA: c2e48ed, VER: 1.7.0 algolib SHA: a666257, VER: 1.7.0 infrastructure_lib SHA: 5c0a46a, VER: 1.7.0 ips SHA: 4038eab, VER: 1.7.0 ipbus_lib SHA: d6f4f62, VER: 1.0.0 usr_ip SHA: e4b7ad6, VER: 1.7.0 ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with Hog2024.2-4 in .gitlab-ci.yml. INFO: [Hog:Msg-0] Sourcing user pre-synthesis file ./Top//efex_processor.2/pre-synthesis.tcl INFO: [Hog:Msg-0] All done. Command: synth_design -top top_efex_processor -part xc7vx550tffg1927-2 -retiming Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 2333860 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2773.859 ; gain = 0.000 ; free physical = 19143 ; free virtual = 56318 --------------------------------------------------------------------------------- WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:65] WARNING: [Synth 8-4747] shared variables must be of a protected type [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:50] INFO: [Synth 8-638] synthesizing module 'top_efex_processor' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:202] Parameter FLAVOUR bound to: 2 - type: integer Parameter GLOBAL_DATE bound to: 32'b00001000000000110010000000100101 Parameter GLOBAL_TIME bound to: 32'b00000000000101000001000100010010 Parameter GLOBAL_SHA bound to: 32'b00001110000000110000111011001011 Parameter GLOBAL_VER bound to: 32'b00000001000001110000000000000000 Parameter TOP_SHA bound to: 32'b00000101010001001100000010100000 Parameter TOP_VER bound to: 32'b00000000000010000000000000000000 Parameter CON_SHA bound to: 32'b11100000001100001110110010111001 Parameter CON_VER bound to: 32'b00000001000001110000000000000000 Parameter XML_SHA bound to: 32'b00000110100110010101101111110110 Parameter XML_VER bound to: 32'b00000001000001110000000000000000 Parameter HOG_SHA bound to: 32'b00000010000110011111001001110111 Parameter HOG_VER bound to: 32'b00001000000011110000000000000100 Parameter ALGOLIB_SHA bound to: 32'b00001010011001100110001001010111 Parameter ALGOLIB_VER bound to: 32'b00000001000001110000000000000000 Parameter INFRASTRUCTURE_LIB_SHA bound to: 32'b00000101110000001010010001101010 Parameter INFRASTRUCTURE_LIB_VER bound to: 32'b00000001000001110000000000000000 Parameter TOB_RDOUT_LIB_SHA bound to: 32'b00001100001011100100100011101101 Parameter TOB_RDOUT_LIB_VER bound to: 32'b00000001000001110000000000000000 Parameter IPBUS_LIB_SHA bound to: 32'b00001101011011110100111101100010 Parameter IPBUS_LIB_VER bound to: 32'b00000001000000000000000000000000 Parameter READOUT_ENABLED bound to: 1 - type: bool Parameter INPUT_RAM_ENABLED bound to: 0 - type: bool Parameter OUTPUT_RAMS_ENABLED bound to: 0 - type: bool Parameter SORT_IN_RAM_ENABLED bound to: 0 - type: bool Parameter SORT_OUT_RAM_ENABLED bound to: 0 - type: bool Parameter MGT_ENABLED bound to: 1 - type: bool Parameter MERGE_ENABLED bound to: 1 - type: bool Parameter DATA_PATH_ENABLED bound to: 1 - type: bool Parameter TAU_ALGO_VERSION bound to: 2'b10 Parameter EG_ALGO_VERSION bound to: 2'b01 Parameter ENCODING_MODE bound to: 2 - type: integer Parameter EFEX_POSITION bound to: 0 - type: integer Parameter n_channels bound to: 64 - type: integer WARNING: [Synth 8-3819] Generic 'IPS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPS_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'USR_IP_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'USR_IP_SHA' not present in instantiated entity will be ignored INFO: [Synth 8-113] binding component instance 'reset_bufg' to cell 'BUFG' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:608] INFO: [Synth 8-638] synthesizing module 'proc_FPGAs' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/Process_FPGA_IPbus.vhd:74] Parameter IPBUSPORT bound to: 16'b1100001101010011 INFO: [Synth 8-638] synthesizing module 'UDP_node_if' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_node_if.vhd:35] INFO: [Synth 8-256] done synthesizing module 'UDP_node_if' (1#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_node_if.vhd:35] INFO: [Synth 8-638] synthesizing module 'interconnect' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'parity_checker' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-256] done synthesizing module 'parity_checker' (2#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-638] synthesizing module 'parity_gen' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] Parameter width bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'parity_gen' (3#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] INFO: [Synth 8-256] done synthesizing module 'interconnect' (4#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b1 Parameter DHCP_RARP bound to: 1'b0 Parameter N_OOB bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'oob_in' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:89] WARNING: [Synth 8-506] null port 'oob_out' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b1 Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_ipam' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_ipam' (5#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (6#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (7#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (8#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (9#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (10#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (11#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] Parameter SECONDARYPORT bound to: 1'b1 Parameter DHCP_RARP bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (12#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (13#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (14#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (15#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (16#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (17#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (17#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (18#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:83] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (19#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (19#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] Parameter INTERNAL_ONLY bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (20#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (21#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (22#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (23#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] INFO: [Synth 8-638] synthesizing module 'transactor' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (24#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (25#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (26#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor' (27#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (28#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] INFO: [Synth 8-256] done synthesizing module 'proc_FPGAs' (29#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/Process_FPGA_IPbus.vhd:74] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 8 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (30#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'common_id_registers' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (30#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (31#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:107] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:109] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (31#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:121] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:123] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:135] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:149] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:151] INFO: [Synth 8-256] done synthesizing module 'common_id_registers' (32#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'lib_registers' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:41] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 7 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (32#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:72] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:73] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:85] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:86] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:98] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:99] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:111] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:112] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:124] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:125] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:138] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:150] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:151] INFO: [Synth 8-256] done synthesizing module 'lib_registers' (33#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/lib_registers.vhd:41] INFO: [Synth 8-638] synthesizing module 'slaves' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:69] Parameter FPGA_FLAVOUR bound to: 2 - type: integer Parameter reg48 bound to: 16'b0100011100000001 Parameter reg49 bound to: 16'b0000000000000000 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 10 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (33#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (33#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 0 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'd' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized2' (33#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:133] INFO: [Synth 8-638] synthesizing module 'ipbus_xadc_drp' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] Parameter NUMREG bound to: 19 - type: integer Parameter reg48 bound to: 16'b0100011100000001 Parameter reg49 bound to: 16'b0000000000000000 INFO: [Synth 8-638] synthesizing module 'xadc_eFEX' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] Parameter reg48 bound to: 16'b0100011100000001 Parameter reg49 bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'U_BUFG' to cell 'BUFG' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:141] Parameter INIT_40 bound to: 16'b1001000000000000 Parameter INIT_41 bound to: 16'b0010111011110000 Parameter INIT_42 bound to: 16'b0000010000000000 Parameter INIT_43 bound to: 16'b0010111011110000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000001 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0100011100000001 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101100110011001 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1101110111011101 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101000100010001 Parameter INIT_56 bound to: 16'b1001000111101011 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:147] INFO: [Synth 8-256] done synthesizing module 'xadc_eFEX' (34#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] INFO: [Synth 8-256] done synthesizing module 'ipbus_xadc_drp' (35#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:166] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:181] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:197] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] Parameter BYTE_SPI bound to: 1 - type: bool Parameter ADDR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 4 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter DECODE_BASE bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch' (36#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 4 - type: integer Parameter N_STAT bound to: 1 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized3' (36#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] Parameter TIMER_WIDTH bound to: 20 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog' (37#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash' (38#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized0' (38#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'command_sync' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-256] done synthesizing module 'command_sync' (39#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-638] synthesizing module 'spi32_8_control' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter BYTE_SPI bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'spi32_8_control' (40#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] INFO: [Synth 8-638] synthesizing module 'clock_pulse' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'clock_pulse' (41#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32' (42#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_ram' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ram' (43#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] INFO: [Synth 8-256] done synthesizing module 'slaves' (44#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd:69] INFO: [Synth 8-638] synthesizing module 'startup' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-113] binding component instance 'STARTUPE2_inst' to cell 'STARTUPE2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:34] INFO: [Synth 8-256] done synthesizing module 'startup' (45#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] INFO: [Synth 8-638] synthesizing module 'self_configure' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/self_configure.vhd:36] INFO: [Synth 8-638] synthesizing module 'reconfig' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:38] Parameter MAX_COUNT bound to: 65535 - type: integer Parameter DEVICE_ID bound to: 32'b00000011011001010001000010010011 Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-113] binding component instance 'ICAPE2_inst' to cell 'ICAPE2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:70] INFO: [Synth 8-256] done synthesizing module 'reconfig' (46#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:38] INFO: [Synth 8-256] done synthesizing module 'self_configure' (47#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/self_configure.vhd:36] INFO: [Synth 8-638] synthesizing module 'clk_resources' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:67] INFO: [Synth 8-3491] module 'ClockWizard' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/ClockWizard_stub.vhdl:5' bound to instance 'Inputclk40M' of component 'ClockWizard' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:117] INFO: [Synth 8-638] synthesizing module 'ClockWizard' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/ClockWizard_stub.vhdl:19] INFO: [Synth 8-3491] module 'clk_wiz_1' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/clk_wiz_1_stub.vhdl:5' bound to instance 'clk40_gen' of component 'clk_wiz_1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:133] INFO: [Synth 8-638] synthesizing module 'clk_wiz_1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/clk_wiz_1_stub.vhdl:15] INFO: [Synth 8-3491] module 'clocks_7s_extphy' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:23' bound to instance 'clocks' of component 'clocks_7s_extphy' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:148] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFGDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:51] INFO: [Synth 8-113] binding component instance 'bufg200' to cell 'BUFG' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:57] INFO: [Synth 8-113] binding component instance 'bufg125' to cell 'BUFG' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:62] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:69] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 1.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_DIVIDE bound to: 5 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_CASCADE bound to: 0 - type: bool Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter STARTUP_WAIT bound to: 0 - type: bool INFO: [Synth 8-113] binding component instance 'mmcm' to cell 'MMCME2_BASE' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:76] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:58] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (48#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (49#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] INFO: [Synth 8-256] done synthesizing module 'clk_resources' (50#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd:67] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:903] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:903] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:903] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: 0 - type: bool Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'f5_to_f1' to cell 'IBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:903] INFO: [Synth 8-638] synthesizing module 'Readout_logic_top' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/Readout_logic_top.vhd:213] Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'cntr_generic' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 32 - type: integer Parameter WRAPAROUND bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic' (51#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-638] synthesizing module 'tide_mark_block' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/tide_mark_block.vhd:30] Parameter width bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'tide_mark_block' (52#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/tide_mark_block.vhd:30] INFO: [Synth 8-638] synthesizing module 'TOBs_rdout' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOBs_rdout.vhd:283] Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'gen_sync_280M' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/gen_sync_280M.vhd:34] INFO: [Synth 8-256] done synthesizing module 'gen_sync_280M' (53#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/gen_sync_280M.vhd:34] Parameter INIT bound to: 1'b0 Parameter IS_CLR_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'U0_FDCE_xoff' to cell 'FDCE' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOBs_rdout.vhd:480] INFO: [Synth 8-638] synthesizing module 'busy_flag_fsm' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/busy_flag_fsm.vhd:29] Parameter width bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'busy_flag_fsm' (54#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/busy_flag_fsm.vhd:29] INFO: [Synth 8-3491] module 'FIFO_47b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_47b_512_stub.vhdl:5' bound to instance 'U0_FIFO_BCN_L1A' of component 'FIFO_47b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOBs_rdout.vhd:532] INFO: [Synth 8-638] synthesizing module 'FIFO_47b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_47b_512_stub.vhdl:25] INFO: [Synth 8-638] synthesizing module 'T_TOBs_sorting' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/T_TOBs_sorting.vhd:85] Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'SIPO_TOPO_TOBs_unit' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_TOPO_TOBs_unit.vhd:45] INFO: [Synth 8-638] synthesizing module 'GeneralDelay' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 5 - type: integer Parameter size bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay' (55#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-256] done synthesizing module 'SIPO_TOPO_TOBs_unit' (56#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_TOPO_TOBs_unit.vhd:45] INFO: [Synth 8-638] synthesizing module 'fsm_TOB_wr_to_FIFO' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_TOB_wr_to_FIFO.vhd:52] INFO: [Synth 8-638] synthesizing module 'cntr_ram_addr_9b' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_ram_addr_9b.vhd:31] INFO: [Synth 8-256] done synthesizing module 'cntr_ram_addr_9b' (57#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_ram_addr_9b.vhd:31] INFO: [Synth 8-256] done synthesizing module 'fsm_TOB_wr_to_FIFO' (58#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_TOB_wr_to_FIFO.vhd:52] INFO: [Synth 8-3491] module 'DPR_209b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_209b_512_stub.vhdl:5' bound to instance 'U4_T_TOB_DRP' of component 'DPR_209b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/T_TOBs_sorting.vhd:182] INFO: [Synth 8-638] synthesizing module 'DPR_209b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_209b_512_stub.vhdl:20] INFO: [Synth 8-3491] module 'FIFO_209b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_209b_512_stub.vhdl:5' bound to instance 'U5_T_TOBs_fifo' of component 'FIFO_209b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/T_TOBs_sorting.vhd:217] INFO: [Synth 8-638] synthesizing module 'FIFO_209b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_209b_512_stub.vhdl:24] INFO: [Synth 8-256] done synthesizing module 'T_TOBs_sorting' (59#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/T_TOBs_sorting.vhd:85] INFO: [Synth 8-638] synthesizing module 'XTOBs_sorting' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:92] Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 2 - type: integer Parameter size bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized0' (59#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-638] synthesizing module 'SIPO_unit' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:36] INFO: [Synth 8-256] done synthesizing module 'SIPO_unit' (60#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:36] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] INFO: [Synth 8-638] synthesizing module 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:20] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-638] synthesizing module 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:28] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-3491] module 'DPR_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_252b_512_stub.vhdl:5' bound to instance 'U3_XTOB_DRP' of component 'DPR_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:214] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOB_rdout_ip_pkg.vhd:155] INFO: [Synth 8-3491] module 'FIFO_252b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_252b_512_stub.vhdl:5' bound to instance 'U5_XTOBs_FIFO' of component 'FIFO_252b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:227] INFO: [Synth 8-256] done synthesizing module 'XTOBs_sorting' (61#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/XTOBs_sorting.vhd:92] INFO: [Synth 8-638] synthesizing module 'fsm_TOBs_to_muxPISO' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_TOBs_to_muxPISO.vhd:191] Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 4 - type: integer Parameter WRAPAROUND bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized0' (61#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 7 - type: integer Parameter WRAPAROUND bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized1' (61#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 12 - type: integer Parameter WRAPAROUND bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized2' (61#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'fsm_TOBs_to_muxPISO' (62#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_TOBs_to_muxPISO.vhd:191] INFO: [Synth 8-3491] module 'FIFO_33b_8192' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_33b_8192_stub.vhdl:5' bound to instance 'U7_Link_output_FIFO' of component 'FIFO_33b_8192' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOBs_rdout.vhd:732] INFO: [Synth 8-638] synthesizing module 'FIFO_33b_8192' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_33b_8192_stub.vhdl:27] INFO: [Synth 8-638] synthesizing module 'FIFO_to_MGT_TOB_FSM' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/FIFO_to_MGT_TOB_FSM.vhd:66] INFO: [Synth 8-256] done synthesizing module 'FIFO_to_MGT_TOB_FSM' (63#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/FIFO_to_MGT_TOB_FSM.vhd:66] INFO: [Synth 8-638] synthesizing module 'clk_closs_pulse_fsm' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/clk_closs_pulse_fsm.vhd:24] INFO: [Synth 8-256] done synthesizing module 'clk_closs_pulse_fsm' (64#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/clk_closs_pulse_fsm.vhd:24] INFO: [Synth 8-638] synthesizing module 'cntr_up_dn_generic' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_up_dn_generic.vhd:39] Parameter width bound to: 12 - type: integer INFO: [Synth 8-256] done synthesizing module 'cntr_up_dn_generic' (65#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_up_dn_generic.vhd:39] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram' (66#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62] INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 11 - type: integer Parameter WRAPAROUND bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized3' (66#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'TOBs_rdout' (67#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/TOBs_rdout.vhd:283] INFO: [Synth 8-638] synthesizing module 'RAW_data_rdout' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:214] Parameter FPGA_NUMBER bound to: 2 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_CLR_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'U0_FDCE_inst' to cell 'FDCE' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:446] INFO: [Synth 8-638] synthesizing module 'PISO_RAW_data' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/PISO_RAW_data.vhd:42] INFO: [Synth 8-256] done synthesizing module 'PISO_RAW_data' (68#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/PISO_RAW_data.vhd:42] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-638] synthesizing module 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:20] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-638] synthesizing module 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:24] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Synth 8-3491] module 'FIFO_36b_512' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_36b_512_stub.vhdl:5' bound to instance 'U4_FIFO_RAW_Data' of component 'FIFO_36b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:530] INFO: [Synth 8-3491] module 'DPR_36b_1024' declared at '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/DPR_36b_1024_stub.vhdl:5' bound to instance 'U3_DPRAM_RAW_Data' of component 'DPR_36b_1024' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:516] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'link_errors_ORed' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/link_errors_ORed.vhd:44] Parameter N bound to: 49 - type: integer INFO: [Synth 8-256] done synthesizing module 'link_errors_ORed' (69#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/link_errors_ORed.vhd:44] Parameter INIT bound to: 1'b0 Parameter IS_CLR_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'U5_FDCE_inst' to cell 'FDCE' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:584] INFO: [Synth 8-638] synthesizing module 'FIFO_54b_512' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FIFO_54b_512_stub.vhdl:21] INFO: [Synth 8-638] synthesizing module 'fsm_RAW_data_wr_to_DPR' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_RAW_data_wr_to_DPR.vhd:52] INFO: [Synth 8-638] synthesizing module 'cntr_ram_addr_10b' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_ram_addr_10b.vhd:26] INFO: [Synth 8-256] done synthesizing module 'cntr_ram_addr_10b' (70#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_ram_addr_10b.vhd:26] INFO: [Synth 8-256] done synthesizing module 'fsm_RAW_data_wr_to_DPR' (71#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_RAW_data_wr_to_DPR.vhd:52] INFO: [Synth 8-638] synthesizing module 'RAW_fifo_full_flag_gen' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_fifo_full_flag_gen.vhd:41] INFO: [Synth 8-256] done synthesizing module 'RAW_fifo_full_flag_gen' (72#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_fifo_full_flag_gen.vhd:41] INFO: [Synth 8-638] synthesizing module 'fsm_RAW_to_muxPISO' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_RAW_to_muxPISO.vhd:134] INFO: [Synth 8-256] done synthesizing module 'fsm_RAW_to_muxPISO' (73#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_RAW_to_muxPISO.vhd:134] INFO: [Synth 8-638] synthesizing module 'FIFO_to_MGT_RAW_FSM' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/FIFO_to_MGT_RAW_FSM.vhd:61] INFO: [Synth 8-256] done synthesizing module 'FIFO_to_MGT_RAW_FSM' (74#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/FIFO_to_MGT_RAW_FSM.vhd:61] INFO: [Synth 8-256] done synthesizing module 'RAW_data_rdout' (75#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/RAW_data_rdout.vhd:214] INFO: [Synth 8-638] synthesizing module 'readout_ipb_slave' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:211] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 6 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized3' (75#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:267] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:285] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized4' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 8 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized4' (75#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:310] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:311] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized5' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 9 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized5' (75#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:333] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:334] INFO: [Synth 8-638] synthesizing module 'slave_TOB_readout' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:128] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized4' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 29 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized4' (75#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:236] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:237] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:248] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:249] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:260] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:261] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:272] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:284] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:296] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:308] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:322] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:335] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:348] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:360] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:361] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:373] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:389] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:404] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:405] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:417] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:430] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:442] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:443] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:455] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:468] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:480] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:481] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:493] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:506] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:518] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:519] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:530] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:531] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:542] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:543] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:552] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:564] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized6' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 5 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized6' (75#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:585] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:586] INFO: [Synth 8-256] done synthesizing module 'slave_TOB_readout' (76#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_TOB_readout.vhd:128] INFO: [Synth 8-638] synthesizing module 'slave_RAW_readout' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:105] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized5' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 20 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized5' (76#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:193] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:205] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:220] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:236] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:249] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:261] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:275] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:276] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:285] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:297] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:314] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:315] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:325] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:337] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:349] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:350] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:360] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:361] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:371] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:372] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:382] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:383] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:393] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:405] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:406] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:416] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:417] INFO: [Synth 8-256] done synthesizing module 'slave_RAW_readout' (77#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/slave_RAW_readout.vhd:105] INFO: [Synth 8-256] done synthesizing module 'readout_ipb_slave' (78#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/readout_ipb_slave.vhd:211] INFO: [Synth 8-638] synthesizing module 'bcn_l1a_valid_checker' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/bcn_l1a_valid_checker.vhd:46] Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'ttc_parity' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd:23] Parameter SEED bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'ttc_parity' (79#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd:23] INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized4' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 32 - type: integer Parameter WRAPAROUND bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized4' (79#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'bcn_l1a_valid_checker' (80#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/bcn_l1a_valid_checker.vhd:46] INFO: [Synth 8-256] done synthesizing module 'Readout_logic_top' (81#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/Readout_logic_top.vhd:213] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_X' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:992] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-113] binding component instance 'this_to_Y' to cell 'OBUFDS' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:999] INFO: [Synth 8-638] synthesizing module 'data_path_block' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/data_path_block.vhd:151] Parameter n_channels bound to: 64 - type: integer Parameter ENCODING_MODE bound to: 2 - type: integer Parameter ENABLE_INPUT_RAM bound to: 0 - type: bool Parameter EFEX_POSITION bound to: 0 - type: integer Parameter ENABLE_OUTPUT_RAMS bound to: 0 - type: bool Parameter ENABLE_SORTING_INPUT_RAM bound to: 0 - type: bool Parameter ENABLE_SORTING_OUTPUT_RAM bound to: 0 - type: bool Parameter FPGA_NUMBER bound to: 2 - type: integer Parameter EG_ALGO_VERSION bound to: 2'b01 Parameter TAU_ALGO_VERSION bound to: 2'b10 INFO: [Synth 8-638] synthesizing module 'data_alignment' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/data_alignment.vhd:73] Parameter n_channels bound to: 64 - type: integer Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'quad_bc_alignment' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/quad_bc_alignment.vhd:52] INFO: [Synth 8-638] synthesizing module 'pseudo_orbit_gen' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/pseudo_orbit_gen.vhd:24] INFO: [Synth 8-256] done synthesizing module 'pseudo_orbit_gen' (82#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/pseudo_orbit_gen.vhd:24] INFO: [Synth 8-638] synthesizing module 'orbit_sm' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/orbit_sm.vhd:34] INFO: [Synth 8-256] done synthesizing module 'orbit_sm' (83#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/orbit_sm.vhd:34] INFO: [Synth 8-256] done synthesizing module 'quad_bc_alignment' (84#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/quad_bc_alignment.vhd:52] INFO: [Synth 8-638] synthesizing module 'top_synch' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/top_synch.vhd:79] INFO: [Synth 8-638] synthesizing module 'SRLC32E_226' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:30] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SRL132E_inst_227' to cell 'SRLC32E' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:39] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'SRLC32E_226' (85#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl32e_226.vhd:30] INFO: [Synth 8-638] synthesizing module 'd_type' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/d_type.vhd:24] INFO: [Synth 8-256] done synthesizing module 'd_type' (86#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/d_type.vhd:24] INFO: [Synth 8-638] synthesizing module 'tac_sm' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:37] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:70] INFO: [Synth 8-256] done synthesizing module 'tac_sm' (87#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:37] INFO: [Synth 8-638] synthesizing module 'synch_stage_1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/synch_stg_1.vhd:55] INFO: [Synth 8-638] synthesizing module 'SRL16E_35' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl16e_35.vhd:31] Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter INIT bound to: 16'b0000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'SRL16E_35' (88#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/srl16e_35.vhd:31] INFO: [Synth 8-256] done synthesizing module 'synch_stage_1' (89#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/synch_stg_1.vhd:55] INFO: [Synth 8-638] synthesizing module 'latch_enable' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/latch_enable.vhd:27] INFO: [Synth 8-256] done synthesizing module 'latch_enable' (90#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/latch_enable.vhd:27] INFO: [Synth 8-256] done synthesizing module 'top_synch' (91#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/top_synch.vhd:79] INFO: [Synth 8-638] synthesizing module 'crc_checker' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/crc_checker.vhd:29] INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd:18] Parameter REVERSE_BIT_ORDER bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (92#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd:18] INFO: [Synth 8-256] done synthesizing module 'crc_checker' (93#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/crc_checker.vhd:29] INFO: [Synth 8-638] synthesizing module 'fibremap_block' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/fibremap_block.vhd:38] Parameter FPGA_NUMBER bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'RegSyncLogic' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/Regsync_logic.vhd:24] INFO: [Synth 8-256] done synthesizing module 'RegSyncLogic' (94#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/Regsync_logic.vhd:24] INFO: [Synth 8-256] done synthesizing module 'fibremap_block' (95#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/fibremap_block.vhd:38] INFO: [Synth 8-256] done synthesizing module 'data_alignment' (96#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/data_alignment.vhd:73] INFO: [Synth 8-638] synthesizing module 'IPBusTopAlgoModule' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopAlgoModule.vhd:113] Parameter ENCODING_MODE bound to: 2 - type: integer Parameter USE_INPUT_RAM bound to: 0 - type: bool Parameter EFEX_POSITION bound to: 0 - type: integer Parameter USE_OUTPUT_RAMS bound to: 0 - type: bool Parameter FPGA bound to: 2 - type: integer Parameter EG_ALGO_VERSION bound to: 2'b01 Parameter TAU_ALGO_VERSION bound to: 2'b10 INFO: [Synth 8-638] synthesizing module 'LoadGenerator' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/LoadGenerator.vhd:30] Parameter PHASE200 bound to: 6 - type: integer Parameter PHASE280 bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'LoadGenerator' (97#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/LoadGenerator.vhd:30] INFO: [Synth 8-638] synthesizing module 'AlgoInputStage' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoInputStage.vhd:40] Parameter ENCODING_MODE bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'EnergyConverter' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/EnergyConverter.vhd:36] Parameter ENCODING_MODE bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'EnergyConverter' (98#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/EnergyConverter.vhd:36] INFO: [Synth 8-256] done synthesizing module 'AlgoInputStage' (99#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoInputStage.vhd:40] INFO: [Synth 8-638] synthesizing module 'TopAlgoModule' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TopAlgoModule.vhd:91] Parameter EG_ALGO_VERSION bound to: 2'b01 Parameter TAU_ALGO_VERSION bound to: 2'b10 INFO: [Synth 8-638] synthesizing module 'AlgoShiftRegister' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoShiftRegister.vhd:85] INFO: [Synth 8-256] done synthesizing module 'AlgoShiftRegister' (100#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoShiftRegister.vhd:85] INFO: [Synth 8-638] synthesizing module 'AlgoCore_eg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoCore_eg.vhd:75] Parameter EG_ALGO_VERSION bound to: 2'b01 INFO: [Synth 8-638] synthesizing module 'SeedFinder' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SeedFinder.vhd:34] INFO: [Synth 8-256] done synthesizing module 'SeedFinder' (101#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SeedFinder.vhd:34] INFO: [Synth 8-638] synthesizing module 'egInputMultiplexer' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/egInputMultiplexer.vhd:48] INFO: [Synth 8-256] done synthesizing module 'egInputMultiplexer' (102#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/egInputMultiplexer.vhd:48] INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 4 - type: integer Parameter size bound to: 28 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized1' (102#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-638] synthesizing module 'MultiAdder' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] Parameter stage bound to: 7 - type: integer Parameter delay bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'Adder' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/Adder.vhd:27] INFO: [Synth 8-256] done synthesizing module 'Adder' (103#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/Adder.vhd:27] WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:63] INFO: [Synth 8-256] done synthesizing module 'MultiAdder' (104#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdder__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] Parameter stage bound to: 4 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:63] INFO: [Synth 8-256] done synthesizing module 'MultiAdder__parameterized0' (104#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdder__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] Parameter stage bound to: 3 - type: integer Parameter delay bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'MultiAdder__parameterized1' (104#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdder__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] Parameter stage bound to: 4 - type: integer Parameter delay bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'MultiAdder__parameterized2' (104#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdder__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] Parameter stage bound to: 5 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:63] INFO: [Synth 8-256] done synthesizing module 'MultiAdder__parameterized3' (104#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdder__parameterized4' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] Parameter stage bound to: 4 - type: integer Parameter delay bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'MultiAdder__parameterized4' (104#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiAdder.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiMultiplier' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiMultiplier.vhd:21] Parameter parameters bound to: 3 - type: integer Parameter FAST bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'Mult' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/Mult_stub.vhdl:15] INFO: [Synth 8-256] done synthesizing module 'MultiMultiplier' (105#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiMultiplier.vhd:21] INFO: [Synth 8-638] synthesizing module 'MultiMultiplier__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiMultiplier.vhd:21] Parameter parameters bound to: 3 - type: integer Parameter FAST bound to: 1 - type: bool INFO: [Synth 8-638] synthesizing module 'FastMult' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/FastMult_stub.vhdl:15] INFO: [Synth 8-256] done synthesizing module 'MultiMultiplier__parameterized0' (105#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/MultiMultiplier.vhd:21] INFO: [Synth 8-638] synthesizing module 'Delay' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/Delay.vhd:28] Parameter delay bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'Delay' (106#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/Delay.vhd:28] INFO: [Synth 8-638] synthesizing module 'Delay__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/Delay.vhd:28] Parameter delay bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'Delay__parameterized0' (106#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/Delay.vhd:28] INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 9 - type: integer Parameter size bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized2' (106#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 2 - type: integer Parameter size bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized3' (106#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-256] done synthesizing module 'AlgoCore_eg' (107#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoCore_eg.vhd:75] INFO: [Synth 8-638] synthesizing module 'AlgoCore_tau_bdt' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/AlgoCore_tau_bdt.vhd:76] Parameter TAU_ALGO_VERSION bound to: 2'b10 INFO: [Synth 8-638] synthesizing module 'AdderTree' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/AdderTree.vhd:190] INFO: [Synth 8-638] synthesizing module 'MultiAdderWithCarry' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] Parameter stage bound to: 2 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:66] INFO: [Synth 8-256] done synthesizing module 'MultiAdderWithCarry' (108#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdderWithCarry__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] Parameter stage bound to: 1 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:66] INFO: [Synth 8-256] done synthesizing module 'MultiAdderWithCarry__parameterized0' (108#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdderWithCarry__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] Parameter stage bound to: 4 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:66] INFO: [Synth 8-256] done synthesizing module 'MultiAdderWithCarry__parameterized1' (108#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdderWithCarry__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] Parameter stage bound to: 5 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:66] INFO: [Synth 8-256] done synthesizing module 'MultiAdderWithCarry__parameterized2' (108#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] INFO: [Synth 8-638] synthesizing module 'MultiAdderWithCarry__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] Parameter stage bound to: 3 - type: integer Parameter delay bound to: 0 - type: integer WARNING: [Synth 8-3919] null assignment ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:66] INFO: [Synth 8-256] done synthesizing module 'MultiAdderWithCarry__parameterized3' (108#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/MultiAdderWithCarry.vhd:34] INFO: [Synth 8-638] synthesizing module 'DelayWithCarry' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] Parameter delay bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'DelayWithCarry' (109#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] INFO: [Synth 8-638] synthesizing module 'DelayWithCarry__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] Parameter delay bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'DelayWithCarry__parameterized0' (109#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] INFO: [Synth 8-638] synthesizing module 'DelayWithCarry__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] Parameter delay bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'DelayWithCarry__parameterized1' (109#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] INFO: [Synth 8-256] done synthesizing module 'AdderTree' (110#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/AdderTree.vhd:190] INFO: [Synth 8-638] synthesizing module 'TauSeedFinder' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauSeedFinder.vhd:32] INFO: [Synth 8-256] done synthesizing module 'TauSeedFinder' (111#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauSeedFinder.vhd:32] INFO: [Synth 8-638] synthesizing module 'BDTModel' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel.vhd:30] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_31' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_31.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 7 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 7 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 7 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 7 - type: integer Parameter def_WIDTH bound to: 7 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'BDTModel_sparsemux_9_2_7_1_1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_7_1_1.vhd:55] Parameter din0_WIDTH bound to: 7 - type: integer Parameter din1_WIDTH bound to: 7 - type: integer Parameter din2_WIDTH bound to: 7 - type: integer Parameter din3_WIDTH bound to: 7 - type: integer Parameter def_WIDTH bound to: 7 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 7 - type: integer Parameter CASE0 bound to: 2'b00 Parameter CASE1 bound to: 2'b01 Parameter CASE2 bound to: 2'b10 Parameter CASE3 bound to: 2'b11 Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_7_1_1.vhd:63] INFO: [Synth 8-256] done synthesizing module 'BDTModel_sparsemux_9_2_7_1_1' (112#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_7_1_1.vhd:55] INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_31' (113#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_31.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_30' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_30.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'BDTModel_sparsemux_9_2_6_1_1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1.vhd:55] Parameter din0_WIDTH bound to: 6 - type: integer Parameter din1_WIDTH bound to: 6 - type: integer Parameter din2_WIDTH bound to: 6 - type: integer Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer Parameter CASE0 bound to: 2'b00 Parameter CASE1 bound to: 2'b01 Parameter CASE2 bound to: 2'b10 Parameter CASE3 bound to: 2'b11 Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1.vhd:63] INFO: [Synth 8-256] done synthesizing module 'BDTModel_sparsemux_9_2_6_1_1' (114#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1.vhd:55] INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_30' (115#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_30.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_19' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_19.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_19' (116#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_19.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_8' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_8.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'BDTModel_sparsemux_9_2_6_1_1_x' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1_x.vhd:55] Parameter din0_WIDTH bound to: 6 - type: integer Parameter din1_WIDTH bound to: 6 - type: integer Parameter din2_WIDTH bound to: 6 - type: integer Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer Parameter CASE0 bound to: 2'b00 Parameter CASE1 bound to: 2'b01 Parameter CASE2 bound to: 2'b10 Parameter CASE3 bound to: 2'b11 Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1_x.vhd:63] INFO: [Synth 8-256] done synthesizing module 'BDTModel_sparsemux_9_2_6_1_1_x' (117#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_6_1_1_x.vhd:55] INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_8' (118#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_8.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_5' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_5.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_5' (119#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_5.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_4' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_4.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_4' (120#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_4.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_3.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_3' (121#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_3.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_2.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_2' (122#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_2.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_1.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_1' (123#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_1.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function' (124#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_29' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_29.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_29' (125#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_29.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_28' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_28.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_28' (126#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_28.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_27' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_27.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_27' (127#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_27.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_26' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_26.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_26' (128#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_26.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_25' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_25.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_25' (129#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_25.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_24' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_24.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_24' (130#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_24.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_23' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_23.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_23' (131#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_23.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_22' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_22.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_22' (132#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_22.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_21' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_21.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_21' (133#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_21.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_20' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_20.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_20' (134#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_20.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_18' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_18.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_18' (135#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_18.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_17' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_17.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_17' (136#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_17.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_16' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_16.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_16' (137#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_16.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_15' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_15.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_15' (138#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_15.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_14' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_14.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_14' (139#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_14.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_13' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_13.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_13' (140#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_13.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_12' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_12.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_12' (141#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_12.vhd:20] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_11' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_11.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_11' (142#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_11.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_10' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_10.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 7 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 7 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 7 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 7 - type: integer Parameter def_WIDTH bound to: 7 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'BDTModel_sparsemux_9_2_7_1_1_x' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_7_1_1_x.vhd:55] Parameter din0_WIDTH bound to: 7 - type: integer Parameter din1_WIDTH bound to: 7 - type: integer Parameter din2_WIDTH bound to: 7 - type: integer Parameter din3_WIDTH bound to: 7 - type: integer Parameter def_WIDTH bound to: 7 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 7 - type: integer Parameter CASE0 bound to: 2'b00 Parameter CASE1 bound to: 2'b01 Parameter CASE2 bound to: 2'b10 Parameter CASE3 bound to: 2'b11 Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_7_1_1_x.vhd:63] INFO: [Synth 8-256] done synthesizing module 'BDTModel_sparsemux_9_2_7_1_1_x' (143#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_sparsemux_9_2_7_1_1_x.vhd:55] INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_10' (144#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_10.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_9' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_9.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_9' (145#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_9.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_7' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_7.vhd:21] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_7' (146#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_7.vhd:21] INFO: [Synth 8-638] synthesizing module 'BDTModel_decision_function_6' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_6.vhd:20] Parameter ID bound to: 1 - type: integer Parameter NUM_STAGE bound to: 1 - type: integer Parameter CASE0 bound to: 2'b00 Parameter din0_WIDTH bound to: 6 - type: integer Parameter CASE1 bound to: 2'b01 Parameter din1_WIDTH bound to: 6 - type: integer Parameter CASE2 bound to: 2'b10 Parameter din2_WIDTH bound to: 6 - type: integer Parameter CASE3 bound to: 2'b11 Parameter din3_WIDTH bound to: 6 - type: integer Parameter def_WIDTH bound to: 6 - type: integer Parameter sel_WIDTH bound to: 2 - type: integer Parameter dout_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'BDTModel_decision_function_6' (147#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel_decision_function_6.vhd:20] INFO: [Synth 8-256] done synthesizing module 'BDTModel' (148#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/HLS/BDTModel.vhd:30] INFO: [Synth 8-638] synthesizing module 'DelayTree' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayTree.vhd:121] INFO: [Synth 8-638] synthesizing module 'DelayWithCarry__parameterized2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] Parameter delay bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'DelayWithCarry__parameterized2' (148#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] INFO: [Synth 8-638] synthesizing module 'DelayWithCarry__parameterized3' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] Parameter delay bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'DelayWithCarry__parameterized3' (148#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayWithCarry.vhd:28] INFO: [Synth 8-256] done synthesizing module 'DelayTree' (149#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/DelayTree.vhd:121] INFO: [Synth 8-638] synthesizing module 'TauConditionsEnergyAndSeed' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/TauConditionsEnergyAndSeed.vhd:21] INFO: [Synth 8-256] done synthesizing module 'TauConditionsEnergyAndSeed' (150#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/TauConditionsEnergyAndSeed.vhd:21] INFO: [Synth 8-638] synthesizing module 'TauConditionsBDT' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/TauConditionsBDT.vhd:23] INFO: [Synth 8-256] done synthesizing module 'TauConditionsBDT' (151#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/TauConditionsBDT.vhd:23] INFO: [Synth 8-638] synthesizing module 'TauConditionsFrac' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/TauConditionsFrac.vhd:23] INFO: [Synth 8-256] done synthesizing module 'TauConditionsFrac' (152#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/TauConditionsFrac.vhd:23] INFO: [Synth 8-256] done synthesizing module 'AlgoCore_tau_bdt' (153#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TauBDT/AlgoCore_tau_bdt.vhd:76] INFO: [Synth 8-256] done synthesizing module 'TopAlgoModule' (154#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TopAlgoModule.vhd:91] INFO: [Synth 8-638] synthesizing module 'SerialSorter' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SerialSorter.vhd:32] INFO: [Synth 8-638] synthesizing module 'SortingCell' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SortingCell.vhd:37] INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SortingCell.vhd:65] INFO: [Synth 8-256] done synthesizing module 'SortingCell' (155#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SortingCell.vhd:37] INFO: [Synth 8-256] done synthesizing module 'SerialSorter' (156#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/SerialSorter.vhd:32] INFO: [Synth 8-638] synthesizing module 'AlgoRateMonitor' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoRateMonitor.vhd:48] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized7' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 2 - type: integer Parameter N_STAT bound to: 98 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized7' (156#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'counter' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] Parameter DEPTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'counter' (157#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] INFO: [Synth 8-256] done synthesizing module 'AlgoRateMonitor' (158#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoRateMonitor.vhd:48] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized8' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 64 - type: integer Parameter N_STAT bound to: 64 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized8' (158#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'AlgoParameterRAM_wrapper' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoParameterRAM_wrapper.vhd:59] INFO: [Synth 8-638] synthesizing module 'AlgoParameterRAM' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/AlgoParameterRAM_stub.vhdl:23] INFO: [Synth 8-256] done synthesizing module 'AlgoParameterRAM_wrapper' (159#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/AlgoParameterRAM_wrapper.vhd:59] INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized4' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 12 - type: integer Parameter size bound to: 12 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized4' (159#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized5' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 24 - type: integer Parameter size bound to: 12 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized5' (159#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] WARNING: [Synth 8-6026] Ignoring keep related attribute (keep/mark_debug/dont_touch) applied on memory [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopAlgoModule.vhd:136] INFO: [Synth 8-256] done synthesizing module 'IPBusTopAlgoModule' (160#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopAlgoModule.vhd:113] INFO: [Synth 8-638] synthesizing module 'IPBusTopSortingModule' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopSortingModule.vhd:56] Parameter USE_INPUT_RAM bound to: 0 - type: bool Parameter USE_OUTPUT_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized6' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 5 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized6' (160#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized9' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 4 - type: integer Parameter N_STAT bound to: 4 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized9' (160#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'TopSortingModule' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TopSortingModule.vhd:40] Parameter STAGE bound to: 3 - type: integer Parameter N_TOBS bound to: 5 - type: integer INFO: [Synth 8-638] synthesizing module 'ParallelSorter' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ParallelSorter.vhd:40] Parameter USE_EXTERNAL_WRITE bound to: 1 - type: bool Parameter N_TOBS_IN bound to: 7 - type: integer Parameter N_TOBS_OUT bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'FastFifo' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/FastFifo.vhd:39] Parameter FASTFIFO_DATA_DEPTH bound to: 7 - type: integer Parameter FASTFIFO_ADDRESS_DEPTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'FastFifo' (161#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/FastFifo.vhd:39] INFO: [Synth 8-256] done synthesizing module 'ParallelSorter' (162#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ParallelSorter.vhd:40] INFO: [Synth 8-638] synthesizing module 'ParallelSorter__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ParallelSorter.vhd:40] Parameter USE_EXTERNAL_WRITE bound to: 0 - type: bool Parameter N_TOBS_IN bound to: 5 - type: integer Parameter N_TOBS_OUT bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ParallelSorter__parameterized0' (162#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ParallelSorter.vhd:40] INFO: [Synth 8-256] done synthesizing module 'TopSortingModule' (163#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TopSortingModule.vhd:40] INFO: [Synth 8-638] synthesizing module 'GeneralDelay__parameterized6' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] Parameter delay bound to: 7 - type: integer Parameter size bound to: 12 - type: integer INFO: [Synth 8-256] done synthesizing module 'GeneralDelay__parameterized6' (163#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/GeneralDelay.vhd:23] INFO: [Synth 8-256] done synthesizing module 'IPBusTopSortingModule' (164#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopSortingModule.vhd:56] INFO: [Synth 8-638] synthesizing module 'local_bcn_counter' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/local_bcn_counter.vhd:15] INFO: [Synth 8-256] done synthesizing module 'local_bcn_counter' (165#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/local_bcn_counter.vhd:15] INFO: [Synth 8-256] done synthesizing module 'data_path_block' (166#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/data_path_block.vhd:151] INFO: [Synth 8-638] synthesizing module 'MGT_4_quad_gen' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/MGT_4_quad_gen.vhd:91] Parameter num_quad_tx_rx bound to: 20 - type: integer Parameter QUAD_ENABLE bound to: 20'b11101100011111111111 INFO: [Synth 8-638] synthesizing module 'mgt_selection_wrapper' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_selection_wrapper.vhd:214] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer Parameter ENABLED bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'min_latency_1quad_11g2_RxTX_wrapper' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1quad_11g2_RxTX_wrapper.vhd:212] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'min_latency_1_quad_rx_tx_support' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_support.vhd:379] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_gt_usrclk_source.vhd:112] Parameter CLKCM_CFG bound to: 1 - type: bool Parameter CLKRCV_TRST bound to: 1 - type: bool Parameter CLKSWING_CFG bound to: 2'b11 INFO: [Synth 8-256] done synthesizing module 'min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE' (167#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_gt_usrclk_source.vhd:112] INFO: [Synth 8-638] synthesizing module 'min_latency_1_quad_rx_tx_common' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_common.vhd:92] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000001011100 Parameter IS_DRPCLK_INVERTED bound to: 1'b0 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 Parameter IS_QPLLLOCKDETCLK_INVERTED bound to: 1'b0 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'min_latency_1_quad_rx_tx_common' (168#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_common.vhd:92] INFO: [Synth 8-638] synthesizing module 'min_latency_1_quad_rx_tx_common_reset' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-226] default block is never used [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'min_latency_1_quad_rx_tx_common_reset' (169#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_common_reset.vhd:91] INFO: [Synth 8-638] synthesizing module 'min_latency_1_quad_rx_tx' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/min_latency_1_quad_rx_tx_stub.vhdl:224] INFO: [Synth 8-256] done synthesizing module 'min_latency_1_quad_rx_tx_support' (170#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1_quad_rx_tx_support.vhd:379] INFO: [Synth 8-256] done synthesizing module 'min_latency_1quad_11g2_RxTX_wrapper' (171#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1quad_11g2_RxTX_wrapper.vhd:212] INFO: [Synth 8-256] done synthesizing module 'mgt_selection_wrapper' (172#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_selection_wrapper.vhd:214] INFO: [Synth 8-638] synthesizing module 'mgt_selection_wrapper__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_selection_wrapper.vhd:214] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer Parameter ENABLED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'mgt_selection_wrapper__parameterized0' (172#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_selection_wrapper.vhd:214] INFO: [Synth 8-256] done synthesizing module 'MGT_4_quad_gen' (173#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/MGT_4_quad_gen.vhd:91] INFO: [Synth 8-638] synthesizing module 'mgt_slaves' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_slaves.vhd:150] Parameter MGT_QUAD_ENABLE bound to: 20'b11101100011111111111 Parameter MGT_USE_OTHER_CLK bound to: 20'b00000000010000000000 Parameter MGT_TX_POWER bound to: 80'b11111111111100000000000000000000000000110000000000000000000000000000000000000000 Parameter MGT_RX_POWER bound to: 80'b11111111111100000000111100000000000000001111111111111111111111111111111111111111 INFO: [Synth 8-638] synthesizing module 'mgt_quad_slaves' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd:132] Parameter ENABLE bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized7' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 9 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized7' (173#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'led_stretch' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/led_stretch.vhd:23] INFO: [Synth 8-256] done synthesizing module 'led_stretch' (174#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/led_stretch.vhd:23] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd:245] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd:258] INFO: [Common 17-14] Message 'Synth 8-6778' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'gt_information' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/gt_information.vhd:85] Parameter addr_width bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt_playback_ram_wrapper' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_playback_ram_wrapper.vhd:47] Parameter DISABLE bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_playback_ram' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/mgt_playback_ram_stub.vhdl:23] INFO: [Synth 8-638] synthesizing module 'ctrl_playback_ram' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/ctrl_playback_ram.vhd:38] INFO: [Synth 8-256] done synthesizing module 'ctrl_playback_ram' (175#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/ctrl_playback_ram.vhd:38] INFO: [Synth 8-256] done synthesizing module 'mgt_playback_ram_wrapper' (176#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_playback_ram_wrapper.vhd:47] INFO: [Synth 8-638] synthesizing module 'counter__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] Parameter DEPTH bound to: 16 - type: integer INFO: [Synth 8-256] done synthesizing module 'counter__parameterized0' (176#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] INFO: [Synth 8-256] done synthesizing module 'gt_information' (177#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/gt_information.vhd:85] INFO: [Synth 8-256] done synthesizing module 'mgt_quad_slaves' (178#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd:132] INFO: [Synth 8-638] synthesizing module 'mgt_quad_slaves__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd:132] Parameter ENABLE bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized8' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 9 - type: integer Parameter STROBE_GAP bound to: 0 - type: bool Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized8' (178#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-256] done synthesizing module 'mgt_quad_slaves__parameterized0' (178#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd:132] INFO: [Synth 8-256] done synthesizing module 'mgt_slaves' (179#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_slaves.vhd:150] INFO: [Synth 8-638] synthesizing module 'IPBusTopMergingModule' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopMergingModule.vhd:52] Parameter TEST bound to: 0 - type: bool Parameter ENABLE bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized10' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 3 - type: integer Parameter N_STAT bound to: 2 - type: integer Parameter SWAP_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized10' (179#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'TOB_synch' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TOB_synch.vhd:42] INFO: [Synth 8-256] done synthesizing module 'TOB_synch' (180#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TOB_synch.vhd:42] INFO: [Synth 8-638] synthesizing module 'TopSortingModule__parameterized0' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TopSortingModule.vhd:40] Parameter STAGE bound to: 2 - type: integer Parameter N_TOBS bound to: 7 - type: integer INFO: [Synth 8-638] synthesizing module 'ParallelSorter__parameterized1' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ParallelSorter.vhd:40] Parameter USE_EXTERNAL_WRITE bound to: 0 - type: bool Parameter N_TOBS_IN bound to: 7 - type: integer Parameter N_TOBS_OUT bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ParallelSorter__parameterized1' (180#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ParallelSorter.vhd:40] INFO: [Synth 8-256] done synthesizing module 'TopSortingModule__parameterized0' (180#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/TopSortingModule.vhd:40] INFO: [Synth 8-638] synthesizing module 'ipbus_sorting_outputRAM_wrapper' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ipbus_sorting_outputRAM_wrapper.vhd:32] INFO: [Synth 8-638] synthesizing module 'SortingOutputRAM' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/SortingOutputRAM_stub.vhdl:23] INFO: [Synth 8-256] done synthesizing module 'ipbus_sorting_outputRAM_wrapper' (181#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/ipbus_sorting_outputRAM_wrapper.vhd:32] INFO: [Synth 8-256] done synthesizing module 'IPBusTopMergingModule' (182#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Algorithm/hdl/IPBusTopMergingModule.vhd:52] INFO: [Synth 8-638] synthesizing module 'efex_topo_tx' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/efex_topo_tx.vhd:60] Parameter NCOUNTERS bound to: 12 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_topo_frame_sm' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/efex_topo_frame_sm.vhd:46] INFO: [Synth 8-256] done synthesizing module 'efex_topo_frame_sm' (183#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/efex_topo_frame_sm.vhd:46] INFO: [Synth 8-256] done synthesizing module 'efex_topo_tx' (184#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/efex_topo_tx.vhd:60] Parameter SYS_W bound to: 16 - type: integer Parameter DEV_W bound to: 16 - type: integer INFO: [Synth 8-638] synthesizing module 'io_delay' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/io_delay_stub.vhdl:24] Parameter SYS_W bound to: 16 - type: integer Parameter DEV_W bound to: 16 - type: integer Parameter SYS_W bound to: 16 - type: integer Parameter DEV_W bound to: 16 - type: integer Parameter SYS_W bound to: 16 - type: integer Parameter DEV_W bound to: 16 - type: integer Parameter SYS_W bound to: 16 - type: integer Parameter DEV_W bound to: 16 - type: integer Parameter SYS_W bound to: 16 - type: integer Parameter DEV_W bound to: 16 - type: integer Parameter SYS_W bound to: 1 - type: integer Parameter DEV_W bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'io_delay2' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/.Xil/Vivado-2332925-efex-heavyduty-vm1.cern.ch/realtime/io_delay2_stub.vhdl:24] Parameter SYS_W bound to: 1 - type: integer Parameter DEV_W bound to: 1 - type: integer Parameter SYS_W bound to: 1 - type: integer Parameter DEV_W bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'top_efex_processor' (185#1) [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd:202] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 3254.094 ; gain = 480.234 ; free physical = 19970 ; free virtual = 57157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 3265.969 ; gain = 492.109 ; free physical = 20016 ; free virtual = 57203 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 3265.969 ; gain = 492.109 ; free physical = 20016 ; free virtual = 57203 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3769.930 ; gain = 12.000 ; free physical = 18536 ; free virtual = 55998 INFO: [Netlist 29-17] Analyzing 75 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM/AlgoParameterRAM_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM/AlgoParameterRAM_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_1/ALGO_OUTPUT_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_1/ALGO_OUTPUT_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_2/ALGO_OUTPUT_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_2/ALGO_OUTPUT_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_3/ALGO_OUTPUT_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_3/ALGO_OUTPUT_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_4/ALGO_OUTPUT_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_4/ALGO_OUTPUT_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/outputRAM/ALGO_OUTPUT_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM/SortingOutputRAM_in_context.xdc] for cell 'GLOBAL_MERGE.Merging_Module/outputRAM/ALGO_OUTPUT_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult/Mult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult/FastMult_in_context.xdc] for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U3_DPRAM_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024/DPR_36b_1024_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U3_DPRAM_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_209b_512/DPR_209b_512/DPR_209b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U4_T_TOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_209b_512/DPR_209b_512/DPR_209b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U4_T_TOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512/DPR_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192/FIFO_33b_8192_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192/FIFO_33b_8192_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192/FIFO_33b_8192_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192/FIFO_33b_8192_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512/FIFO_36b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512/FIFO_47b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512/FIFO_47b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512/FIFO_47b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512/FIFO_47b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512/FIFO_54b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512/FIFO_54b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512/FIFO_209b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512/FIFO_209b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512/FIFO_252b_512_in_context.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1/clk_wiz_1_in_context.xdc] for cell 'clock_resources/clk40_gen' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1/clk_wiz_1_in_context.xdc] for cell 'clock_resources/clk40_gen' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc] for cell 'clock_resources/Inputclk40M' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard/ClockWizard_in_context.xdc] for cell 'clock_resources/Inputclk40M' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx/min_latency_1_quad_rx_tx_in_context.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[1].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[2].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[3].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[4].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[5].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[6].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[7].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[8].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[10].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[14].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[15].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[17].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT1/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT2/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram/mgt_playback_ram_in_context.xdc] for cell 'MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C' Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C' Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc] Finished Parsing XDC File [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_efex_processor_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_efex_processor_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 4474.430 ; gain = 0.000 ; free physical = 17628 ; free virtual = 55119 INFO: [Project 1-111] Unisim Transformation Summary: A total of 69 instances were transformed. IBUFGDS => IBUFDS: 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 66 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4474.430 ; gain = 0.000 ; free physical = 17598 ; free virtual = 55091 WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_A1' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_A2' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_B1' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_B2' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_BC_A' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_BC_B' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_BC_C' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_C1' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GLOBAL_MERGE.IO_DELAY_C2' at clock pin 'clk_in' is different from the actual clock period '3.563', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' at clock pin 'clkb' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' at clock pin 'CLK' is different from the actual clock period '4.988', this can lead to different synthesis results. INFO: [Common 17-14] Message 'Timing 38-316' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:01:44 ; elapsed = 00:01:48 . Memory (MB): peak = 4474.430 ; gain = 1700.570 ; free physical = 18806 ; free virtual = 56313 --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 48). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 49). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 50). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 53). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 54). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 55). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 56). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 57). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 58). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 61). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 62). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 63). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 64). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 48). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 49). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 50). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 53). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 54). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 55). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 56). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 57). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 58). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 61). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 62). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 63). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 64). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 48). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 49). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 50). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 53). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 54). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 55). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 56). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 57). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 58). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 61). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 62). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 63). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 64). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 48). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 49). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 50). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 53). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 54). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 55). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 56). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 57). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 58). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 61). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 62). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 63). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 64). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [0]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [10]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [11]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [12]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [13]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [14]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [15]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [1]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 48). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 49). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [2]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 50). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [3]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 53). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [4]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 54). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 55). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [5]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 56). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 57). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [6]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 58). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [7]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 61). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [8]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 62). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 63). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [9]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 64). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [16]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [26]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [27]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [28]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [29]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [30]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [31]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [17]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 48). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 49). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [18]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 50). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [19]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 53). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [20]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 54). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 55). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [21]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 56). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 57). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [22]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 58). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [23]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 61). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [24]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 62). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 63). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [25]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay/io_delay_in_context.xdc, line 64). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_n] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_A_p] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_n] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_B_p] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 4). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 1). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_n] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 2). Applied set_property IO_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for \efex_in[data_from_fpga_C_p] [32]. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2/io_delay2_in_context.xdc, line 4). Applied set_property BLOCK_SYNTH.MUXF_MAPPING = 1 for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE. (constraint file /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc, line 1). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.Merging_Module /inputRAM_1/ALGO_OUTPUT_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.Merging_Module /inputRAM_2/ALGO_OUTPUT_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.Merging_Module /inputRAM_3/ALGO_OUTPUT_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.Merging_Module /inputRAM_4/ALGO_OUTPUT_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.Merging_Module /outputRAM/ALGO_OUTPUT_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[0].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[1].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /RETA_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /WS_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT /Frac_MULTIPLIER/\MULT_FOR[2].SPEED.MULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[0].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[1].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[0].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[1].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[2].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[3].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[4].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[5].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[6].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \DATA_PATH_IF.data_path_Module /algorithm_block/TOP_ALGO_MODULE/\ALGO_GENERATION[7].AGLO_CORE_EG /HADRON_MULTIPLIER/\MULT_FOR[2].SPEED.FASTMULTIPLIER . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[0].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[10].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[11].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[12].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[13].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[14].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[15].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[16].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[17].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[18].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[19].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[1].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[20].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[21].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[22].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[23].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[24].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[25].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[26].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[27].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[28].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[29].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[2].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[30].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[31].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[32].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[33].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[34].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[35].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[36].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[37].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[38].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[39].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[3].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[40].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[41].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[42].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[43].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[44].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[45].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[46].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[47].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[48].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[4].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[5].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[6].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[7].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[8].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[9].U3_DPRAM_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/\U1_TOB_sorting_gen.U1_TOBs_sorting /U4_T_TOB_DRP. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[0].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[0].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[1].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[1].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[2].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[2].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[3].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[3].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[4].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[4].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[5].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[5].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[6].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[6].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[7].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[7].U3_XTOB_DRP . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U7_Link_output_FIFO. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/U8_RAW_Link_output_FIFO. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[0].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[10].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[11].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[12].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[13].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[14].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[15].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[16].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[17].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[18].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[19].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[1].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[20].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[21].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[22].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[23].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[24].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[25].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[26].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[27].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[28].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[29].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[2].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[30].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[31].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[32].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[33].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[34].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[35].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[36].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[37].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[38].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[39].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[3].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[40].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[41].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[42].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[43].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[44].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[45].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[46].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[47].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[48].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[4].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[5].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[6].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[7].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[8].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/\GEN_CHANNEL[9].U4_FIFO_RAW_Data . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U0_FIFO_BCN_L1A. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/U6_FIFO_BCN_L1A. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U1_RAW_readout/U5_FIFO_link_err. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/\U1_TOB_sorting_gen.U1_TOBs_sorting /U5_T_TOBs_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[0].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[0].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[1].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[1].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[2].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[2].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[3].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[3].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[4].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[4].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[5].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[5].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[6].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[6].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U2_XTOBs_eg_sorting/\GEN_XTOB_RAM[7].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \READOUT_IF.Readout_block /U0_TOBs_readout/U3_XTOBs_tau_sorting/\GEN_XTOB_RAM[7].U5_XTOBs_FIFO . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for clock_resources/clk40_gen. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for clock_resources/Inputclk40M. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[0].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[1].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[2].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[3].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[4].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[5].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[6].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[7].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[8].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[9].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[10].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[14].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[15].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[17].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[18].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_TX_RX /\MGT_GEN[19].mgt_1quad_Rx_Tx /\QUAD_ENABLED.mgt /min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[0].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[0].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[0].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[0].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[1].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[1].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[1].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[1].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[2].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[2].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[2].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[2].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[3].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[3].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[3].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[3].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[4].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[4].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[4].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[4].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[5].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[5].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[5].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[5].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[6].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[6].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[6].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[6].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[7].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[7].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[7].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[7].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[8].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[8].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[8].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[8].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[9].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[9].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[9].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[9].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[10].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[10].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[10].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[10].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[11].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[11].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[11].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[11].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[12].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[12].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[12].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[12].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[13].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[13].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[13].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[13].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[14].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[14].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[14].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[14].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[15].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[15].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[15].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[15].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[16].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[16].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[16].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[16].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[17].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[17].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[17].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[17].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[18].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[18].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[18].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[18].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[19].quad /MGT_GT0/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[19].quad /MGT_GT1/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[19].quad /MGT_GT2/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \MGT_IF.MGT_ipb /\QUAD_FOR[19].quad /MGT_GT3/playback_ram/PLAYBACK_RAM. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_A1 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_A2 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_B1 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_B2 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_C1 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_C2 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_BC_A . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_BC_B . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GLOBAL_MERGE.IO_DELAY_BC_C . (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 4478.348 ; gain = 1704.488 ; free physical = 18556 ; free virtual = 56066 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'xadc_eFEX' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'command_sync' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control' INFO: [Synth 8-802] inferred FSM for state register 'NEXT_STATE_reg' in module 'reconfig' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'fsm_TOB_wr_to_FIFO' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'fsm_TOBs_to_muxPISO' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'FIFO_to_MGT_TOB_FSM' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'PISO_RAW_data' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'fsm_RAW_data_wr_to_DPR' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'fsm_RAW_to_muxPISO' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'FIFO_to_MGT_RAW_FSM' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'orbit_sm' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'tac_sm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'AlgoRateMonitor' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'ctrl_playback_ram' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'efex_topo_frame_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init_read | 00000000000000000000000000000000000000001 | 000000 read_waitdrdy | 00000000000000000000000000000000000000010 | 000001 write_waitdrdy | 00000000000000000000000000000000000000100 | 000010 read_reg00 | 00000000000000000000000000000000000001000 | 000011 reg00_waitdrdy | 00000000000000000000000000000000000010000 | 000100 read_reg01 | 00000000000000000000000000000000000100000 | 000101 reg01_waitdrdy | 00000000000000000000000000000000001000000 | 000110 read_reg02 | 00000000000000000000000000000000010000000 | 000111 reg02_waitdrdy | 00000000000000000000000000000000100000000 | 001000 read_reg03 | 00000000000000000000000000000001000000000 | 001001 reg03_waitdrdy | 00000000000000000000000000000010000000000 | 001010 read_reg06 | 00000000000000000000000000000100000000000 | 001011 reg06_waitdrdy | 00000000000000000000000000001000000000000 | 001100 read_reg10 | 00000000000000000000000000010000000000000 | 001101 reg10_waitdrdy | 00000000000000000000000000100000000000000 | 001110 read_reg11 | 00000000000000000000000001000000000000000 | 001111 reg11_waitdrdy | 00000000000000000000000010000000000000000 | 010000 read_reg12 | 00000000000000000000000100000000000000000 | 010001 reg12_waitdrdy | 00000000000000000000001000000000000000000 | 010010 read_reg13 | 00000000000000000000010000000000000000000 | 010011 reg13_waitdrdy | 00000000000000000000100000000000000000000 | 010100 read_reg14 | 00000000000000000001000000000000000000000 | 010101 reg14_waitdrdy | 00000000000000000010000000000000000000000 | 010110 read_reg15 | 00000000000000000100000000000000000000000 | 010111 reg15_waitdrdy | 00000000000000001000000000000000000000000 | 011000 read_reg20 | 00000000000000010000000000000000000000000 | 011001 reg20_waitdrdy | 00000000000000100000000000000000000000000 | 011010 read_reg21 | 00000000000001000000000000000000000000000 | 011011 reg21_waitdrdy | 00000000000010000000000000000000000000000 | 011100 read_reg22 | 00000000000100000000000000000000000000000 | 011101 reg22_waitdrdy | 00000000001000000000000000000000000000000 | 011110 read_reg23 | 00000000010000000000000000000000000000000 | 011111 reg23_waitdrdy | 00000000100000000000000000000000000000000 | 100000 read_reg24 | 00000001000000000000000000000000000000000 | 100001 reg24_waitdrdy | 00000010000000000000000000000000000000000 | 100010 read_reg25 | 00000100000000000000000000000000000000000 | 100011 reg25_waitdrdy | 00001000000000000000000000000000000000000 | 100100 read_reg26 | 00010000000000000000000000000000000000000 | 100101 reg26_waitdrdy | 00100000000000000000000000000000000000000 | 100110 read_reg27 | 01000000000000000000000000000000000000000 | 100111 reg27_waitdrdy | 10000000000000000000000000000000000000000 | 101000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'xadc_eFEX' INFO: [Synth 8-3971] The signal "ipbus_dpram_flash:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized0:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0001 | 00 request | 0010 | 01 done | 0100 | 10 iSTATE | 1000 | 11 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'one-hot' in module 'command_sync' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 data_00 | 0001 | 0001 data_01 | 0010 | 0010 data_02 | 0011 | 0011 data_03 | 0100 | 0100 data_04 | 0101 | 0101 data_05 | 0110 | 0110 data_06 | 0111 | 0111 data_07 | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'NEXT_STATE_reg' using encoding 'sequential' in module 'reconfig' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 000 ser_1 | 010 | 001 ser_4 | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'one-hot' in module 'fsm_TOB_wr_to_FIFO' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000000000000000001 | 00000 idle_1 | 00000000000000000010 | 00001 wait5 | 00000000000000000100 | 00110 rd_fifo | 00000000000000001000 | 01101 norm_sop1 | 00000000000000010000 | 01001 norm_sop2 | 00000000000000100000 | 01010 rdout_t_tob_eg | 00000000000001000000 | 10000 rdout_xtob_eg_a0 | 00000000000010000000 | 10001 rdout_xtob_eg_b | 00000000000100000000 | 10011 rdout_xtob_tau_a0 | 00000000001000000000 | 10100 rdout_xtob_tau_b | 00000000010000000000 | 10110 wait1 | 00000000100000000000 | 00010 sub_trl_1 | 00000001000000000000 | 01110 sub_trl_2 | 00000010000000000000 | 01111 wait3 | 00000100000000000000 | 00100 wait4 | 00001000000000000000 | 00101 norm_eop | 00010000000000000000 | 01100 wait2 | 00100000000000000000 | 00011 rdout_xtob_tau_a | 01000000000000000000 | 10101 rdout_xtob_eg_a | 10000000000000000000 | 10010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'one-hot' in module 'fsm_TOBs_to_muxPISO' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 rd_fifo1 | 0001 | 0001 tx_data_sof1 | 0010 | 0011 tx_data1 | 0011 | 0101 tx_data_eof1 | 0100 | 0111 wait1 | 0101 | 1001 wait2 | 0110 | 1010 tx_data_eof2 | 0111 | 1000 wait3 | 1000 | 1011 wait4 | 1001 | 1100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'FIFO_to_MGT_TOB_FSM' INFO: [Synth 8-3971] The signal "ipbus_dpram:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 ser_1 | 001 | 001 ser_2 | 010 | 010 ser_3 | 011 | 011 ser_4 | 100 | 100 ser_5 | 101 | 101 ser_6 | 110 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'PISO_RAW_data' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 000 rd_mem | 01 | 001 wait_1 | 10 | 010 ser_1 | 11 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'fsm_RAW_data_wr_to_DPR' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000 | 00000 rd_bcn_fifo | 00001 | 10011 norm_sop_1 | 00010 | 01111 norm_sop_2 | 00011 | 10000 empty_raw_fifo | 00100 | 10100 wait_1 | 00101 | 00001 wait_2 | 00110 | 00010 wait_3 | 00111 | 00011 wait_4 | 01000 | 00100 rdout_raw_2 | 01001 | 10110 rdout_raw_3 | 01010 | 10111 sub_trl_1 | 01011 | 11100 sub_trl_2 | 01100 | 11101 wait_5 | 01101 | 00101 norm_eop | 01110 | 10010 wait_6 | 01111 | 00110 wait_7 | 10000 | 00111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'fsm_RAW_to_muxPISO' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 rd_fifo1 | 0001 | 0011 tx_data_sof1 | 0010 | 0101 tx_data1 | 0011 | 0111 tx_data_eof1 | 0100 | 1001 wait3 | 0101 | 1101 tx_data_eof2 | 0110 | 1010 wait1 | 0111 | 1011 wait2 | 1000 | 1100 decrement1 | 1001 | 0001 decrement2 | 1010 | 0010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'FIFO_to_MGT_RAW_FSM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * idle | 000001 | 000001 cnt0_inc | 000010 | 000010 cnt_ref0 | 000100 | 000100 cnt1_inc | 001000 | 001000 cnt_ref1 | 010000 | 010000 s1 | 100000 | 100000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'orbit_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 wt_rstdone | 01 | 01 wt_comma | 10 | 10 wt_ttc_redge | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'tac_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ready | 00 | 00 run | 01 | 10 idle | 10 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'AlgoRateMonitor' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 rd_en | 01 | 01 bcr_done | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'ctrl_playback_ram' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 str | 0001 | 0101 empty_data | 0010 | 1000 wait1 | 0011 | 0111 wait_2 | 0100 | 1010 wait0 | 0101 | 0110 wait_3 | 0110 | 1011 fin | 0111 | 1001 fin1 | 1000 | 1101 empty | 1001 | 0001 kchar | 1010 | 0011 empty_1 | 1011 | 0100 trialer_0 | 1100 | 0010 trialer_1 | 1101 | 1100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'efex_topo_frame_sm' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:02:32 ; elapsed = 00:02:41 . Memory (MB): peak = 4478.348 ; gain = 1704.488 ; free physical = 17219 ; free virtual = 54791 --------------------------------------------------------------------------------- INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U1_gen_sync_280' (gen_sync_280M) to 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U1_gen_sync_280' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_QUAD_Synch' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[11].quad/MGT_QUAD_PHASE' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_QUAD_Synch' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[12].quad/MGT_QUAD_PHASE' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_QUAD_Synch' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[13].quad/MGT_QUAD_PHASE' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_QUAD_Synch' INFO: [Synth 8-223] decloning instance 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_QUAD_Control' (ipbus_ctrlreg_v__parameterized2) to 'MGT_IF.MGT_ipb/QUAD_FOR[16].quad/MGT_QUAD_PHASE' --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 24 Bit Adders := 1 2 Input 17 Bit Adders := 3600 2 Input 16 Bit Adders := 2 2 Input 13 Bit Adders := 662 2 Input 12 Bit Adders := 3 2 Input 11 Bit Adders := 670 3 Input 11 Bit Adders := 8 2 Input 10 Bit Adders := 681 2 Input 9 Bit Adders := 42 3 Input 9 Bit Adders := 3 2 Input 8 Bit Adders := 698 4 Input 8 Bit Adders := 48 2 Input 7 Bit Adders := 25 2 Input 6 Bit Adders := 2 2 Input 5 Bit Adders := 257 2 Input 4 Bit Adders := 227 2 Input 3 Bit Adders := 157 2 Input 2 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 1262 13 Input 1 Bit XORs := 1 21 Input 1 Bit XORs := 66 3 Input 1 Bit XORs := 195 9 Input 1 Bit XORs := 131 4 Input 1 Bit XORs := 195 15 Input 1 Bit XORs := 65 10 Input 1 Bit XORs := 130 19 Input 1 Bit XORs := 65 14 Input 1 Bit XORs := 65 12 Input 1 Bit XORs := 65 7 Input 1 Bit XORs := 65 +---Registers : 252 Bit Registers := 16 240 Bit Registers := 32 228 Bit Registers := 64 227 Bit Registers := 49 224 Bit Registers := 49 209 Bit Registers := 1 192 Bit Registers := 1 128 Bit Registers := 7 120 Bit Registers := 1 112 Bit Registers := 8 80 Bit Registers := 1 64 Bit Registers := 2 49 Bit Registers := 4 48 Bit Registers := 83 45 Bit Registers := 2 42 Bit Registers := 1 38 Bit Registers := 1 37 Bit Registers := 64 36 Bit Registers := 388 35 Bit Registers := 384 34 Bit Registers := 1 33 Bit Registers := 1 32 Bit Registers := 1068 31 Bit Registers := 1 30 Bit Registers := 1 28 Bit Registers := 40 24 Bit Registers := 6 22 Bit Registers := 1 20 Bit Registers := 1 17 Bit Registers := 648 16 Bit Registers := 7230 15 Bit Registers := 660 13 Bit Registers := 18 12 Bit Registers := 125 11 Bit Registers := 18 10 Bit Registers := 34 9 Bit Registers := 141 8 Bit Registers := 132 7 Bit Registers := 222 6 Bit Registers := 246 5 Bit Registers := 648 4 Bit Registers := 583 3 Bit Registers := 206 2 Bit Registers := 716 1 Bit Registers := 7961 +---RAMs : 256K Bit (8192 X 32 bit) RAMs := 1 64K Bit (2048 X 32 bit) RAMs := 2 64K Bit (8192 X 8 bit) RAMs := 4 32K Bit (4096 X 8 bit) RAMs := 1 32K Bit (1024 X 32 bit) RAMs := 1 4K Bit (128 X 32 bit) RAMs := 2 +---Muxes : 20 Input 240 Bit Muxes := 16 2 Input 228 Bit Muxes := 64 2 Input 128 Bit Muxes := 8 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 112 Bit Muxes := 8 2 Input 80 Bit Muxes := 11 2 Input 49 Bit Muxes := 9 17 Input 49 Bit Muxes := 1 2 Input 48 Bit Muxes := 2 5 Input 48 Bit Muxes := 1 41 Input 41 Bit Muxes := 1 2 Input 41 Bit Muxes := 21 3 Input 38 Bit Muxes := 1 7 Input 36 Bit Muxes := 49 3 Input 34 Bit Muxes := 1 2 Input 33 Bit Muxes := 1 20 Input 32 Bit Muxes := 1 10 Input 32 Bit Muxes := 1 17 Input 32 Bit Muxes := 1 11 Input 32 Bit Muxes := 1 2 Input 32 Bit Muxes := 573 128 Input 32 Bit Muxes := 1 8 Input 32 Bit Muxes := 80 4 Input 32 Bit Muxes := 12 6 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 3 14 Input 32 Bit Muxes := 2 9 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 2 2 Input 30 Bit Muxes := 1 2 Input 24 Bit Muxes := 6 3 Input 22 Bit Muxes := 1 20 Input 20 Bit Muxes := 1 2 Input 20 Bit Muxes := 14 3 Input 16 Bit Muxes := 668 8 Input 16 Bit Muxes := 64 2 Input 16 Bit Muxes := 1890 4 Input 16 Bit Muxes := 170 14 Input 16 Bit Muxes := 3 11 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 18 Input 16 Bit Muxes := 4 2 Input 15 Bit Muxes := 128 2 Input 14 Bit Muxes := 128 4 Input 13 Bit Muxes := 661 2 Input 13 Bit Muxes := 151 8 Input 13 Bit Muxes := 1 3 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 132 2 Input 11 Bit Muxes := 136 6 Input 10 Bit Muxes := 60 2 Input 10 Bit Muxes := 3108 4 Input 10 Bit Muxes := 1 3 Input 9 Bit Muxes := 6 2 Input 9 Bit Muxes := 205 3 Input 8 Bit Muxes := 4 20 Input 8 Bit Muxes := 1 4 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 706 13 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 4 6 Input 8 Bit Muxes := 2 17 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 140 4 Input 7 Bit Muxes := 16 7 Input 7 Bit Muxes := 1 41 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 139 17 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 129 4 Input 6 Bit Muxes := 241 8 Input 6 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 6 Input 6 Bit Muxes := 2 28 Input 5 Bit Muxes := 1 30 Input 5 Bit Muxes := 1 21 Input 5 Bit Muxes := 2 2 Input 5 Bit Muxes := 388 7 Input 5 Bit Muxes := 384 5 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 421 20 Input 4 Bit Muxes := 3 10 Input 4 Bit Muxes := 97 4 Input 4 Bit Muxes := 131 17 Input 4 Bit Muxes := 3 21 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 225 5 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 14 Input 4 Bit Muxes := 2 9 Input 4 Bit Muxes := 2 2 Input 3 Bit Muxes := 218 3 Input 3 Bit Muxes := 6 20 Input 3 Bit Muxes := 2 10 Input 3 Bit Muxes := 1 7 Input 3 Bit Muxes := 52 11 Input 3 Bit Muxes := 1 5 Input 3 Bit Muxes := 11 4 Input 3 Bit Muxes := 35 6 Input 3 Bit Muxes := 2 8 Input 3 Bit Muxes := 4 4 Input 2 Bit Muxes := 727 2 Input 2 Bit Muxes := 1416 3 Input 2 Bit Muxes := 742 5 Input 2 Bit Muxes := 72 17 Input 2 Bit Muxes := 2 41 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 1897 3 Input 1 Bit Muxes := 847 20 Input 1 Bit Muxes := 43 10 Input 1 Bit Muxes := 8 7 Input 1 Bit Muxes := 637 4 Input 1 Bit Muxes := 116 17 Input 1 Bit Muxes := 25 11 Input 1 Bit Muxes := 10 9 Input 1 Bit Muxes := 6 12 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 9 8 Input 1 Bit Muxes := 9 6 Input 1 Bit Muxes := 8 5 Input 1 Bit Muxes := 3 16 Input 1 Bit Muxes := 9 41 Input 1 Bit Muxes := 23 14 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U2_XTOBs_eg/sync_5_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_5_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:68] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U2_XTOBs_eg/sync_4_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_4_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:69] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U2_XTOBs_eg/sync_3_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_3_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:70] INFO: [Synth 8-4471] merging register 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U2_XTOBs_eg/sync_2_tmp_reg' into 'U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/SIPO_unit.vhd:71] WARNING: [Synth 8-3917] design TOBs_rdout__GB0 has port tob_fsm_monitor[31] driven by constant 0 WARNING: [Synth 8-3917] design TOBs_rdout__GB0 has port tob_fsm_monitor[30] driven by constant 0 WARNING: [Synth 8-3917] design TOBs_rdout__GB0 has port tob_fsm_monitor[29] driven by constant 0 WARNING: [Synth 8-3917] design TOBs_rdout__GB0 has port tob_fsm_monitor[28] driven by constant 0 WARNING: [Synth 8-3917] design TOBs_rdout__GB0 has port tob_fsm_monitor[27] driven by constant 0 WARNING: [Synth 8-3917] design TOBs_rdout__GB0 has port ipbus_out_tob_dpram[ipb_err] driven by constant 0 WARNING: [Synth 8-7129] Port rdout_T_TOB_209b_in[201] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port rdout_T_TOB_209b_in[200] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port rdout_T_TOB_209b_in[199] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port rdout_T_TOB_209b_in[198] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port valid_T_TOB_in in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[7][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[6][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[5][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[4][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[3][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[2][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[1][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[0][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[0][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_eg_in[0][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[7][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][249] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][248] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][247] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][246] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[6][245] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[5][251] in module fsm_TOBs_to_muxPISO is either unconnected or has no load WARNING: [Synth 8-7129] Port XTOBs_tau_in[5][250] in module fsm_TOBs_to_muxPISO is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3971] The signal "TOBs_rdout__GB0/U12_TOB_SPY_mem/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM U12_TOB_SPY_mem/ram_reg to conserve power WARNING: [Synth 8-3936] Found unconnected internal register 'rec_err_flg_4b_i_reg' and it is trimmed from '4' to '3' bits. [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Readout/src/fsm_RAW_to_muxPISO.vhd:322] WARNING: [Synth 8-3917] design RAW_data_rdout__GB0 has port ipbus_out_raw_dpram[ipb_err] driven by constant 0 INFO: [Synth 8-3971] The signal "RAW_data_rdout__GB0/U12_RAW_SPY_mem/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM U12_RAW_SPY_mem/ram_reg to conserve power WARNING: [Synth 8-7129] Port reset in module crc_checker__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module crc_checker__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module crc_checker__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_0[6] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_0[5] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_1[6] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_1[5] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_2[6] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_2[5] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_3[6] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_3[5] in module quad_bc_alignment__3 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_0[6] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_0[5] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_1[6] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_1[5] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_2[6] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_2[5] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_3[6] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_3[5] in module quad_bc_alignment__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_0[6] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_0[5] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_1[6] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_1[5] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_2[6] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_2[5] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_3[6] in module quad_bc_alignment__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port bcn_3[5] in module quad_bc_alignment__1 is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[2].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[1].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[0].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[3].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[0].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[2].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer2_for[3].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer2_for[2].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer2_for[1].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer2_for[0].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[0].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[0].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[2].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[9].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[2].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[2].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[2].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[2].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[0].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[2].layer2_for[0].EnergyConverter2 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[3].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[1].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[9].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[3].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[8].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[1].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[0].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[3].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[2].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[1].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[2].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[1].row_for[1].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[0].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[8].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[0].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[7].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[0].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[0].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[1].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[1].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[1].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[1].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[2].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[2].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[7].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[2].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[6].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[2].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[3].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[3].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[3].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[3].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[4].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[4].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[4].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[6].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[4].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[5].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[5].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[5].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[5].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[5].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[6].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[6].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[6].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[6].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[5].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[7].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[4].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[7].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[7].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[7].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[8].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[8].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[8].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[8].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[9].layer1_for[0].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[4].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[9].layer1_for[1].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[3].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[9].layer1_for[2].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[2].row_for[9].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[0].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[0].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[1].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[1].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[2].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[2].layer3_for[0].EnergyConverter3 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[3].row_for[3].layer0_for[0].EnergyConverter0 /\ENCODING_IF.OutData_reg[14] ) INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[2].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer2_for[2].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[1].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer2_for[1].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[3].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[1].layer2_for[3].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[0].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[0].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[2].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[2].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer2_for[3].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer2_for[3].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer2_for[2].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer2_for[2].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer2_for[1].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer2_for[1].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[0].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[0].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[0].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[0].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[2].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[2].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[9].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[9].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[2].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[2].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[2].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[2].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[2].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[2].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[2].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[2].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[0].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[0].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[2].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[4].row_for[2].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[3].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[3].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[1].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[1].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[9].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[9].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[3].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[3].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[8].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[8].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[1].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[1].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[0].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[0].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[3].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[3].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[2].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[2].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[1].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[1].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[2].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[2].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[1].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[1].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[0].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[0].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[8].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[8].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[0].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[0].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[7].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[7].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[0].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[0].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[0].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[0].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[1].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[1].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[1].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[1].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[1].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[1].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[2].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[2].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[2].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[2].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[7].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[7].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[2].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[2].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[6].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[6].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[2].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[2].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[3].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[3].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[3].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[3].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[3].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[3].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[3].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[3].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[4].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[4].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[4].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[4].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[4].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[4].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[6].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[6].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[4].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[4].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[5].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[5].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[5].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[5].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[5].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[5].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[5].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[5].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[5].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[5].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[6].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[6].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[6].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[6].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[6].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[6].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[6].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[6].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[5].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[5].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[7].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[7].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[4].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[4].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[7].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[7].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[7].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[7].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[7].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[7].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[8].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[8].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[8].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[8].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[8].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[8].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[8].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[8].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[9].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[9].layer1_for[0].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[4].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[4].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[9].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[9].layer1_for[1].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[3].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[3].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[9].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[9].layer1_for[2].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[2].row_for[9].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[2].row_for[9].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[0].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[0].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[0].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[0].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[1].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[1].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[1].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[1].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[2].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[2].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[2].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[2].layer3_for[0].EnergyConverter3/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[3].row_for[3].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[14]' (FD) to 'column_for[3].row_for[3].layer0_for[0].EnergyConverter0/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[2].EnergyConverter2 /\ENCODING_IF.OutData_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[1].EnergyConverter2 /\ENCODING_IF.OutData_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer2_for[0].EnergyConverter2 /\ENCODING_IF.OutData_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\column_for[4].row_for[1].layer1_for[3].EnergyConverter1 /\ENCODING_IF.OutData_reg[13] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[2].EnergyConverter2/ENCODING_IF.OUT_Data_reg[13]' (FD) to 'column_for[4].row_for[1].layer2_for[2].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[1].EnergyConverter2/ENCODING_IF.OUT_Data_reg[13]' (FD) to 'column_for[4].row_for[1].layer2_for[1].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[13]' (FD) to 'column_for[4].row_for[1].layer2_for[0].EnergyConverter2/ENCODING_IF.OUT_Data_reg[15]' INFO: [Synth 8-3886] merging instance 'column_for[4].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[13]' (FD) to 'column_for[4].row_for[1].layer1_for[3].EnergyConverter1/ENCODING_IF.OUT_Data_reg[15]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3917] design AdderTree__sblockDup__1 has port OUT_Overflows[3] driven by constant 0 INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (MGT_GT0/playback_ram/sm_playback/FSM_sequential_current_state_reg[0]) is unused and will be removed from module mgt_quad_slaves__parameterized0. WARNING: [Synth 8-3332] Sequential element (MGT_GT0/playback_ram/sm_playback/FSM_sequential_current_state_reg[0]) is unused and will be removed from module mgt_quad_slaves__parameterized0__xdcDup__3. WARNING: [Synth 8-3332] Sequential element (MGT_GT0/playback_ram/sm_playback/FSM_sequential_current_state_reg[0]) is unused and will be removed from module mgt_quad_slaves__parameterized0__xdcDup__2. WARNING: [Synth 8-3332] Sequential element (MGT_GT0/playback_ram/sm_playback/FSM_sequential_current_state_reg[0]) is unused and will be removed from module mgt_quad_slaves__parameterized0__xdcDup__1. INFO: [Synth 8-5544] ROM "buf_to_load_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power WARNING: [Synth 8-6014] Unused sequential element spi_dpram_out/ram_reg was removed. INFO: [Synth 8-3971] The signal "slaves/spi_flash/spi_dpram_in/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power WARNING: [Synth 8-3332] Sequential element (synch/FSM_onehot_sequencer_reg[3]) is unused and will be removed from module ipbus_spi32. WARNING: [Synth 8-3917] design top_efex_processor__GCB1 has port flash_led driven by constant 0 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:10:49 ; elapsed = 00:11:06 . Memory (MB): peak = 4486.355 ; gain = 1712.496 ; free physical = 22131 ; free virtual = 59926 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |TOBs_rdout__GB0 | U12_TOB_SPY_mem/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |RAW_data_rdout__GB0 | U12_RAW_SPY_mem/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slaves/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slaves/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |slaves | RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | +------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:11:10 ; elapsed = 00:11:27 . Memory (MB): peak = 4486.355 ; gain = 1712.496 ; free physical = 21148 ; free virtual = 59187 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:12:12 ; elapsed = 00:12:31 . Memory (MB): peak = 4486.355 ; gain = 1712.496 ; free physical = 20537 ; free virtual = 58601 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |TOBs_rdout__GB0 | U12_TOB_SPY_mem/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |RAW_data_rdout__GB0 | U12_RAW_SPY_mem/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |U_1/\U_2/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |slaves/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |slaves/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |slaves | RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | +------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-5816] Retiming module `egInputMultiplexer__sblockDup__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `egInputMultiplexer__sblockDup__1' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `MultiAdder__sblockDup__1` Numbers of forward move = 0, and backward move = 35 Retimed registers names: MultiAdder__sblockDup__1:/stage_gen[0].adder_gen[0].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[0].adder_gen[0].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[0].adder_gen[0].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[1].adder_gen[0].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[1].adder_gen[0].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[1].adder_gen[0].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[1].adder_gen[1].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[1].adder_gen[1].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[1].adder_gen[1].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[0].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[0].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[0].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[1].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[1].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[1].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[2].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[2].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[2].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[3].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[3].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[2].adder_gen[3].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[0].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[0].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[0].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[1].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[1].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[1].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[2].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[2].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[2].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[3].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[3].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[3].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[4].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[4].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[4].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[5].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[5].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[5].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[6].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[6].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[6].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[7].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[7].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[3].adder_gen[7].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[0].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[0].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[0].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[10].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[10].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[11].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[11].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[12].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[12].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[13].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[13].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[14].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[14].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[14].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[15].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[15].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[15].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[1].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[1].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[2].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[2].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[3].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[3].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[4].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[4].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[5].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[5].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[6].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[6].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[7].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[7].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[7].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[8].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[8].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[9].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[4].adder_gen[9].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[28].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[28].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[28].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[29].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[29].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[29].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[30].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[30].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[30].ADD/OutCarry_reg_bret__1 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[31].ADD/OutCarry_reg_bret MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[31].ADD/OutCarry_reg_bret__0 MultiAdder__sblockDup__1:/stage_gen[5].adder_gen[31].ADD/OutCarry_reg_bret__1 INFO: [Synth 8-5816] Retiming module `MultiAdder__sblockDup__1' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__1__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EGi_1/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__1__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AdderTree__sblockDup__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `AdderTree__sblockDup__1' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__1__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDTi_2/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__1__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__2__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EGi_3/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__2__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__2__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDTi_4/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__2__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__3__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EGi_5/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__3__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__3__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDTi_6/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__3__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__4__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EGi_7/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__4__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__4__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDTi_8/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__4__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__5__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EGi_9/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__5__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__5__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDTi_10/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__5__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__6__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EGi_11/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__6__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__6__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDTi_12/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__6__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/i_2402 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__7__GC0` Numbers of forward move = 3, and backward move = 0 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EGi_13/MULTI_ADDER_WS_ENV/DelayedOut_reg[0][15]_fret__0 INFO: [Synth 8-5816] Retiming module `AlgoCore_eg__xdcDup__7__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Synth 8-5816] Retiming module `top_efex_processor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_processor' done INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__7__GC0` Numbers of forward move = 0, and backward move = 2 Retimed registers names: DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[0]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__0 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__1 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__2 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__3 DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDTi_14/CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret__4 INFO: [Synth 8-5816] Retiming module `AlgoCore_tau_bdt__xdcDup__7__GC0' done INFO: [Synth 8-5816] Retiming module `TopAlgoModule` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `TopAlgoModule' done INFO: [Common 17-14] Message 'Synth 8-5816' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2276 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2277 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2278 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2279 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2280 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2281 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2282 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2283 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2284 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2285 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2286 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2287 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2276 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2277 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2278 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2279 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2280 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2281 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2282 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2283 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2284 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2285 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2286 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2287 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2391 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2392 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2393 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2394 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2395 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2396 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2397 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2398 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2399 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2400 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2401 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][15] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2402 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][14] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2402 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2391 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2392 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2393 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2394 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2395 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2396 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2397 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2398 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2399 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2400 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2401 RETIMING: forward move fails for register DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][13] along load instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EGi_15/i_2402 INFO: [Synth 8-7052] The timing for the instance U0_TOBs_readouti_5/READOUT_IF.Readout_block/U0_TOBs_readout/U12_TOB_SPY_mem/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U0_TOBs_readouti_5/READOUT_IF.Readout_block/U0_TOBs_readout/U12_TOB_SPY_mem/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U1_RAW_readouti_6/READOUT_IF.Readout_block/U1_RAW_readout/U12_RAW_SPY_mem/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U1_RAW_readouti_6/READOUT_IF.Readout_block/U1_RAW_readout/U12_RAW_SPY_mem/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/slaves/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_0/slaves/RAM/reg_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:17:18 ; elapsed = 00:17:46 . Memory (MB): peak = 4494.359 ; gain = 1720.500 ; free physical = 23934 ; free virtual = 62054 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance slaves/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance slaves/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance READOUT_IF.Readout_block/U0_TOBs_readout/U12_TOB_SPY_mem/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance READOUT_IF.Readout_block/U0_TOBs_readout/U12_TOB_SPY_mem/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance READOUT_IF.Readout_block/U1_RAW_readout/U12_RAW_SPY_mem/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance READOUT_IF.Readout_block/U1_RAW_readout/U12_RAW_SPY_mem/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_1/U_2/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance slaves/RAM/reg_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[48] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[47] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[46] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[45] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[44] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[43] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[42] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[41] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[40] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[39] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[38] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[37] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[36] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[35] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[34] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[33] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[32] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[31] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[30] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[29] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[28] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[27] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[26] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[25] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[24] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[23] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[22] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[21] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[20] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[19] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[18] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[17] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[16] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[15] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[12] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[11] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[10] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[9] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[8] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[7] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[6] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[5] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[4] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[3] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin READOUT_IF.Readout_block/U1_RAW_readout/delayed_crc_error_i_inferred:in0[0] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1996[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1996[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1997[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1997[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1998[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1998[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1999[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I1999[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2000[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2000[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2001[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2001[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2002[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2002[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2003[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2003[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2004[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2004[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2005[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2005[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2007[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2007[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2008[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2008[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2009[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2009[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2010[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2010[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2011[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2011[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2012[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2012[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2013[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2013[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2014[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2014[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2015[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2015[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2016[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2016[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2018[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2018[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2019[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2019[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2020[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2020[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2021[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2021[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2022[14] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2022[13] to constant 0 WARNING: [Synth 8-3295] tying undriven pin i_0:I2023[14] to constant 0 INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:18:37 ; elapsed = 00:19:08 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 22769 ; free virtual = 61106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:18:38 ; elapsed = 00:19:10 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 22767 ; free virtual = 61104 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:19:58 ; elapsed = 00:20:31 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 23453 ; free virtual = 61827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:20:02 ; elapsed = 00:20:35 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 23454 ; free virtual = 61828 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:20:19 ; elapsed = 00:20:53 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 23251 ; free virtual = 61625 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:20:23 ; elapsed = 00:20:56 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 23252 ; free virtual = 61627 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +---------------------------------+---------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +---------------------------------+---------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__1__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AdderTree | EM_ET/stage_gen[1].adder_gen[1].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AdderTree | DelayWC_l2_d1051_l2_d1051_d/DelayedWord_reg[0][16] | 3 | 1 | NO | NO | YES | 1 | 0 | |AdderTree | DelayWC_l2_d0375_l2_d0375_d/DelayedWord_reg[0][16] | 4 | 16 | NO | YES | YES | 16 | 0 | |AdderTree | DelayWC_l2_d0375_l2_d0375_d/DelayedWord_reg[0][0] | 3 | 1 | NO | NO | YES | 1 | 0 | |AdderTree | DelayWC_l2_d0625_l2_d0625_d/DelayedWord_reg[0][16] | 4 | 17 | NO | YES | YES | 17 | 0 | |AdderTree | DelayWC_l0_d0000_l0_d0000_d/DelayedWord_reg[0][15] | 4 | 16 | NO | NO | YES | 16 | 0 | |AdderTree | DelayWC_l2_d0125_l2_d0125_d/DelayedWord_reg[0][16] | 4 | 17 | NO | YES | YES | 17 | 0 | |AdderTree | DelayWC_l2_d0990_l2_d0990_d/DelayedWord_reg[0][16] | 3 | 1 | NO | NO | YES | 1 | 0 | |AdderTree | DelayWC_l1_d1493_l1_d1493_d/DelayedWord_reg[0][16] | 3 | 1 | NO | NO | YES | 1 | 0 | |AdderTree | DelayWC_l1_d1315_l1_d1315_d/DelayedWord_reg[0][16] | 3 | 1 | NO | NO | YES | 1 | 0 | |AdderTree | DelayWC_l1_d1164_l1_d1164_d/DelayedWord_reg[0][16] | 3 | 1 | NO | NO | YES | 1 | 0 | |AdderTree | DelayWC_l1_d1690_l1_d1690_d/DelayedWord_reg[0][16] | 3 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__1__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__2__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__2__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__3__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__3__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__4__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__4__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__5__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__5__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__6__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__6__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__xdcDup__7__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__xdcDup__7__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_RETA_CORE/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_RETA_CORE/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_WS_ENV/DelayedOverflow_reg[0] | 5 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[1][15] | 4 | 5 | NO | YES | YES | 5 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_WS_ENV/DelayedOut_reg[0][10] | 5 | 11 | NO | YES | YES | 11 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_HAD_CORE/stage_gen[1].adder_gen[0].ADD/OutWord_reg[15] | 4 | 17 | NO | YES | YES | 17 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_HAD_ENV/DelayedOverflow_reg[0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[1][15] | 5 | 3 | NO | YES | YES | 3 | 0 | |AlgoCore_eg__GC0 | MULTI_ADDER_HAD_ENV/DelayedOut_reg[0][12] | 6 | 13 | NO | YES | YES | 13 | 0 | |AlgoCore_eg__GC0 | Energy_threshold_delay/DelayedWord_reg[0][15] | 4 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__GC0 | Condition_threshold_delay/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_eg__GC0 | DEAD_MATERIAL_DELAY/DelayedSignal_reg[0][27] | 5 | 28 | NO | YES | YES | 28 | 0 | |AlgoCore_eg__GC0 | SEED_DELAY/DelayedSignal_reg[0][4] | 10 | 4 | NO | NO | YES | 4 | 0 | |AlgoCore_eg__GC0 | SEED_DELAY/DelayedSignal_reg[0][1] | 11 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_eg__GC0 | OVERFLOW_DELAY/DelayedSignal_reg[0][2] | 5 | 3 | NO | NO | YES | 3 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d/DelayedWord_reg[0][15] | 5 | 16 | NO | YES | YES | 16 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d/DelayedWord_reg[0][15] | 3 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d/DelayedWord_reg[0][0] | 5 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergy_Final_TOBEnergy_d/DelayedWord_reg[0][15] | 5 | 16 | NO | NO | YES | 16 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_Final_IsMax_Final_IsMax_d/DelayedWord_reg[0][0] | 6 | 1 | NO | NO | YES | 1 | 0 | |AlgoCore_tau_bdt__GC0 | CONDITIONS_FRAC/OUT_FracCondition_reg[1]_bret | 4 | 1 | NO | YES | YES | 1 | 0 | |AlgoCore_tau_bdt__GC0 | DELAY_TREE/DelayWC_Final_FracCondition_Final_FracCondition_d/DelayedWord_reg[0][1] | 3 | 2 | NO | NO | YES | 2 | 0 | |XTOBs_sorting | GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |data_alignment__GCB1 | synch_gen[20].u0/synch_1/temp12_reg[34] | 7 | 2 | NO | NO | NO | 2 | 0 | |AlgoRateMonitor__GB1 | sync_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U2_XTOBs_eg/sync_2_tmp_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U1_TOBs_eg/wr_6_tmp_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U1_TOBs_eg/U3_TOB_BCN_Delay/DelayedSignal_reg[0][6] | 14 | 3 | NO | NO | YES | 3 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U1_TOBs_eg/U3_TOB_BCN_Delay/DelayedSignal_reg[0][3] | 6 | 4 | NO | NO | YES | 4 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U1_TOBs_eg/sync_1_tmp_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/U2_XTOB_BCN_Delay/DelayedSignal_reg[0][0] | 16 | 7 | NO | NO | YES | 7 | 0 | |top_efex_processor | READOUT_IF.Readout_block/U1_RAW_readout/en_error_valid_3dly_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | READOUT_IF.Readout_block/TOB_out_is_char_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[44].u0/synch_1/temp12_reg[34] | 7 | 102 | NO | NO | NO | 102 | 0 | |top_efex_processor | DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/Load_delay200_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/Load_delay280_reg[4] | 5 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | DATA_PATH_IF.data_path_Module/Sorting_Module/BCN_Delay/DelayedSignal_reg[0][11] | 33 | 12 | NO | NO | YES | 0 | 12 | |top_efex_processor | DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/OUT_Start_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | GLOBAL_MERGE.Merging_Module/inputRAM_1/dOutput_reg[2][31] | 3 | 32 | NO | NO | YES | 32 | 0 | |top_efex_processor | GLOBAL_MERGE.Merging_Module/inputRAM_2/dOutput_reg[2][31] | 3 | 32 | NO | NO | YES | 32 | 0 | |top_efex_processor | GLOBAL_MERGE.Merging_Module/inputRAM_3/dOutput_reg[2][31] | 3 | 32 | NO | NO | YES | 32 | 0 | |top_efex_processor | GLOBAL_MERGE.Merging_Module/inputRAM_4/dOutput_reg[2][31] | 3 | 32 | NO | NO | YES | 32 | 0 | |top_efex_processor | GLOBAL_MERGE.Merging_Module/outputRAM/dOutput_reg[2][31] | 3 | 32 | NO | NO | YES | 32 | 0 | |top_efex_processor | GLOBAL_MERGE.TOB_BCN_sync_ii_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | GLOBAL_MERGE.tx_phase_adjust/BCN_reg_reg[0] | 8 | 4 | NO | NO | YES | 4 | 0 | |top_efex_processor | GLOBAL_MERGE.Merging_Module/outputRAM/dSync_reg[4] | 3 | 1 | NO | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/IPADDR/rarp_reply._MAC_IP_addr_rx_rarp.pkt_mask_reg[41] | 32 | 1 | YES | NO | YES | 0 | 1 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |top_efex_processor | U_1/U_2/udp_if/resend/resend_pkt_id_block.pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[33] | 6 | 2 | YES | NO | YES | 2 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/rarp_reply._rarp.pkt_mask_reg[21] | 6 | 3 | YES | NO | YES | 3 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[18] | 5 | 1 | YES | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[11] | 8 | 1 | YES | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[37] | 23 | 1 | YES | NO | YES | 0 | 1 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[13] | 12 | 1 | YES | NO | YES | 1 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[71] | 5 | 4 | YES | NO | YES | 4 | 0 | |top_efex_processor | U_1/U_2/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[59] | 4 | 1 | YES | NO | YES | 1 | 0 | +---------------------------------+---------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Retiming Report: +--------------------+-----+ |Retiming summary: | | +--------------------+-----+ |Forward Retiming | 24 | |Backward Retiming | 111 | |New registers added | 453 | |Registers deleted | 151 | +--------------------+-----+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+-------------------------+----------+ | |BlackBox name |Instances | +------+-------------------------+----------+ |1 |io_delay | 6| |2 |io_delay2 | 3| |3 |FastMult | 24| |4 |Mult | 72| |5 |AlgoParameterRAM | 1| |6 |SortingOutputRAM | 5| |7 |min_latency_1_quad_rx_tx | 16| |8 |mgt_playback_ram | 80| |9 |FIFO_47b_512 | 2| |10 |FIFO_33b_8192 | 2| |11 |DPR_209b_512 | 1| |12 |FIFO_209b_512 | 1| |13 |DPR_252b_512 | 16| |14 |FIFO_252b_512 | 16| |15 |DPR_36b_1024 | 49| |16 |FIFO_36b_512 | 49| |17 |FIFO_54b_512 | 1| |18 |ClockWizard | 1| |19 |clk_wiz_1 | 1| +------+-------------------------+----------+ Report Cell Usage: +------+-----------------------------------+-------+ | |Cell |Count | +------+-----------------------------------+-------+ |1 |AlgoParameterRAM_bbox | 1| |2 |ClockWizard_bbox | 1| |3 |DPR_209b_512_bbox | 1| |4 |DPR_252b_512_bbox | 1| |5 |DPR_252b_512_bbox_128_ | 1| |6 |DPR_252b_512_bbox | 1| |7 |DPR_252b_512_bbox_130_ | 1| |8 |DPR_252b_512_bbox | 1| |9 |DPR_252b_512_bbox_132_ | 1| |10 |DPR_252b_512_bbox | 1| |11 |DPR_252b_512_bbox_134_ | 1| |12 |DPR_252b_512_bbox | 1| |13 |DPR_252b_512_bbox_136_ | 1| |14 |DPR_252b_512_bbox | 1| |15 |DPR_252b_512_bbox_138_ | 1| |16 |DPR_252b_512_bbox | 1| |17 |DPR_252b_512_bbox_140_ | 1| |18 |DPR_252b_512_bbox | 1| |19 |DPR_252b_512_bbox_142_ | 1| |20 |DPR_36b_1024_bbox | 49| |69 |FIFO_209b_512_bbox | 1| |70 |FIFO_252b_512_bbox | 1| |71 |FIFO_252b_512_bbox_129_ | 1| |72 |FIFO_252b_512_bbox | 1| |73 |FIFO_252b_512_bbox_131_ | 1| |74 |FIFO_252b_512_bbox | 1| |75 |FIFO_252b_512_bbox_133_ | 1| |76 |FIFO_252b_512_bbox | 1| |77 |FIFO_252b_512_bbox_135_ | 1| |78 |FIFO_252b_512_bbox | 1| |79 |FIFO_252b_512_bbox_137_ | 1| |80 |FIFO_252b_512_bbox | 1| |81 |FIFO_252b_512_bbox_139_ | 1| |82 |FIFO_252b_512_bbox | 1| |83 |FIFO_252b_512_bbox_141_ | 1| |84 |FIFO_252b_512_bbox | 1| |85 |FIFO_252b_512_bbox_143_ | 1| |86 |FIFO_33b_8192_bbox | 2| |88 |FIFO_36b_512_bbox | 49| |137 |FIFO_47b_512_bbox | 2| |139 |FIFO_54b_512_bbox | 1| |140 |FastMult_bbox | 1| |141 |FastMult_bbox_249_ | 7| |148 |FastMult_bbox | 1| |149 |FastMult_bbox_250_ | 7| |156 |FastMult_bbox | 1| |157 |FastMult_bbox_251_ | 7| |164 |Mult_bbox | 1| |165 |Mult_bbox_246_ | 23| |188 |Mult_bbox | 1| |189 |Mult_bbox_247_ | 23| |212 |Mult_bbox | 1| |213 |Mult_bbox_248_ | 23| |236 |SortingOutputRAM_bbox | 1| |237 |SortingOutputRAM_bbox_255_ | 4| |241 |clk_wiz_1_bbox | 1| |242 |io_delay2_bbox | 3| |245 |io_delay_bbox | 6| |251 |mgt_playback_ram_bbox | 1| |252 |mgt_playback_ram_bbox_254_ | 79| |331 |min_latency_1_quad_rx_tx_bbox | 1| |332 |min_latency_1_quad_rx_tx_bbox_253_ | 15| |347 |BUFG | 7| |348 |BUFH | 64| |349 |CARRY4 | 19035| |350 |GTHE2_COMMON | 16| |351 |IBUFDS_GTE2 | 16| |352 |ICAPE2 | 1| |353 |LUT1 | 927| |354 |LUT2 | 53817| |355 |LUT3 | 32973| |356 |LUT4 | 26568| |357 |LUT5 | 25572| |358 |LUT6 | 56096| |359 |MMCME2_BASE | 1| |360 |MUXF7 | 5823| |361 |MUXF8 | 973| |362 |RAMB36E1 | 24| |368 |SRL16 | 1| |369 |SRL16E | 4536| |370 |SRLC32E | 11415| |371 |STARTUPE2 | 1| |372 |XADC | 1| |373 |FDCE | 496| |374 |FDPE | 1| |375 |FDRE | 246798| |376 |FDSE | 1318| |377 |IBUF | 218| |378 |IBUFDS | 4| |379 |IBUFGDS | 1| |380 |OBUF | 171| |381 |OBUFDS | 66| +------+-----------------------------------+-------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:20:23 ; elapsed = 00:20:57 . Memory (MB): peak = 4604.195 ; gain = 1830.336 ; free physical = 23254 ; free virtual = 61629 --------------------------------------------------------------------------------- Report Applied BLOCK_SYNTH Properties: +--------+--------------------------------------------------------------+-------------------------------+ |Inst ID |Instance Name |Applied BLOCK_SYNTH Properties | +--------+--------------------------------------------------------------+-------------------------------+ |1 |DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE |"MUXF_MAPPING 1" | +--------+--------------------------------------------------------------+-------------------------------+ Report BLOCK_SYNTH Property Instance Level Cell Usage: +------+-------+-----------+ | |Cell |Inst ID: 1 | +------+-------+-----------+ |1 |LUT1 | 80| |2 |LUT3 | 5422| |3 |MUXF7 | 640| |4 |LUT6 | 18704| |5 |LUT5 | 5288| |6 |LUT4 | 11756| |7 |LUT2 | 47802| |8 |CARRY4 | 15176| |9 |FDSE | 939| |10 |SRL16E | 2240| |11 |FDRE | 102192| |12 |BUF | 2304| +------+-------+-----------+ NOTE: Inst IDs in this report represent instances and are taken from the Report Applied BLOCK_SYNTH Properties. Synthesis finished with 0 errors, 0 critical warnings and 1565 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:19:22 ; elapsed = 00:19:51 . Memory (MB): peak = 4608.105 ; gain = 625.785 ; free physical = 25206 ; free virtual = 63580 Synthesis Optimization Complete : Time (s): cpu = 00:20:29 ; elapsed = 00:20:59 . Memory (MB): peak = 4608.105 ; gain = 1834.246 ; free physical = 25236 ; free virtual = 63568 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4850.750 ; gain = 0.000 ; free physical = 30628 ; free virtual = 68996 INFO: [Netlist 29-17] Analyzing 25930 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5282.266 ; gain = 0.000 ; free physical = 29676 ; free virtual = 68044 INFO: [Project 1-111] Unisim Transformation Summary: A total of 69 instances were transformed. IBUFGDS => IBUFDS: 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 66 instances SRL16 => SRL16E: 1 instance INFO: [Common 17-83] Releasing license: Synthesis 1356 Infos, 478 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:22:30 ; elapsed = 00:23:03 . Memory (MB): peak = 5282.266 ; gain = 2508.406 ; free physical = 30815 ; free virtual = 69183 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Common 17-1381] The checkpoint '/home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/synth_1/top_efex_processor.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:18 ; elapsed = 00:01:22 . Memory (MB): peak = 5282.266 ; gain = 0.000 ; free physical = 29698 ; free virtual = 68145 INFO: [runtcl-4] Executing : report_utilization -file top_efex_processor_utilization_synth.rpt -pb top_efex_processor_utilization_synth.pb source /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-synthesis.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.2... INFO: [Hog:GetRepoVersions-0] Hog submodule /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.0-E030ECB INFO: [Hog:Msg-0] Creating /home/gitlab-runner/builds/t3_oV-mw4/2/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.2-v1.7.0-E030ECB... INFO: [Hog:Msg-0] Copying synthesised IP AlgoInputRAM to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP AlgoOutputRAM to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP AlgoParameterRAM to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP ClockWizard to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP DPR_209b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP DPR_252b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP DPR_36b_1024 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FIFO_209b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FIFO_252b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FIFO_33b_8192 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FIFO_36b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FIFO_47b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FIFO_54b_512 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP FastMult to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP Mult to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP SortingInputRAM to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP SortingOutputRAM to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP clk_wiz_1 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP io_delay to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP io_delay2 to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP mgt_playback_ram to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] Copying synthesised IP min_latency_1_quad_rx_tx to /eos/user/e/efex/www/firmware/eFEX/ip... eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by eos) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libzmq.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /lib64/libEosCommon.so.5) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /lib64/libjsoncpp.so.25) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdUtils.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libprotobuf.so.23) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_time_zone.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_log_internal_message.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_cord.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_status.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.11' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by /opt/eos/xrootd/lib64/libXrdCl.so.3) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_crc_cord_state.so.2301.0.0) eos: /opt/Xilinx/Vivado/2020.2/lib/lnx64.o/Default/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by /opt/eos/grpc/lib64/libabsl_str_format_internal.so.2301.0.0) CRITICAL WARNING: [Hog:HandleIP-0] Could not run ls for for EOS path: /eos/user/e/efex/www/firmware/eFEX/ip (error: child process exited abnormally). Either the drectory does not exist or there are (temporary) problem with EOS. INFO: [Hog:Msg-0] All done. INFO: [Common 17-206] Exiting Vivado at Sun Mar 9 01:12:39 2025...