<!-- MGT register address table -->
<!-- Defines MGT_channel container  -->
<!-- version: 1.7.0     sha: 6995bf6 -->

<node fwinfo="endpoint;width=8">
  <node id="status" permission="r"   address="0x0" description="Quad Channel Status Register" fwinfo="endpoint;width=0">
    <node id="rx_resetdone" 	mask="0x1" description="Quad Channel Reset done" />
    <node id="rx_fsm_reset_done"	mask="0x2" description="Quad Channel " />
    <node id="rx_byteisaligned"	mask="0x4" description="Quad Channel" />
    <node id="tx_resetdone"	mask="0x10" description="Quad Channel " />
    <node id="tx_fsm_reset_done"	mask="0x20" description="Quad Channel " />
    <node id="tx_bufstatus"		mask="0xC0" description="Quad Channel " />
    <node id="tx_pwr"		mask="0x100" description="Channel Tx power" />
    <node id="rx_pwr"		mask="0x200" description="Channel Rx power" />
  </node>
  <node id="error_counter"  	permission="r"  address="0x1" description="Quad Channel  Data not in Table Error Counter" fwinfo="endpoint;width=0"/>
  <node id="disperr_counter" 	permission="r"  address="0x2" description="Quad Channel  Data Disparity Error Counter" fwinfo="endpoint;width=0"/>
  <node id="byterealign_counter" 	permission="r"  address="0x3" description="Quad Channel  Byte Realignment Counter" fwinfo="endpoint;width=0"/>
  <node id="delay_counter" 	permission="r"  address="0x4" description="Quad Channel  Stage 1 State Machine Delay Counter" fwinfo="endpoint;width=0"/>
  <node id="bc_counter" 		permission="r"  address="0x5" description="Quad Channel  BC Time Counter" fwinfo="endpoint;width=0"/>
  <node id="bc_mux_counter"   permission="r"  address="0x6" description="Quad Channel  BC Time after mux counter" fwinfo="endpoint;width=0"/>
  <node id="crc_error_counter"      permission="r"  address="0x7" description="Quad Channel  tx phase error counter" fwinfo="endpoint;width=0"/>
  <node id="playback_ram"     address="0x80" mode="block" size="0x80" description="MGT spy and playback RAM" fwinfo="endpoint;width=7"/>
</node >
