Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Sun Mar 9 00:41:33 2025 | Host : efex-heavyduty-vm1.cern.ch running 64-bit unknown | Command : report_utilization -hierarchical -hierarchical_percentages -file /home/gitlab-runner/builds/t3_oV-mw4/1/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.4-v1.7.0-5C0A46A/reports/hierarchical_utilization.txt | Design : top_efex_processor | Device : 7vx550tffg1927-2 | Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ | top_efex_processor | (top) | 186278(53.78%) | 172335(49.75%) | 0(0.00%) | 13943(8.00%) | 261993(37.82%) | 706(59.83%) | 83(3.52%) | 96(3.33%) | | (top_efex_processor) | (top) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_PATH_IF.data_path_Module | data_path_block | 118993(34.35%) | 105127(30.35%) | 0(0.00%) | 13866(7.96%) | 180609(26.07%) | 8(0.68%) | 0(0.00%) | 96(3.33%) | | (DATA_PATH_IF.data_path_Module) | data_path_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Sorting_Module | IPBusTopSortingModule | 3241(0.94%) | 3228(0.93%) | 0(0.00%) | 13(0.01%) | 6818(0.98%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Sorting_Module) | IPBusTopSortingModule | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_Delay | GeneralDelay__parameterized5 | 34(0.01%) | 22(0.01%) | 0(0.00%) | 12(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_SORTING_REGISTERS | ipbus_ctrlreg_v__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_eg | TopSortingModule | 1578(0.46%) | 1577(0.46%) | 0(0.00%) | 1(0.01%) | 3341(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_eg) | TopSortingModule | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 290(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5897 | 221(0.06%) | 220(0.06%) | 0(0.00%) | 1(0.01%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5897 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5916 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5917 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5898 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5898 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5914 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5915 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5899 | 217(0.06%) | 217(0.06%) | 0(0.00%) | 0(0.00%) | 437(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5899 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5912 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5913 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0_5900 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0_5900 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5910 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5911 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5901 | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5901 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5908 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5909 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5902 | 224(0.06%) | 224(0.06%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5902 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5906 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5907 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5903 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 438(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5903 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5904 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5905 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_tau | TopSortingModule_5878 | 1587(0.46%) | 1587(0.46%) | 0(0.00%) | 0(0.00%) | 3335(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_tau) | TopSortingModule_5878 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 288(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5895 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5896 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5879 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5879 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5893 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5894 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5880 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5880 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5891 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5892 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5889 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5890 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5881 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5881 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5887 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5888 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5882 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5882 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5885 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5886 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5883 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5883 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5884 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | algorithm_block | IPBusTopAlgoModule | 96050(27.73%) | 94695(27.34%) | 0(0.00%) | 1355(0.78%) | 136267(19.67%) | 8(0.68%) | 0(0.00%) | 96(3.33%) | | (algorithm_block) | IPBusTopAlgoModule | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_STAGE | AlgoInputStage | 5600(1.62%) | 5600(1.62%) | 0(0.00%) | 0(0.00%) | 19479(2.81%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (INPUT_STAGE) | AlgoInputStage | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].EnergyConverterH | EnergyConverter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1594 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1595 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1596 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1597 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1598 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1599 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1600 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1601 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1602 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1603 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].EnergyConverterH | EnergyConverter_1604 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1605 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1606 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1607 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1608 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1609 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1610 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1611 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1612 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1613 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1614 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].EnergyConverterH | EnergyConverter_1615 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1616 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1617 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1618 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1619 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1620 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1621 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1622 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1623 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1624 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1625 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].EnergyConverterH | EnergyConverter_1626 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1627 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1628 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1629 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1630 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1631 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1632 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1633 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1634 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1635 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1636 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].EnergyConverterH | EnergyConverter_1637 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1638 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1639 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1640 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1642 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1643 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1644 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1645 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1646 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1647 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].EnergyConverterH | EnergyConverter_1648 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1649 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1650 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1651 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1652 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1653 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1654 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1655 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1656 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1657 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1658 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].EnergyConverterH | EnergyConverter_1659 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1660 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1661 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1662 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1663 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1664 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1665 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1666 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1667 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1668 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1669 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].EnergyConverterH | EnergyConverter_1670 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1671 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1672 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1673 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1674 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1675 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1676 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1677 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1678 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1679 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1680 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].EnergyConverterH | EnergyConverter_1681 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1682 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1683 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1684 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1685 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1686 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1687 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1688 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1689 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1690 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1691 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].EnergyConverterH | EnergyConverter_1692 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1693 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1694 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1695 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1696 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1697 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1698 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1699 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1700 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1701 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1702 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].EnergyConverterH | EnergyConverter_1703 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1704 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1705 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1706 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1707 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1708 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1709 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1711 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1712 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1713 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].EnergyConverterH | EnergyConverter_1714 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1715 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1716 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1717 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1718 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1719 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1720 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1721 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1722 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1723 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1724 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].EnergyConverterH | EnergyConverter_1725 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1726 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1727 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1728 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1729 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1730 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1731 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1732 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1733 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1734 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1735 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].EnergyConverterH | EnergyConverter_1736 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1737 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1738 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1739 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1740 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1741 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1742 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1743 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1744 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1745 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1746 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].EnergyConverterH | EnergyConverter_1747 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1748 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1749 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1750 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1751 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1752 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1753 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1754 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1755 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1756 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1757 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].EnergyConverterH | EnergyConverter_1758 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1759 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1760 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1761 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1762 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1763 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1764 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1765 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1766 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1767 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1768 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].EnergyConverterH | EnergyConverter_1769 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1770 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1771 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1772 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1773 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1774 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1775 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1776 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1777 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1778 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1779 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].EnergyConverterH | EnergyConverter_1780 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1781 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1782 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1783 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1784 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1785 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1786 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1787 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1788 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1789 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1790 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].EnergyConverterH | EnergyConverter_1791 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1792 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1793 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1794 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1795 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1796 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1797 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1798 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1799 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1800 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1801 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].EnergyConverterH | EnergyConverter_1802 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1803 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1804 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1805 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1806 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1807 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1808 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1809 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1810 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1811 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1812 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].EnergyConverterH | EnergyConverter_1813 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1814 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1815 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1816 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1817 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1818 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1819 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1820 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1821 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1822 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1823 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].EnergyConverterH | EnergyConverter_1824 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1825 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1826 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1827 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1828 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1829 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1830 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1831 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1832 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1833 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1834 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].EnergyConverterH | EnergyConverter_1835 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1836 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1837 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1838 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1839 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1840 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1841 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1842 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1843 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1844 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1845 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].EnergyConverterH | EnergyConverter_1846 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1847 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1848 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1849 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1850 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1851 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1852 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1853 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1854 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1855 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1856 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].EnergyConverterH | EnergyConverter_1857 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1858 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1859 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1860 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1861 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1862 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1863 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1864 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1865 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1866 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1867 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].EnergyConverterH | EnergyConverter_1868 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1869 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1870 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1871 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1872 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1873 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1874 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1875 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1876 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1877 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1878 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].EnergyConverterH | EnergyConverter_1879 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1880 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1881 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1882 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1883 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1884 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1885 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1886 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1887 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1888 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1889 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].EnergyConverterH | EnergyConverter_1890 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1891 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1892 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1893 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1894 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1895 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1896 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1897 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1898 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1899 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1900 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].EnergyConverterH | EnergyConverter_1901 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1902 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1903 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1904 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1905 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1906 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1907 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1908 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1909 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1910 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1911 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].EnergyConverterH | EnergyConverter_1912 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1913 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1914 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1915 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1916 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1917 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1918 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1919 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1920 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1921 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1922 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].EnergyConverterH | EnergyConverter_1923 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1924 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1925 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1926 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1927 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1928 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1929 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1930 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1931 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1932 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1933 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].EnergyConverterH | EnergyConverter_1934 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1935 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1936 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1937 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1938 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1939 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1940 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1941 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1942 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1943 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1944 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].EnergyConverterH | EnergyConverter_1945 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1946 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1947 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1948 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1949 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1950 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1951 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1952 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1953 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1954 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1955 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].EnergyConverterH | EnergyConverter_1956 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1957 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1958 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1959 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1960 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1961 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1962 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1963 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1964 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1965 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1966 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].EnergyConverterH | EnergyConverter_1967 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1968 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1969 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1970 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1971 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1972 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1973 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1974 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1975 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1976 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1977 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].EnergyConverterH | EnergyConverter_1978 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1979 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1980 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1981 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1982 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1983 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1984 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1985 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1986 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1987 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1988 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].EnergyConverterH | EnergyConverter_1989 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1990 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1991 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1992 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1993 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1994 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1995 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1996 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1997 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1998 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1999 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].EnergyConverterH | EnergyConverter_2000 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2001 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2002 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2003 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2004 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2005 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2006 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2007 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2008 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2009 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2010 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].EnergyConverterH | EnergyConverter_2011 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2012 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2013 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2014 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2015 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2016 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2017 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2018 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2019 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2020 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2021 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].EnergyConverterH | EnergyConverter_2022 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2023 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2024 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2025 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2026 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2027 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2028 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2029 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2030 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2031 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2032 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].EnergyConverterH | EnergyConverter_2033 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2034 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2035 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2036 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2037 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2038 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2039 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2040 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2041 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2042 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2043 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].EnergyConverterH | EnergyConverter_2044 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2045 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2046 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2047 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2048 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2049 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2050 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2051 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2052 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2053 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2054 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].EnergyConverterH | EnergyConverter_2055 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2056 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2057 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2058 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2059 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2060 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2061 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2062 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2063 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2064 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2065 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].EnergyConverterH | EnergyConverter_2066 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2067 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2068 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2069 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2070 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2071 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2072 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2073 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2074 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2075 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2076 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].EnergyConverterH | EnergyConverter_2077 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2078 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2079 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2080 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2081 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2082 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2084 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2085 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2086 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2087 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].EnergyConverterH | EnergyConverter_2088 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2089 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2090 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2091 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2092 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2093 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2094 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2095 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2096 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2097 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2098 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].EnergyConverterH | EnergyConverter_2099 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2100 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2101 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2102 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2103 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2104 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2105 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2106 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2107 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2108 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2109 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].EnergyConverterH | EnergyConverter_2110 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2111 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2112 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2113 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2114 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2115 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2116 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2117 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2118 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2119 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2120 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].EnergyConverterH | EnergyConverter_2121 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2122 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2123 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2124 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2125 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2126 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2127 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2128 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2129 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2130 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2131 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].EnergyConverterH | EnergyConverter_2132 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2133 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2134 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2135 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2136 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2137 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2138 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2139 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2140 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2141 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2142 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].EnergyConverterH | EnergyConverter_2143 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2144 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2145 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2146 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2147 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2148 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2149 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2150 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2151 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2152 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2153 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].EnergyConverterH | EnergyConverter_2154 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2155 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2156 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2157 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2158 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2159 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2160 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2161 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2162 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2163 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2164 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].EnergyConverterH | EnergyConverter_2165 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2166 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2167 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2168 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2169 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2170 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2171 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2172 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2173 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2174 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2175 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].EnergyConverterH | EnergyConverter_2176 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2177 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2178 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2179 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2180 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2181 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2183 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2184 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2185 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2186 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].EnergyConverterH | EnergyConverter_2187 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2188 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2189 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2190 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2191 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2192 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2193 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2194 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2195 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2196 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2197 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].EnergyConverterH | EnergyConverter_2198 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2199 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2200 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2201 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2202 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2203 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2204 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2205 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2206 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2207 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2208 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].EnergyConverterH | EnergyConverter_2209 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2210 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2211 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2212 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2213 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2214 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2215 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2216 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2217 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2218 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2219 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].EnergyConverterH | EnergyConverter_2220 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2221 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2222 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2223 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2224 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2225 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2227 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2228 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2229 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2230 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].EnergyConverterH | EnergyConverter_2231 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2232 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2233 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2234 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2235 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2236 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2237 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2238 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2239 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2240 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2241 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].EnergyConverterH | EnergyConverter_2242 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2243 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2244 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2245 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2246 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2247 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2248 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2249 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2250 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2251 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2252 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_PARAMETER_RAM | AlgoParameterRAM_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (IPBUS_ALGO_PARAMETER_RAM) | AlgoParameterRAM_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_PARAMETER_RAM | AlgoParameterRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | AlgoParameterRAM_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | AlgoParameterRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized8 | 5463(1.58%) | 5463(1.58%) | 0(0.00%) | 0(0.00%) | 2059(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LOAD_GENERATOR | LoadGenerator | 127(0.04%) | 125(0.04%) | 0(0.00%) | 2(0.01%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RATE_MONITOR | AlgoRateMonitor | 1923(0.56%) | 1922(0.55%) | 0(0.00%) | 1(0.01%) | 3215(0.46%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RATE_MONITOR) | AlgoRateMonitor | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized7 | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | NORMALISATION_CNT | counter | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_EG | counter_1498 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_TAU | counter_1499 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_EG | counter_1500 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_TAU | counter_1501 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_EG | counter_1502 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_TAU | counter_1503 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_EG | counter_1504 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_TAU | counter_1505 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_EG | counter_1506 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_TAU | counter_1507 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_EG | counter_1508 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_TAU | counter_1509 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_EG | counter_1510 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_TAU | counter_1511 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_EG | counter_1512 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_TAU | counter_1513 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_EG | counter_1514 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_TAU | counter_1515 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_EG | counter_1516 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_TAU | counter_1517 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_EG | counter_1518 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_TAU | counter_1519 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_EG | counter_1520 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_TAU | counter_1521 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_EG | counter_1522 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_TAU | counter_1523 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_EG | counter_1524 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_TAU | counter_1525 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_EG | counter_1526 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_TAU | counter_1527 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_EG | counter_1528 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_TAU | counter_1529 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_EG | counter_1530 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_TAU | counter_1531 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_EG | counter_1532 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_TAU | counter_1533 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_EG | counter_1534 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_TAU | counter_1535 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_EG | counter_1536 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_TAU | counter_1537 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_EG | counter_1538 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_TAU | counter_1539 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_EG | counter_1540 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_TAU | counter_1541 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_EG | counter_1542 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_TAU | counter_1543 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_EG | counter_1544 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_TAU | counter_1545 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_EG | counter_1546 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_TAU | counter_1547 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_EG | counter_1548 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_TAU | counter_1549 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_EG | counter_1550 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_TAU | counter_1551 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_EG | counter_1552 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_TAU | counter_1553 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_EG | counter_1554 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_TAU | counter_1555 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_EG | counter_1556 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_TAU | counter_1557 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_EG | counter_1558 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_TAU | counter_1559 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_EG | counter_1560 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_TAU | counter_1561 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_EG | counter_1562 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_TAU | counter_1563 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_EG | counter_1564 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_TAU | counter_1565 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_EG | counter_1566 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_TAU | counter_1567 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_EG | counter_1568 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_TAU | counter_1569 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_EG | counter_1570 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_TAU | counter_1571 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_EG | counter_1572 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_TAU | counter_1573 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_EG | counter_1574 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_TAU | counter_1575 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_EG | counter_1576 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_TAU | counter_1577 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_EG | counter_1578 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_TAU | counter_1579 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_EG | counter_1580 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_TAU | counter_1581 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_EG | counter_1582 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_TAU | counter_1583 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_EG | counter_1584 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_TAU | counter_1585 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_EG | counter_1586 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_TAU | counter_1587 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_EG | counter_1588 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_TAU | counter_1589 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_EG | counter_1590 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_TAU | counter_1591 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_EG | counter_1592 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_TAU | counter_1593 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOP_ALGO_MODULE | TopAlgoModule | 78033(22.53%) | 76681(22.14%) | 0(0.00%) | 1352(0.78%) | 103687(14.97%) | 0(0.00%) | 0(0.00%) | 96(3.33%) | | (TOP_ALGO_MODULE) | TopAlgoModule | 75756(21.87%) | 75756(21.87%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[0].AGLO_CORE_EG | AlgoCore_eg__xdcDup__1 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7534(1.09%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[0].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__1 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5656 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_5657 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 80(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5658 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_5659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5780 | 0(0.00%) | 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stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_5853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_5854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_5855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_5856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_5857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_5858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_5859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_5860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_5861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_5862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_5863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_5864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_5865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_5866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_5867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_5868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_5869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_5870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_5871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_5872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_5873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_5874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_5875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_5876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_5877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_5661 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_5661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5735 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_5662 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_5662 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5663 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5663 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5666 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 281(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5666 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_5667 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_5668 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5669 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__1 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3872(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_5421 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3298(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_5444 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5644 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5647 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_5445 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_5446 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_5447 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_5448 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_5449 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_5450 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_5451 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_5452 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_5453 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_5454 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5455 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5625 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5630 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5631 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5456 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5597 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5599 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5600 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5601 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5602 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5604 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5606 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5607 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5610 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_5457 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_5458 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5582 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_5459 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5567 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5571 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_5460 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5558 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5559 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_5461 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5546 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_5462 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5534 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5535 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_5463 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5519 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5520 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5522 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5523 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_5464 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5508 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5509 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5511 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5512 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_5465 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5496 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5497 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5500 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_5466 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5493 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_5467 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5490 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_5468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5487 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_5469 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5484 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_5470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_5471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_5472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_5473 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5478 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_5474 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5475 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_5422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_5423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_5424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_5425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_5426 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_5428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_5430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_5431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5432 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_5433 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_5434 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_5435 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_5437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_5438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_5440 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_5441 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5442 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_5443 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_5427 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[1].AGLO_CORE_EG | AlgoCore_eg__xdcDup__2 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7494(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[1].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__2 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5199 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_5200 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5201 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_5202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_5203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_5203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_5337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_5338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_5339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_5340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_5341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_5342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_5343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_5344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_5346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_5349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | 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stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5278 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_5205 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_5205 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5206 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5206 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5209 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5209 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_5210 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_5211 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5212 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__2 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3873(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_4964 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3298(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4987 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5187 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5190 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5191 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4988 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4989 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4990 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4991 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4992 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4993 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4994 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4995 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4996 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4997 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4998 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5168 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5169 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5171 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5173 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5175 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5176 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5177 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4999 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5141 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5142 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5143 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5145 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_5000 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_5001 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5123 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5125 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_5002 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5110 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5111 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_5003 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5098 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5099 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5101 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_5004 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5086 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5089 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5090 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_5005 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5075 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5077 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5078 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_5006 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5062 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5063 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5065 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5066 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_5007 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5051 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5054 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5055 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_5008 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5040 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5043 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_5009 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_5010 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5033 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_5011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5030 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_5012 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5027 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_5013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_5014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_5015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_5016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5021 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_5017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5018 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4967 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4969 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 202(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4975 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4976 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4977 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4978 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4983 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4984 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4985 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4986 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[2].AGLO_CORE_EG | AlgoCore_eg__xdcDup__3 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7492(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[2].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__3 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4742 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_4743 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4744 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4856 | 0(0.00%) | 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0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_4747 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4821 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_4748 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_4748 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4749 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4749 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4752 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4752 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_4753 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_4754 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4755 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__3 | 150(0.04%) | 71(0.02%) | 0(0.00%) | 79(0.05%) | 3868(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_4507 | 113(0.03%) | 64(0.02%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4530 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4733 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4531 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4532 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4533 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4534 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4535 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4536 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4537 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4538 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4539 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4540 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4541 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4716 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4718 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4542 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4685 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4686 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4687 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4688 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4693 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4695 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4544 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4545 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4653 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4657 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4546 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4644 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4547 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4548 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4617 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4618 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4620 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4621 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_4549 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4606 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_4550 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4594 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4597 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_4551 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4582 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4585 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_4552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_4553 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4576 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_4554 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4573 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_4555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_4556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_4557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_4558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_4559 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4564 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_4560 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4561 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4510 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4512 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4518 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4519 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4520 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4521 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4526 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4527 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4528 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4529 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4513 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[3].AGLO_CORE_EG | AlgoCore_eg__xdcDup__4 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7492(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[3].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__4 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4285 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_4286 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4287 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_4288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_4289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_4289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_4423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_4424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_4425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_4426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_4427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_4428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_4429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_4430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_4431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_4432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_4435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_4436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_4437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_4438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_4439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_4440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_4441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_4444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_4445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_4446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_4447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_4448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_4449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_4450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_4451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_4452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_4453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_4454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_4455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_4456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 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stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | 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0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_4290 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_4290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4364 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_4291 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_4291 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4292 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4292 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4295 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4295 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_4296 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_4297 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4298 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__4 | 150(0.04%) | 71(0.02%) | 0(0.00%) | 79(0.05%) | 3874(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__4 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_4050 | 113(0.03%) | 64(0.02%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4073 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4274 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4276 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4277 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4074 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4075 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4076 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4077 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4078 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4079 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4080 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4081 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4082 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4083 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4084 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4257 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4258 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4259 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4260 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4261 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4263 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4085 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4226 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4227 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4229 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4231 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4233 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4086 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4087 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4088 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4196 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4197 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4199 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4200 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4089 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4185 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4187 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4090 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4173 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4175 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4176 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4091 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4160 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4164 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_4092 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_4093 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4137 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4141 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_4094 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4125 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_4095 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_4096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4119 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_4097 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_4098 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_4099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_4100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_4101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_4102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4107 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_4103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4104 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4053 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4055 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 204(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4061 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4062 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4063 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4064 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4069 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4070 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4071 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4072 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4056 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[4].AGLO_CORE_EG | AlgoCore_eg__xdcDup__5 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7492(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[4].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__5 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3828 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_3829 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3830 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD85 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD86 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD88 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD89 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD90 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD91 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_3833 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_3833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3907 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_3834 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_3834 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3835 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3835 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3838 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3838 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_3839 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_3840 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3841 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__5 | 150(0.04%) | 71(0.02%) | 0(0.00%) | 79(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__5 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_3593 | 113(0.03%) | 64(0.02%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_3616 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3816 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3817 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3819 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3820 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_3617 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_3618 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_3619 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_3620 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_3621 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_3622 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_3623 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_3624 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_3625 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_3626 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3627 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3797 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3802 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3803 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3628 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3769 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3771 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3772 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3774 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3777 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3781 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3782 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_3629 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3764 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_3630 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3754 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_3631 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3739 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3743 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_3632 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_3633 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3718 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_3634 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3703 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_3635 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3695 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_3636 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_3637 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_3638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_3639 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3662 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_3640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3659 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_3641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_3642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_3643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_3644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_3645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_3646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3647 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_3596 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_3598 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3604 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_3605 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_3606 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_3607 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_3608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_3610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_3612 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_3613 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3614 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3615 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3599 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[5].AGLO_CORE_EG | AlgoCore_eg__xdcDup__6 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7499(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[5].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__6 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3371 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_3372 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3373 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD92 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD93 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | 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Adder__sblockDup__1_3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_3376 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3450 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_3377 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_3377 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3378 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3378 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3381 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3381 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_3382 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_3383 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3384 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__6 | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_3136 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_3159 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3359 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3360 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3362 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3363 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_3160 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_3161 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_3162 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_3163 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_3164 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_3165 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_3166 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_3167 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_3168 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_3169 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3170 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3340 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3341 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3344 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3345 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3347 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3348 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3171 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3312 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3313 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3314 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3317 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3319 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3321 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3324 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_3172 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3307 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_3173 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3294 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3295 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_3174 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3282 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3283 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3285 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3286 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_3175 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3273 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3274 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_3176 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3258 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3259 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3261 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_3177 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3249 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3250 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_3178 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_3179 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3223 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3224 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3226 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3227 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_3180 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3215 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_3181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_3182 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3205 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_3183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3202 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_3184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3199 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_3185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_3186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_3188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_3189 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3190 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_3139 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_3141 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3147 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_3148 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_3149 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_3150 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_3155 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_3156 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3157 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3158 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3142 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[6].AGLO_CORE_EG | AlgoCore_eg__xdcDup__7 | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7504(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[6].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__7 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_2914 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1_2915 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_2916 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1_2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1_2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1_2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_3088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_3090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_3091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_3092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_3093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_2919 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2993 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_2920 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_2920 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_2921 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_2921 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_2924 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 283(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_2924 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1_2925 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1_2926 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_2927 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__7 | 149(0.04%) | 71(0.02%) | 0(0.00%) | 78(0.04%) | 3866(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__7 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1_2679 | 112(0.03%) | 64(0.02%) | 0(0.00%) | 48(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_2702 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2902 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_2703 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_2704 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_2705 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_2706 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_2707 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_2708 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_2709 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_2710 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_2711 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_2712 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2713 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2883 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2886 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2887 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2888 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2889 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2890 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2891 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2714 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2855 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2857 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2858 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2859 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2860 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2862 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2863 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2864 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2865 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2866 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_2715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_2716 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2837 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2840 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2841 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_2717 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2825 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_2718 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2813 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2816 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2817 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_2719 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2802 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2804 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_2720 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2789 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2790 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2792 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_2721 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2777 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2781 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_2722 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2767 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2769 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_2723 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2754 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2755 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2757 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2758 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_2724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_2725 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2748 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_2726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_2727 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_2728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_2729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_2730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_2731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_2732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2733 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_2682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_2684 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2690 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_2691 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_2692 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_2693 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_2698 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_2699 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2700 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2701 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_2685 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[7].AGLO_CORE_EG | AlgoCore_eg | 137(0.04%) | 47(0.01%) | 0(0.00%) | 90(0.05%) | 7494(1.08%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[7].AGLO_CORE_EG) | AlgoCore_eg | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized0__sblockDup__1 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_16_HD29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_16_viv_HD30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2034(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 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0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_2652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_2653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_2654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_2655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_2656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_2657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_2658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_2659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_2660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_2664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_2674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2536 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 258(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 122(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 273(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1 | 12(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized2__sblockDup__1 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized1__sblockDup__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt | 151(0.04%) | 71(0.02%) | 0(0.00%) | 80(0.05%) | 3885(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1 | 114(0.03%) | 64(0.02%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_2266 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_2267 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_2268 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_2269 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_2270 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_2271 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_2272 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_2273 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1 | 17(0.01%) | 8(0.01%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2439 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2440 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2442 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2443 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2444 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2445 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2446 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2447 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2448 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2274 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2411 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2412 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2413 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2414 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2416 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2419 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2421 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2422 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2406 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_2275 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2393 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2394 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2396 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2397 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_2276 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2382 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2384 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2385 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_2277 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2373 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_2278 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2357 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2360 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2361 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_2279 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2348 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2349 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_2280 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2336 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2337 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_2281 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2326 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_2282 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2310 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2311 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2313 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2314 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2307 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_2283 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2304 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_2284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2301 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_2285 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_2286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_2287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_2288 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2292 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_2289 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1 | 30(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.02%) | 215(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_2254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2255 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_2256 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_2257 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_2258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_2259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_2260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_2262 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_2263 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2264 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2265 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_16_HD384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_16_viv_HD385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_SHIFT_REGISTER | AlgoShiftRegister | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12630(1.82%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_eg | SerialSorter | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 481(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_eg) | SerialSorter | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1493 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1494 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1495 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1496 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1497 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_tau | SerialSorter_1404 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_tau) | SerialSorter_1404 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1488 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1489 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1490 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1491 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1492 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_eg | SerialSorter_1405 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_eg) | SerialSorter_1405 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1483 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1484 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1485 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1486 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1487 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_tau | SerialSorter_1406 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_tau) | SerialSorter_1406 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1478 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1479 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1480 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1481 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1482 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_eg | SerialSorter_1407 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_eg) | SerialSorter_1407 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1473 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1474 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1475 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1476 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1477 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_tau | SerialSorter_1408 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_tau) | SerialSorter_1408 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1468 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1469 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1470 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1471 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1472 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_eg | SerialSorter_1409 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_eg) | SerialSorter_1409 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1463 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1464 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1465 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1466 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1467 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_tau | SerialSorter_1410 | 295(0.09%) | 295(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_tau) | SerialSorter_1410 | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1458 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1459 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1460 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1461 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1462 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_eg | SerialSorter_1411 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_eg) | SerialSorter_1411 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1453 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1454 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1455 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1456 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1457 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_tau | SerialSorter_1412 | 295(0.09%) | 295(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_tau) | SerialSorter_1412 | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1448 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1449 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1450 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1451 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1452 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_eg | SerialSorter_1413 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_eg) | SerialSorter_1413 | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1443 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1444 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1445 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1446 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1447 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_tau | SerialSorter_1414 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_tau) | SerialSorter_1414 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1438 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1439 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1440 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1441 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1442 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_eg | SerialSorter_1415 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_eg) | SerialSorter_1415 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1433 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1434 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1435 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1436 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1437 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_tau | SerialSorter_1416 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_tau) | SerialSorter_1416 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1428 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1429 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1430 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1431 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1432 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_eg | SerialSorter_1417 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_eg) | SerialSorter_1417 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1423 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1424 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1425 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1426 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1427 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_tau | SerialSorter_1418 | 296(0.09%) | 296(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_tau) | SerialSorter_1418 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1419 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1420 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1421 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1422 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_alignment_block | data_alignment | 19683(5.68%) | 7185(2.07%) | 0(0.00%) | 12498(7.17%) | 37512(5.41%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_alignment_block) | data_alignment | 180(0.05%) | 180(0.05%) | 0(0.00%) | 0(0.00%) | 848(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[0].bc_align_b | quad_bc_alignment | 117(0.03%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[0].bc_align_b) | quad_bc_alignment | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1400 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1401 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1402 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1403 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[10].bc_align_b | quad_bc_alignment_593 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[10].bc_align_b) | quad_bc_alignment_593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1393 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1394 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1395 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1396 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[12].bc_align_b | quad_bc_alignment_594 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[12].bc_align_b) | quad_bc_alignment_594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1385 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1386 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1387 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1388 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[13].bc_align_b | quad_bc_alignment_595 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[13].bc_align_b) | quad_bc_alignment_595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1377 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1378 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1379 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1380 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[14].bc_align_b | quad_bc_alignment_596 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[14].bc_align_b) | quad_bc_alignment_596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1369 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1370 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1371 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1372 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[15].bc_align_b | quad_bc_alignment_597 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[15].bc_align_b) | quad_bc_alignment_597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1361 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1362 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1363 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1364 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[1].bc_align_b | quad_bc_alignment_598 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[1].bc_align_b) | quad_bc_alignment_598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1353 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1354 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1355 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1356 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[2].bc_align_b | quad_bc_alignment_599 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[2].bc_align_b) | quad_bc_alignment_599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1345 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1346 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1347 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1348 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[3].bc_align_b | quad_bc_alignment_600 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[3].bc_align_b) | quad_bc_alignment_600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1337 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1338 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1339 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1340 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[4].bc_align_b | quad_bc_alignment_601 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[4].bc_align_b) | quad_bc_alignment_601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1329 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1330 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1331 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1332 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[5].bc_align_b | quad_bc_alignment_602 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[5].bc_align_b) | quad_bc_alignment_602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1321 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1322 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1323 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1324 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[6].bc_align_b | quad_bc_alignment_603 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[6].bc_align_b) | quad_bc_alignment_603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1313 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1314 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1315 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1316 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[7].bc_align_b | quad_bc_alignment_604 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[7].bc_align_b) | quad_bc_alignment_604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1305 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1306 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1307 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1308 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[8].bc_align_b | quad_bc_alignment_605 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[8].bc_align_b) | quad_bc_alignment_605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1297 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1298 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1299 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1300 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[9].bc_align_b | quad_bc_alignment_606 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[9].bc_align_b) | quad_bc_alignment_606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1289 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1290 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1291 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1292 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[0].bc_align_a | quad_bc_alignment_607 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[0].bc_align_a) | quad_bc_alignment_607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1281 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1282 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1283 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1284 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[10].bc_align_a | quad_bc_alignment_608 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[10].bc_align_a) | quad_bc_alignment_608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1274 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1275 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1276 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1277 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[12].bc_align_a | quad_bc_alignment_610 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[12].bc_align_a) | quad_bc_alignment_610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1262 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1263 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1264 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1265 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[13].bc_align_a | quad_bc_alignment_611 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[13].bc_align_a) | quad_bc_alignment_611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1254 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1255 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1256 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1257 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[14].bc_align_a | quad_bc_alignment_612 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[14].bc_align_a) | quad_bc_alignment_612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1246 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1247 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1248 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1249 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[15].bc_align_a | quad_bc_alignment_613 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[15].bc_align_a) | quad_bc_alignment_613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1238 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1239 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1240 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1241 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[1].bc_align_a | quad_bc_alignment_614 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[1].bc_align_a) | quad_bc_alignment_614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1230 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1231 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1232 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1233 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[2].bc_align_a | quad_bc_alignment_615 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[2].bc_align_a) | quad_bc_alignment_615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1222 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1223 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1224 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1225 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[3].bc_align_a | quad_bc_alignment_616 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[3].bc_align_a) | quad_bc_alignment_616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1214 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1215 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1216 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1217 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[4].bc_align_a | quad_bc_alignment_617 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[4].bc_align_a) | quad_bc_alignment_617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1206 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1207 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1208 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1209 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[5].bc_align_a | quad_bc_alignment_618 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[5].bc_align_a) | quad_bc_alignment_618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1198 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1199 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1200 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1201 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[6].bc_align_a | quad_bc_alignment_619 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[6].bc_align_a) | quad_bc_alignment_619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1190 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1191 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1192 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1193 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[7].bc_align_a | quad_bc_alignment_620 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[7].bc_align_a) | quad_bc_alignment_620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1182 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1183 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1184 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1185 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[8].bc_align_a | quad_bc_alignment_621 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[8].bc_align_a) | quad_bc_alignment_621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1174 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1175 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1176 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1177 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[9].bc_align_a | quad_bc_alignment_622 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[9].bc_align_a) | quad_bc_alignment_622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1167 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1168 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1169 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo | pseudo_orbit_gen | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo_b | pseudo_orbit_gen_623 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u0 | top_synch | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u0) | top_synch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1158 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1159 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1160 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1161 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1161 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1162 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u1 | crc_checker | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u1) | crc_checker | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1156 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u0 | top_synch_624 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u0) | top_synch_624 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1151 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1152 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1153 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1154 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1154 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1155 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u1 | crc_checker_625 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u1) | crc_checker_625 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1149 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u0 | top_synch_626 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u0) | top_synch_626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1143 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1144 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1145 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1146 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1147 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1147 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1148 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u1 | crc_checker_627 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u1) | crc_checker_627 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1142 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u0 | top_synch_628 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u0) | top_synch_628 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1137 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1138 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1139 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1140 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1140 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1141 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u1 | crc_checker_629 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u1) | crc_checker_629 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1135 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u0 | top_synch_630 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u0) | top_synch_630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1130 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1131 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1132 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1133 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1133 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1134 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u1 | crc_checker_631 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u1) | crc_checker_631 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1128 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u0 | top_synch_632 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u0) | top_synch_632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1123 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1124 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1125 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1126 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1126 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1127 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u1 | crc_checker_633 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u1) | crc_checker_633 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1121 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u0 | top_synch_634 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u0) | top_synch_634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1116 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1117 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1118 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1119 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1119 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1120 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u1 | crc_checker_635 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u1) | crc_checker_635 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1114 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u0 | top_synch_636 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u0) | top_synch_636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1109 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1110 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1111 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1112 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1112 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1113 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u1 | crc_checker_637 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u1) | crc_checker_637 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1107 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u0 | top_synch_638 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u0) | top_synch_638 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1101 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1102 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1103 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1104 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1105 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1105 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1106 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u1 | crc_checker_639 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u1) | crc_checker_639 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1100 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u0 | top_synch_640 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u0) | top_synch_640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1095 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1096 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1097 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1098 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1098 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1099 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u1 | crc_checker_641 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u1) | crc_checker_641 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1093 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u0 | top_synch_642 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u0) | top_synch_642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1088 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1089 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1090 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1091 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1091 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1092 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u1 | crc_checker_643 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u1) | crc_checker_643 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1086 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u0 | top_synch_644 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u0) | top_synch_644 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1081 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1082 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1083 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1084 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1084 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1085 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u1 | crc_checker_645 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u1) | crc_checker_645 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1079 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u0 | top_synch_646 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u0) | top_synch_646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1073 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1074 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1075 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1076 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1077 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1077 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1078 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u1 | crc_checker_647 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u1) | crc_checker_647 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1072 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u0 | top_synch_648 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u0) | top_synch_648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1066 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1067 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1068 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1069 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1070 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1070 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1071 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u1 | crc_checker_649 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u1) | crc_checker_649 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1065 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u0 | top_synch_650 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u0) | top_synch_650 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1059 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1060 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1061 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1062 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1063 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1063 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1064 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u1 | crc_checker_651 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u1) | crc_checker_651 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1058 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u0 | top_synch_652 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u0) | top_synch_652 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1053 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1054 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1055 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1056 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1056 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1057 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u1 | crc_checker_653 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u1) | crc_checker_653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1051 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u0 | top_synch_654 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u0) | top_synch_654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1045 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1046 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1047 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1048 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1049 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1049 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1050 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u1 | crc_checker_655 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u1) | crc_checker_655 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1044 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u0 | top_synch_656 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u0) | top_synch_656 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1038 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1039 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1040 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1041 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1042 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1042 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1043 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u1 | crc_checker_657 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u1) | crc_checker_657 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1037 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u0 | top_synch_658 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u0) | top_synch_658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1031 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1032 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1033 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1034 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1035 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1035 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1036 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u1 | crc_checker_659 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u1) | crc_checker_659 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1030 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u0 | top_synch_660 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u0) | top_synch_660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1024 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1025 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1026 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1027 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1028 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1028 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1029 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u1 | crc_checker_661 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u1) | crc_checker_661 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1023 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u0 | top_synch_662 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u0) | top_synch_662 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1018 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1019 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1020 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1021 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1021 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1022 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u1 | crc_checker_663 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u1) | crc_checker_663 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1016 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u0 | top_synch_664 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u0) | top_synch_664 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1010 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1011 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1012 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1013 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1014 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1014 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1015 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u1 | crc_checker_665 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u1) | crc_checker_665 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1009 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u0 | top_synch_666 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u0) | top_synch_666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1004 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1005 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1006 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1007 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1007 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1008 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u1 | crc_checker_667 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u1) | crc_checker_667 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1002 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u0 | top_synch_668 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u0) | top_synch_668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_996 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_997 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_998 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_999 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1000 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1000 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1001 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u1 | crc_checker_669 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u1) | crc_checker_669 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_995 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u0 | top_synch_670 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u0) | top_synch_670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_989 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_990 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_991 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_992 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_993 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_993 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_994 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u1 | crc_checker_671 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u1) | crc_checker_671 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_988 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u0 | top_synch_672 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u0) | top_synch_672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_982 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_983 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_984 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_985 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_986 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_986 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_987 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u1 | crc_checker_673 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u1) | crc_checker_673 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_981 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u0 | top_synch_674 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u0) | top_synch_674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_976 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_977 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_978 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_979 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_979 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_980 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u1 | crc_checker_675 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u1) | crc_checker_675 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_974 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u0 | top_synch_676 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u0) | top_synch_676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_968 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_969 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_970 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_971 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_972 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_972 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_973 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u1 | crc_checker_677 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u1) | crc_checker_677 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_967 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u0 | top_synch_678 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u0) | top_synch_678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_961 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_962 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_963 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_964 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_965 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_965 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_966 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u1 | crc_checker_679 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u1) | crc_checker_679 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_960 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u0 | top_synch_680 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u0) | top_synch_680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_954 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_955 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_956 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_957 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_958 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_958 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_959 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u1 | crc_checker_681 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u1) | crc_checker_681 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_953 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u0 | top_synch_682 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u0) | top_synch_682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_947 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_948 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_949 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_950 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_951 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_951 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_952 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u1 | crc_checker_683 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u1) | crc_checker_683 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_946 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u0 | top_synch_684 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u0) | top_synch_684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_940 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_941 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_942 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_943 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_944 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_944 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_945 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u1 | crc_checker_685 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u1) | crc_checker_685 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_939 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u0 | top_synch_686 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u0) | top_synch_686 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_933 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_934 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_935 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_936 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_937 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_937 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_938 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u1 | crc_checker_687 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u1) | crc_checker_687 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_932 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u0 | top_synch_688 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u0) | top_synch_688 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_926 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_927 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_928 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_929 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_930 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_930 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_931 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u1 | crc_checker_689 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u1) | crc_checker_689 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_925 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[40].u0 | top_synch_690 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[40].u0) | top_synch_690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_920 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_921 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_922 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_923 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_923 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_924 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[40].u1 | crc_checker_691 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[40].u1) | crc_checker_691 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_918 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[41].u0 | top_synch_692 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[41].u0) | top_synch_692 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_913 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_914 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_915 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_916 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_916 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_917 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[41].u1 | crc_checker_693 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[41].u1) | crc_checker_693 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_911 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[42].u0 | top_synch_694 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[42].u0) | top_synch_694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_906 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_907 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_908 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_909 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_909 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_910 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[42].u1 | crc_checker_695 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[42].u1) | crc_checker_695 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_904 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[43].u0 | top_synch_696 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[43].u0) | top_synch_696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_899 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_900 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_901 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_902 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_902 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_903 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[43].u1 | crc_checker_697 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[43].u1) | crc_checker_697 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_897 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u0 | top_synch_702 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u0) | top_synch_702 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_887 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_888 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_889 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_890 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_891 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_891 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_892 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u1 | crc_checker_703 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u1) | crc_checker_703 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_886 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u0 | top_synch_704 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u0) | top_synch_704 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_880 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_881 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_882 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_883 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_884 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_884 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_885 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u1 | crc_checker_705 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u1) | crc_checker_705 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_879 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u0 | top_synch_706 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u0) | top_synch_706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_873 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_874 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_875 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_876 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_877 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_877 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_878 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u1 | crc_checker_707 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u1) | crc_checker_707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_872 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u0 | top_synch_708 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u0) | top_synch_708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_866 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_867 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_868 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_869 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_870 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_870 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_871 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u1 | crc_checker_709 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u1) | crc_checker_709 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_865 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u0 | top_synch_710 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u0) | top_synch_710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_859 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_860 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_861 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_862 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_863 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_863 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_864 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u1 | crc_checker_711 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u1) | crc_checker_711 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_858 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u0 | top_synch_712 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u0) | top_synch_712 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_852 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_853 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_854 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_855 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_856 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_856 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_857 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u1 | crc_checker_713 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u1) | crc_checker_713 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_851 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u0 | top_synch_714 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u0) | top_synch_714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_846 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_847 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_848 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_849 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_849 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_850 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u1 | crc_checker_715 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u1) | crc_checker_715 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_844 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u0 | top_synch_716 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u0) | top_synch_716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_839 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_840 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_841 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_842 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_842 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_843 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u1 | crc_checker_717 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u1) | crc_checker_717 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_837 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u0 | top_synch_718 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u0) | top_synch_718 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_831 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_832 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_833 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_834 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_835 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_835 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_836 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u1 | crc_checker_719 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u1) | crc_checker_719 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_830 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u0 | top_synch_720 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u0) | top_synch_720 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_824 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_825 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_826 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_827 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_828 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_828 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_829 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u1 | crc_checker_721 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u1) | crc_checker_721 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_823 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u0 | top_synch_722 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u0) | top_synch_722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_817 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_818 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_819 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_820 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_821 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_821 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_822 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u1 | crc_checker_723 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u1) | crc_checker_723 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_816 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u0 | top_synch_724 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u0) | top_synch_724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_810 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_811 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_812 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_813 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_814 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_814 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_815 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u1 | crc_checker_725 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u1) | crc_checker_725 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_809 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u0 | top_synch_726 | 45(0.01%) | 18(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u0) | top_synch_726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_803 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_804 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_805 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_806 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_807 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_807 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_808 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u1 | crc_checker_727 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u1) | crc_checker_727 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_802 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u0 | top_synch_728 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u0) | top_synch_728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_796 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_797 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_798 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_799 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_800 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_800 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_801 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u1 | crc_checker_729 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u1) | crc_checker_729 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_795 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u0 | top_synch_730 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u0) | top_synch_730 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_789 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_790 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_791 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_792 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_793 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_793 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_794 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u1 | crc_checker_731 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u1) | crc_checker_731 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_788 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u0 | top_synch_732 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u0) | top_synch_732 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_782 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_783 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_784 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_785 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_786 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_786 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_787 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u1 | crc_checker_733 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u1) | crc_checker_733 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_781 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u0 | top_synch_734 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u0) | top_synch_734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_776 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_777 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_778 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_779 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_779 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_780 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u1 | crc_checker_735 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u1) | crc_checker_735 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_774 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u0 | top_synch_736 | 46(0.01%) | 19(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u0) | top_synch_736 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_768 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_769 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_770 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_771 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_772 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_772 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_773 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u1 | crc_checker_737 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u1) | crc_checker_737 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_767 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u0 | top_synch_738 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u0) | top_synch_738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_761 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_762 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_763 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_764 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_765 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_765 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_766 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u1 | crc_checker_739 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u1) | crc_checker_739 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_760 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u0 | top_synch_740 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u0) | top_synch_740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_754 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_755 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_756 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_757 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_758 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_758 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_759 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u1 | crc_checker_741 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u1) | crc_checker_741 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_753 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u0 | top_synch_742 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u0) | top_synch_742 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_748 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_749 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_750 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_751 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_751 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_752 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u1 | crc_checker_743 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u1) | crc_checker_743 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_746 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u0 | top_synch_744 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u0) | top_synch_744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u1 | crc_checker_745 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u1) | crc_checker_745 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bcn_cntr | local_bcn_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_TX_RX | MGT_4_quad_gen | 9978(2.88%) | 9978(2.88%) | 0(0.00%) | 0(0.00%) | 17936(2.59%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__1 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__1 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__1 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_591 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD486 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD487 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD487 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD488 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD488 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD490 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD491 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD491 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD492 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD494 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD495 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD499 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD499 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD500 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD501 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD502 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD503 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD504 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD505 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD507 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD508 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD509 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD510 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD511 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD512 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD512 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD513 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD515 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD519 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD519 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD521 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD522 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD522 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD523 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD525 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD526 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD530 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD530 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD531 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD533 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD537 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD537 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD539 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD540 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD540 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD541 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD543 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD548 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD548 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD549 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD551 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD555 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD555 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD557 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD558 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD558 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD559 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD561 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD562 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD566 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD566 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD567 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD569 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD573 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD574 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD575 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD576 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD577 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[10].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__8 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__8 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__8 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_588 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1682 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1683 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1683 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1684 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1684 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1686 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1687 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1687 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1688 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1690 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1695 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1695 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1697 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1698 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1700 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1701 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1702 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1703 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1704 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1705 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1706 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1708 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1708 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1709 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1711 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1715 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1715 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1717 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1718 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1718 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1719 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1721 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1726 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1726 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1727 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1733 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1733 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1735 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1736 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1736 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1737 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1739 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1744 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1744 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1745 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1751 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1751 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1753 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1754 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1754 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1755 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1757 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1758 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1762 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1762 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1763 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1765 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1769 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1771 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1772 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1773 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[11].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__9 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__9 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__9 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__9 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_585 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1774 | 607(0.18%) | 607(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1775 | 607(0.18%) | 607(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1775 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1776 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1776 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1779 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1779 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1780 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1782 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1787 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1787 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1789 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1790 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1792 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1793 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1794 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1795 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1796 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1797 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1798 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1799 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1800 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1800 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1801 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1803 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1807 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1807 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1809 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1810 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1810 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1811 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1813 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1818 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1818 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1819 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1825 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1825 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1827 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1828 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1828 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1829 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1831 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1832 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1836 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1836 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1837 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1839 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1843 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1843 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1845 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1846 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1846 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1847 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1849 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1854 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1854 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1855 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1857 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1861 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1862 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1863 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1864 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1865 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[12].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__10 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__10 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__10 | 622(0.18%) | 622(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__10 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_582 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD578 | 607(0.18%) | 607(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD579 | 607(0.18%) | 607(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD579 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD580 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD580 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD582 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD583 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD583 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD584 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD586 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD587 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD591 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD591 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD592 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD593 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD594 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD595 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD596 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD597 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD599 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD600 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD601 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD602 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD603 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD604 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD604 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD605 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD607 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD611 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD611 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD613 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD614 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD614 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD617 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD618 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD622 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD622 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD623 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD625 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD629 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD629 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD631 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD632 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD632 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD633 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD635 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD640 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD640 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD641 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD643 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD647 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD647 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD649 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD650 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD650 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD651 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD653 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD658 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD658 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD659 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD661 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD665 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD667 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD669 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[13].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__11 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__11 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__11 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__11 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_579 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD670 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD671 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD671 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD672 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD672 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD675 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD675 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD676 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD678 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD683 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD683 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD685 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD686 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD687 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD688 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD689 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD692 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD693 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD694 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD695 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD696 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD696 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD697 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD699 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD703 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD703 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD705 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD706 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD706 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD709 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD714 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD714 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD715 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD721 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD721 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD723 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD724 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD724 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD725 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD727 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD732 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD732 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD733 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD739 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD739 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD741 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD742 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD742 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD743 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD745 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD746 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD750 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD750 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD751 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD753 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD757 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD758 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD759 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD760 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD761 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[14].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__12 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__12 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__12 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__12 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_576 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD762 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD763 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD763 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD764 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD764 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD767 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD767 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD768 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD770 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD771 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD775 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD775 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD776 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD777 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD778 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD781 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD782 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD784 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD785 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD786 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD787 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD788 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD788 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD789 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD791 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD795 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD795 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD797 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD798 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD798 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD799 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD801 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD802 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD806 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD806 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD807 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD809 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD813 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD813 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD815 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD816 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD816 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD817 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD819 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD820 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD824 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD824 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD825 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD831 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD831 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD833 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD834 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD834 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD835 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD837 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD842 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD842 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD843 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD849 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD851 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD852 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD853 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[16].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__13 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__13 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__13 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__13 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_573 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD854 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD855 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD855 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD856 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD856 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD858 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD859 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD859 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD860 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD862 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD863 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD867 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD867 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD868 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD869 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD870 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD871 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD872 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD873 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD875 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD876 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD879 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD880 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD880 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD881 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD883 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD887 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD887 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD889 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD890 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD890 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD891 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD893 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD894 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD898 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD898 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD899 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD901 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD905 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD905 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD907 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD908 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD908 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD909 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD911 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD916 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD916 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD917 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD923 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD923 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD925 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD926 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD926 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD927 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD929 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD930 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD934 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD934 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD935 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD937 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD941 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD942 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD943 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD944 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD945 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[17].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__14 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__14 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__14 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__14 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_570 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD946 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD947 | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD947 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD948 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD948 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD950 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD951 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD951 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD952 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD954 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD955 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD959 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD959 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD960 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD961 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD962 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD963 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD964 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD965 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD966 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD967 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD968 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD969 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD970 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD971 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD972 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD972 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD973 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD979 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD979 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD981 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD982 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD982 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD983 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD985 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD986 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD990 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD990 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD991 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD993 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD997 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD997 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD999 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1000 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1000 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1003 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1008 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1008 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1009 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1015 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1015 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1017 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1018 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1018 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1019 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1021 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1022 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1026 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1026 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1027 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1029 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1033 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1034 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1035 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1036 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1037 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[18].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__15 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__15 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__15 | 624(0.18%) | 624(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__15 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_567 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1038 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1039 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1039 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1040 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1040 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1043 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1043 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1044 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1046 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1047 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1051 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1051 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1053 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1054 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1055 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1056 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1057 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1058 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1059 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1060 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1061 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1062 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1063 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1064 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1064 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1065 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1067 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1071 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1071 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1073 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1074 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1074 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1075 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1077 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1078 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1082 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1082 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1083 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1085 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1089 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1089 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1091 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1092 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1092 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1093 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1095 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1100 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1100 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1101 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1103 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1107 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1107 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1109 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1110 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1110 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1111 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1113 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1114 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1118 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1118 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1119 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1121 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1125 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1127 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1129 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[19].mgt_1quad_Rx_Tx | mgt_selection_wrapper | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_564 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init | 611(0.18%) | 611(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[1].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__2 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__2 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__2 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__2 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_561 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1130 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1131 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1131 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1132 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1132 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1134 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1135 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1135 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1136 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1138 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1139 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1143 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1143 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1144 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1145 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1146 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1148 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1149 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1152 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1155 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1156 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1156 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1157 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1159 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1163 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1163 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1166 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1166 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1167 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1169 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1170 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1174 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1174 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1175 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1177 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1181 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1181 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1183 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1184 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1184 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1185 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1187 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1192 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1192 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1193 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1195 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1199 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1199 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1201 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1202 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1202 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1203 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1205 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1210 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1210 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1211 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1213 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1217 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1218 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1219 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1221 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[5].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__3 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__3 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__3 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_558 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1222 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1223 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1223 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1224 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1224 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1226 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1227 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1227 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1228 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1230 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1231 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1235 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1235 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1236 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1237 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1238 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1239 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1241 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1243 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1244 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1245 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1246 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1247 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1248 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1248 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1249 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1251 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1255 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1255 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1257 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1258 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1258 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1259 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1261 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1266 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1266 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1267 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1273 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1273 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1275 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1276 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1276 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1277 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1279 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1280 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1284 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1284 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1285 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1287 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1291 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1291 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1293 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1294 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1294 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1295 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1297 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1298 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1302 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1302 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1303 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1305 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1309 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1310 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1311 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1312 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1313 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[6].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__4 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__4 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__4 | 626(0.18%) | 626(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__4 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_555 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1314 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1315 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1315 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1316 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1316 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1319 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1319 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1320 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1322 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1323 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1327 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1327 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1328 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1329 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1330 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1333 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1334 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1335 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1336 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1337 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1339 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1340 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1340 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1341 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1347 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1347 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1349 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1350 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1350 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1351 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1353 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1354 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1358 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1358 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1359 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1361 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1365 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1365 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1367 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1368 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1368 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1371 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1376 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1376 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1377 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1379 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1383 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1383 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1386 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1386 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1387 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1389 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1390 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1394 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1394 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1395 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1397 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1401 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1403 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1404 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1405 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[7].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__5 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__5 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__5 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__5 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_552 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1406 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1407 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1407 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1408 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1408 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1410 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1411 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1411 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1412 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1414 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1419 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1419 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1420 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1421 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1422 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1425 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1426 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1427 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1428 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1429 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1431 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1432 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1432 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1433 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1435 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1439 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1439 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1441 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1442 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1442 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1443 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1445 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1446 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1450 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1450 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1451 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1457 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1457 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1459 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1460 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1460 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1461 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1463 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1464 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1468 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1468 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1469 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1471 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1475 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1475 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1477 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1478 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1478 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1479 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1481 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1482 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1486 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1486 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1487 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1489 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1493 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1494 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1495 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1496 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1497 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[8].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__6 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__6 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__6 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_549 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1498 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1499 | 608(0.18%) | 608(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1499 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1500 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1500 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1503 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1503 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1504 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1506 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1507 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1511 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1511 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1512 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1513 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1514 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1515 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1516 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1517 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1518 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1519 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1520 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1521 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1522 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1523 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1524 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1524 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1525 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1531 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1531 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1533 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1534 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1534 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1535 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1537 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1538 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1542 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1542 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1543 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1549 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1549 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1551 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1552 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1552 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1553 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1555 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1560 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1560 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1561 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1563 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1567 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1567 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1569 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1570 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1570 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1571 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1573 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1574 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1578 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1578 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1579 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1581 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1585 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1587 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1588 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1589 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[9].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__7 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__7 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__7 | 625(0.18%) | 625(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1590 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1591 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_init_HD1591 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1592 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1592 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_80_HD1593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_81_HD1594 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1595 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1595 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_73_HD1596 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_74_HD1597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_75_HD1598 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_76_HD1599 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_77_HD1600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_78_HD1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_79_HD1602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1603 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1603 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_62_HD1604 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_63_HD1605 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_HD1606 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_64_HD1607 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_65_HD1608 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_66_HD1609 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_67_HD1610 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_68_HD1611 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_69_HD1612 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_70_HD1613 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_71_HD1614 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_pulse_72_HD1615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1616 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1616 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_56_HD1617 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_57_HD1618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_58_HD1619 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_59_HD1620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_60_HD1621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_61_HD1622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1623 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1623 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_54_HD1624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_55_HD1625 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1626 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1626 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_47_HD1627 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_48_HD1628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_49_HD1629 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_50_HD1630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_51_HD1631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_52_HD1632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_53_HD1633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1634 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1634 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_41_HD1635 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_42_HD1636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_43_HD1637 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_44_HD1638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_45_HD1639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_46_HD1640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1641 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1641 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_39_HD1642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_40_HD1643 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1644 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1644 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_32_HD1645 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_33_HD1646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_34_HD1647 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_35_HD1648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_36_HD1649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_37_HD1650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_38_HD1651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1652 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1652 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_26_HD1653 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_27_HD1654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_28_HD1655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_29_HD1656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_30_HD1657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_31_HD1658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1659 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1659 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_24_HD1660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_25_HD1661 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1662 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1662 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_17_HD1663 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_18_HD1664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_19_HD1665 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_20_HD1666 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_21_HD1667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_22_HD1668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_23_HD1669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1670 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1670 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_HD1671 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_12_HD1672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_13_HD1673 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_14_HD1674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_15_HD1675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_sync_block_16_HD1676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_multi_gt_HD1677 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_HD1678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_9_HD1679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_10_HD1680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_min_latency_1_quad_rx_tx_GT_11_HD1681 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_ipb | mgt_slaves | 35854(10.35%) | 35854(10.35%) | 0(0.00%) | 0(0.00%) | 8589(1.24%) | 512(43.39%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[0].quad | mgt_quad_slaves__xdcDup__1 | 3546(1.02%) | 3546(1.02%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[0].quad) | mgt_quad_slaves__xdcDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__1 | 858(0.25%) | 858(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_543 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_544 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_545 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_546 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__1 | 817(0.24%) | 817(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__1 | 809(0.23%) | 809(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_547 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__2 | 865(0.25%) | 865(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_538 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_539 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_540 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_541 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__2 | 824(0.24%) | 824(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__2 | 816(0.24%) | 816(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_542 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__3 | 892(0.26%) | 892(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_533 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_534 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_535 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_536 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__3 | 851(0.25%) | 851(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__3 | 843(0.24%) | 843(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_537 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__4 | 887(0.26%) | 887(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_528 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_529 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_530 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_531 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__4 | 839(0.24%) | 839(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__4 | 831(0.24%) | 831(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_532 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_521 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_523 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_525 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_526 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[10].quad | mgt_quad_slaves__xdcDup__8 | 2474(0.71%) | 2474(0.71%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[10].quad) | mgt_quad_slaves__xdcDup__8 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__41 | 577(0.17%) | 577(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_516 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_517 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_518 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_519 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__41 | 536(0.15%) | 536(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__41 | 528(0.15%) | 528(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_520 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__42 | 636(0.18%) | 636(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_511 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_512 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_513 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_514 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__42 | 595(0.17%) | 595(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__42 | 587(0.17%) | 587(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_515 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__43 | 646(0.19%) | 646(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_506 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_507 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_508 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_509 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__43 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__43 | 597(0.17%) | 597(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_510 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__44 | 586(0.17%) | 586(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_501 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_502 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_503 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_504 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__44 | 537(0.16%) | 537(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__44 | 529(0.15%) | 529(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_505 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_494 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_496 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_498 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_500 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[11].quad | mgt_quad_slaves__xdcDup__9 | 2461(0.71%) | 2461(0.71%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[11].quad) | mgt_quad_slaves__xdcDup__9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__45 | 612(0.18%) | 612(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_489 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_490 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_491 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_492 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__45 | 571(0.16%) | 571(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__45 | 563(0.16%) | 563(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_493 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__46 | 636(0.18%) | 636(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_484 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_485 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_486 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_487 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__46 | 595(0.17%) | 595(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__46 | 587(0.17%) | 587(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_488 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__47 | 582(0.17%) | 582(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_479 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_480 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_481 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_482 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__47 | 541(0.16%) | 541(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__47 | 533(0.15%) | 533(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_483 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__48 | 593(0.17%) | 593(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_474 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_475 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_476 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_477 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__48 | 544(0.16%) | 544(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__48 | 536(0.15%) | 536(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_478 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_467 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_469 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_471 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_472 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_473 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[12].quad | mgt_quad_slaves__xdcDup__10 | 3101(0.90%) | 3101(0.90%) | 0(0.00%) | 0(0.00%) | 554(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[12].quad) | mgt_quad_slaves__xdcDup__10 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__49 | 547(0.16%) | 547(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_462 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_463 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_464 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_465 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__49 | 505(0.15%) | 505(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__49 | 497(0.14%) | 497(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_466 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__50 | 665(0.19%) | 665(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_457 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_458 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_459 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_460 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__50 | 623(0.18%) | 623(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__50 | 615(0.18%) | 615(0.18%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_461 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__51 | 913(0.26%) | 913(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_452 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_453 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_454 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_455 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__51 | 870(0.25%) | 870(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__51 | 861(0.25%) | 861(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_456 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__52 | 931(0.27%) | 931(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_447 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_448 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_449 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_450 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__52 | 881(0.25%) | 881(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__52 | 873(0.25%) | 873(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_451 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_440 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_442 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_444 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_445 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_446 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[13].quad | mgt_quad_slaves__xdcDup__11 | 3561(1.03%) | 3561(1.03%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[13].quad) | mgt_quad_slaves__xdcDup__11 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__53 | 868(0.25%) | 868(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_435 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_436 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_437 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_438 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__53 | 827(0.24%) | 827(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__53 | 819(0.24%) | 819(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_439 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__54 | 867(0.25%) | 867(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_430 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_431 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_432 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_433 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__54 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__54 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_434 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__55 | 882(0.25%) | 882(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_425 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_426 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_427 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_428 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__55 | 841(0.24%) | 841(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__55 | 833(0.24%) | 833(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_429 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__56 | 897(0.26%) | 897(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_420 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_421 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_422 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_423 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__56 | 849(0.25%) | 849(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__56 | 841(0.24%) | 841(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_424 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_413 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_415 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_417 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_418 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_419 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[14].quad | mgt_quad_slaves__xdcDup__12 | 3562(1.03%) | 3562(1.03%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[14].quad) | mgt_quad_slaves__xdcDup__12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__57 | 875(0.25%) | 875(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_408 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_409 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_410 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_411 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__57 | 833(0.24%) | 833(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__57 | 825(0.24%) | 825(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_412 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__58 | 867(0.25%) | 867(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_403 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_404 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_405 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_406 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__58 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__58 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_407 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__59 | 890(0.26%) | 890(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_398 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_399 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_400 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_401 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__59 | 849(0.25%) | 849(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__59 | 841(0.24%) | 841(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_402 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__60 | 883(0.25%) | 883(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_393 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_394 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_395 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_396 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__60 | 835(0.24%) | 835(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__60 | 827(0.24%) | 827(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_397 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_386 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_388 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_390 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_391 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_392 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[16].quad | mgt_quad_slaves__xdcDup__13 | 955(0.28%) | 955(0.28%) | 0(0.00%) | 0(0.00%) | 534(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[16].quad) | mgt_quad_slaves__xdcDup__13 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__65 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_381 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_382 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_383 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_384 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__65 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__65 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_385 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__66 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_376 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_377 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_378 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_379 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__66 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__66 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_380 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__67 | 452(0.13%) | 452(0.13%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_371 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_372 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_373 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_374 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__67 | 410(0.12%) | 410(0.12%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__67 | 402(0.12%) | 402(0.12%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_375 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__68 | 334(0.10%) | 334(0.10%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_366 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_367 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_368 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_369 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__68 | 293(0.08%) | 293(0.08%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__68 | 285(0.08%) | 285(0.08%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_370 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_359 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_361 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_363 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_364 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_365 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[17].quad | mgt_quad_slaves__xdcDup__14 | 921(0.27%) | 921(0.27%) | 0(0.00%) | 0(0.00%) | 534(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[17].quad) | mgt_quad_slaves__xdcDup__14 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__69 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_354 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_355 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_356 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_357 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__69 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__69 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_358 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__70 | 342(0.10%) | 342(0.10%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_349 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_350 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_351 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_352 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__70 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__70 | 293(0.08%) | 293(0.08%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_353 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__71 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_344 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_345 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_346 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_347 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__71 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__71 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_348 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__72 | 397(0.11%) | 397(0.11%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_339 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_340 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_341 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_342 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__72 | 356(0.10%) | 356(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__72 | 348(0.10%) | 348(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_343 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_332 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_334 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_336 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_337 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_338 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[18].quad | mgt_quad_slaves__xdcDup__15 | 1032(0.30%) | 1032(0.30%) | 0(0.00%) | 0(0.00%) | 538(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[18].quad) | mgt_quad_slaves__xdcDup__15 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__73 | 449(0.13%) | 449(0.13%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_327 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_328 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_329 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_330 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__73 | 408(0.12%) | 408(0.12%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__73 | 400(0.12%) | 400(0.12%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_331 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__74 | 396(0.11%) | 396(0.11%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_322 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_323 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_324 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_325 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__74 | 355(0.10%) | 355(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__74 | 347(0.10%) | 347(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_326 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__75 | 75(0.02%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_317 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_318 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_319 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_320 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__75 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__75 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_321 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__76 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_312 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_313 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_314 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_315 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__76 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__76 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_316 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_305 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_307 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_309 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_310 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_311 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[19].quad | mgt_quad_slaves | 313(0.09%) | 313(0.09%) | 0(0.00%) | 0(0.00%) | 526(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[19].quad) | mgt_quad_slaves | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__77 | 74(0.02%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_300 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_301 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_302 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_303 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__77 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__77 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD1945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD1946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD1947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD1948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD1949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD1950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD1951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD1952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD1953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD1954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD1955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD1956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD1957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD1958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD1959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD1960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD1961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD1962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD1963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD1964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD1965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_304 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__78 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_295 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_296 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_297 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_298 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__78 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__78 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD1966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD1967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD1968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD1969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD1970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD1971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD1972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD1973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD1974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD1975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD1976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD1977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD1978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD1979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD1980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD1981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD1982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD1983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD1984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD1985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD1986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_299 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__79 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_290 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_291 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_292 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_293 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__79 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__79 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD1987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD1988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD1989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD1990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD1991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD1992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD1993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD1994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD1995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD1996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD1997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD1998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD1999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_294 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_285 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_286 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_287 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_288 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_289 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_278 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_281 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_283 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_284 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[1].quad | mgt_quad_slaves__xdcDup__2 | 3672(1.06%) | 3672(1.06%) | 0(0.00%) | 0(0.00%) | 558(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[1].quad) | mgt_quad_slaves__xdcDup__2 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__5 | 948(0.27%) | 948(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_273 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_274 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_275 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_276 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__5 | 907(0.26%) | 907(0.26%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__5 | 899(0.26%) | 899(0.26%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_277 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__6 | 866(0.25%) | 866(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_268 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_269 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_270 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_271 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__6 | 825(0.24%) | 825(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__6 | 817(0.24%) | 817(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_272 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__7 | 936(0.27%) | 936(0.27%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_263 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_264 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_265 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_266 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__7 | 895(0.26%) | 895(0.26%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__7 | 887(0.26%) | 887(0.26%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_267 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__8 | 875(0.25%) | 875(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_258 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_259 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_260 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_261 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__8 | 834(0.24%) | 834(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__8 | 826(0.24%) | 826(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_262 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_251 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_253 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_256 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_257 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[5].quad | mgt_quad_slaves__xdcDup__3 | 2965(0.86%) | 2965(0.86%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[5].quad) | mgt_quad_slaves__xdcDup__3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__21 | 859(0.25%) | 859(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_246 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_247 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_248 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_249 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__21 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__21 | 810(0.23%) | 810(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_250 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__22 | 881(0.25%) | 881(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_241 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_242 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_243 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_244 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__22 | 840(0.24%) | 840(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__22 | 832(0.24%) | 832(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_245 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__23 | 572(0.17%) | 572(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_236 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_237 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_238 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_239 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__23 | 531(0.15%) | 531(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__23 | 523(0.15%) | 523(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_240 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__24 | 607(0.18%) | 607(0.18%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_231 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_232 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_233 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_234 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__24 | 557(0.16%) | 557(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__24 | 549(0.16%) | 549(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_235 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_224 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_226 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_229 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[6].quad | mgt_quad_slaves__xdcDup__4 | 2671(0.77%) | 2671(0.77%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[6].quad) | mgt_quad_slaves__xdcDup__4 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__25 | 727(0.21%) | 727(0.21%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_219 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_220 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_221 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_222 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__25 | 686(0.20%) | 686(0.20%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__25 | 678(0.20%) | 678(0.20%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_223 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__26 | 682(0.20%) | 682(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_214 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_215 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_216 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_217 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__26 | 641(0.19%) | 641(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__26 | 633(0.18%) | 633(0.18%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_218 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__27 | 651(0.19%) | 651(0.19%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_209 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_210 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_211 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_212 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__27 | 610(0.18%) | 610(0.18%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__27 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_213 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__28 | 574(0.17%) | 574(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_204 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_205 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_206 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_207 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__28 | 524(0.15%) | 524(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__28 | 515(0.15%) | 515(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_208 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_197 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_199 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_201 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_202 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_203 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[7].quad | mgt_quad_slaves__xdcDup__5 | 2629(0.76%) | 2629(0.76%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[7].quad) | mgt_quad_slaves__xdcDup__5 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__29 | 707(0.20%) | 707(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_192 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_193 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_194 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_195 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__29 | 666(0.19%) | 666(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__29 | 658(0.19%) | 658(0.19%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_196 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__30 | 688(0.20%) | 688(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_187 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_188 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_189 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_190 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__30 | 647(0.19%) | 647(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__30 | 639(0.18%) | 639(0.18%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_191 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__31 | 598(0.17%) | 598(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_182 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_183 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_184 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_185 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__31 | 557(0.16%) | 557(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__31 | 549(0.16%) | 549(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_186 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__32 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_177 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_178 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_179 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_180 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__32 | 557(0.16%) | 557(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__32 | 549(0.16%) | 549(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_181 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_170 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_172 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_175 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_176 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[8].quad | mgt_quad_slaves__xdcDup__6 | 171(0.05%) | 171(0.05%) | 0(0.00%) | 0(0.00%) | 395(0.06%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[8].quad) | mgt_quad_slaves__xdcDup__6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__33 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_166 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_167 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_168 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__33 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_169 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__34 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_162 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_163 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_164 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__34 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__34 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_165 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__35 | 36(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_158 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_159 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_160 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__35 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__35 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_161 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__36 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_154 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_155 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_156 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__36 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_157 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_149 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_151 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_152 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_153 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[9].quad | mgt_quad_slaves__xdcDup__7 | 1949(0.56%) | 1949(0.56%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[9].quad) | mgt_quad_slaves__xdcDup__7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__37 | 564(0.16%) | 564(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_142 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_143 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_144 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_145 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__37 | 523(0.15%) | 523(0.15%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__37 | 515(0.15%) | 515(0.15%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_146 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__38 | 697(0.20%) | 697(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_137 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_138 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_139 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_140 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__38 | 656(0.19%) | 656(0.19%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__38 | 648(0.19%) | 648(0.19%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_141 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__39 | 586(0.17%) | 586(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_132 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_133 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_134 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_135 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__39 | 545(0.16%) | 545(0.16%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__39 | 537(0.16%) | 537(0.16%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_136 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__40 | 76(0.02%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_129 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_130 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_131 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__40 | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__40 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_4_HD3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_4_synth_HD3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_123 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_125 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_127 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READOUT_IF.Readout_block | Readout_logic_top | 15021(4.34%) | 14964(4.32%) | 0(0.00%) | 57(0.03%) | 50758(7.33%) | 166(14.07%) | 83(3.52%) | 0(0.00%) | | (READOUT_IF.Readout_block) | Readout_logic_top | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 138(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_ECR_debug_counter | cntr_generic | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_L1A_debug_counter | cntr_generic_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_RAW_busy | cntr_generic_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOB_LO_fifo_tidemark | tide_mark_block | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOB_busy | cntr_generic_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOBs_readout | TOBs_rdout | 6036(1.74%) | 5981(1.73%) | 0(0.00%) | 55(0.03%) | 14542(2.10%) | 106(8.98%) | 33(1.40%) | 0(0.00%) | | (U0_TOBs_readout) | TOBs_rdout | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_FIFO_BCN_L1A | FIFO_47b_512_HD3605 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_5_HD3606 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_5_synth_HD3607 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top_HD3608 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo_HD3609 | 97(0.03%) | 97(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs_HD3610 | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs_HD3610 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray_HD3611 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2_HD3612 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic_HD3613 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as_HD3614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as_HD3615 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as_HD3615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1_HD3616 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2_HD3617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr_HD3619 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic_HD3620 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as_HD3621 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as_HD3622 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as_HD3622 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_HD3623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0_HD3624 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr_HD3625 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory_HD3626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_4_HD3627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_4_synth_HD3628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top_HD3629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr_HD3630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width_HD3631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper_HD3632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo_HD3633 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo_HD3633 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst_HD3634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single_HD3635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2_HD3636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1_HD3637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_flag_fsm | busy_flag_fsm_98 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_TOB_SPY_mem | ipbus_dpram_99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3_100 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_gen_sync_280 | gen_sync_280M_101 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOBs_eg_sorting | XTOBs_sorting__xdcDup__1 | 678(0.20%) | 649(0.19%) | 0(0.00%) | 29(0.02%) | 4714(0.68%) | 48(4.07%) | 16(0.68%) | 0(0.00%) | | (U2_XTOBs_eg_sorting) | XTOBs_sorting__xdcDup__1 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1967(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit_113 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_252b_512_HD3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_252b_512_HD4191 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4192 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4193 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4194 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4195 | 84(0.02%) | 81(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4196 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4196 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4197 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4198 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4199 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_252b_512_rd_dc_as_HD4200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4201 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4201 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4202 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4205 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4206 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4209 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4212 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4213 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4214 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4215 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4216 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4217 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4224 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4224 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4225 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_252b_512_HD3805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_252b_512_HD4231 | 74(0.02%) | 71(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4232 | 74(0.02%) | 71(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4233 | 74(0.02%) | 71(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4234 | 74(0.02%) | 71(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4235 | 74(0.02%) | 71(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4236 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4236 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4237 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4238 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4239 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4241 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4241 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4245 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4246 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4249 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4249 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4251 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4252 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4253 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4254 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4255 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4256 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4257 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4264 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4264 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4265 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4266 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4266 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_252b_512_HD3818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_252b_512_HD4271 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4272 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4273 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4274 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4275 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4276 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4276 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4277 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4278 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4279 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4281 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4281 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4282 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4285 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4286 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4289 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4289 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4291 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4292 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4293 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4294 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4295 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4296 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4297 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4304 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4304 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4305 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4306 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4306 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_252b_512_HD3831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_252b_512_HD4311 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4312 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4313 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4314 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4315 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4316 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4316 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4317 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4318 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4319 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4321 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4321 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_252b_512_rd_handshaking_flags_HD4324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4325 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4326 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_252b_512_wr_pf_as_HD4327 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4329 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4329 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4332 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4333 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4334 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4335 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4336 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4337 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4344 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4344 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4345 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4346 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4346 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_252b_512_HD3844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_252b_512_HD4351 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4352 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4353 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4354 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4355 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4356 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4356 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4357 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4358 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4359 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4361 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4361 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4362 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4365 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4366 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4369 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4371 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4372 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4373 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4374 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4375 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4376 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4377 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4384 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4384 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4385 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4386 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4386 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 167(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_252b_512_HD3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_252b_512_HD4391 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4392 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4393 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4394 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4395 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4396 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4396 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4397 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4398 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4399 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4401 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4401 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4405 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4406 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4409 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4409 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4411 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4412 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4413 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4414 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4415 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4416 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4417 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4424 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4424 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4425 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4426 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4426 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_252b_512_HD3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_252b_512_HD4431 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4432 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4433 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4434 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4435 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4436 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4436 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4437 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4438 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4439 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4441 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4441 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4442 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4445 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4446 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4449 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4449 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4451 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4452 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4453 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4454 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4455 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4456 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4457 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4464 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4464 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4465 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4466 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4466 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_252b_512_HD3883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_252b_512_HD4471 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4472 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4473 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4474 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4475 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4476 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4476 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4477 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4478 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4479 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4481 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4481 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4482 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4485 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4486 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4489 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4489 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4491 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4492 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4493 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4494 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4495 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4496 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4497 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4504 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4504 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4505 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4506 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4506 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO_121 | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO_121 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b_122 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_BCN_Delay | GeneralDelay | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOBs_tau_sorting | XTOBs_sorting | 674(0.19%) | 649(0.19%) | 0(0.00%) | 25(0.01%) | 4939(0.71%) | 48(4.07%) | 16(0.68%) | 0(0.00%) | | (U3_XTOBs_tau_sorting) | XTOBs_sorting | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 1966(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 195(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_252b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_252b_512 | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5 | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_252b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 197(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_252b_512_HD3701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_252b_512_HD3911 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD3912 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD3913 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3914 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3915 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3916 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3916 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3917 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3918 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3919 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3921 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3921 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3922 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3925 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3926 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3929 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3929 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3931 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3932 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3933 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD3934 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD3935 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3936 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3937 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3944 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3944 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3945 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3946 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3946 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD3947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD3948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD3949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD3950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_252b_512_HD3714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_252b_512_HD3951 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD3952 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD3953 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3954 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3955 | 77(0.02%) | 74(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3956 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3956 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3957 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3958 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3959 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3961 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3961 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3962 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3965 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3966 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3969 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3969 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3971 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3972 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3973 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD3974 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD3975 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3976 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3977 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3984 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3984 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3985 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3986 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3986 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD3987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD3988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD3989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD3990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_252b_512_HD3727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_252b_512_HD3991 | 95(0.03%) | 92(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD3992 | 95(0.03%) | 92(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD3993 | 95(0.03%) | 92(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3994 | 95(0.03%) | 92(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3995 | 95(0.03%) | 92(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3996 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3996 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3997 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3998 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3999 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4001 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4002 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4005 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4006 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_252b_512_wr_pf_as_HD4007 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4009 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4009 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4011 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4012 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4013 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4014 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4015 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4016 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4017 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4024 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4024 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4025 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4026 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4026 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_252b_512_HD3740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_252b_512_HD4031 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4032 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4033 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4034 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4035 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4036 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4036 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4037 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4038 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4039 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4041 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4041 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4045 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4046 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4049 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4049 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4051 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4052 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4053 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4054 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4055 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4056 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4057 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4064 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4064 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4065 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4066 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4066 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 197(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_252b_512_HD3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_252b_512_HD4071 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4072 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4073 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4074 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4075 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4076 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4076 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4077 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4078 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4079 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4081 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4081 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4085 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4086 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4089 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4089 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4092 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4093 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4094 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4095 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4096 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4097 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4104 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4104 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4105 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4106 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4106 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_252b_512_HD3766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_252b_512_HD4111 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4112 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4113 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4114 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4115 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4116 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4116 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4117 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4118 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4119 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4121 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4121 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4125 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4126 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4129 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4132 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4133 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4134 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4135 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4136 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4137 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4144 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4144 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4145 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4146 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4146 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_252b_512_HD3779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_4_HD3780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_4_synth_HD3781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_252b_512_HD4151 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_5_HD4152 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_5_synth_HD4153 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4154 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4155 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4156 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4156 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4157 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4158 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4159 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4161 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4161 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4162 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4165 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4166 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4169 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4169 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4171 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4172 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4173 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_4_HD4174 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_4_synth_HD4175 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4176 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4177 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4184 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4184 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4185 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4186 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4186 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_rd_mux_fsm | fsm_TOBs_to_muxPISO | 4369(1.26%) | 4369(1.26%) | 0(0.00%) | 0(0.00%) | 4248(0.61%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U6_rd_mux_fsm) | fsm_TOBs_to_muxPISO | 4350(1.26%) | 4350(1.26%) | 0(0.00%) | 0(0.00%) | 4222(0.61%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_TOB_payld_length | cntr_generic__parameterized2_104 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_eg_cntr | cntr_generic__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_tau_cntr | cntr_generic__parameterized1_105 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO | FIFO_33b_8192_HD3639 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_5_HD3640 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_5_synth_HD3641 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top_HD3642 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo_HD3643 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs_HD3644 | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs_HD3644 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray_HD3645 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2_HD3646 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic_HD3647 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as_HD3648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as_HD3649 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as_HD3649 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2_HD3650 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3_HD3651 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr_HD3653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic_HD3654 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as_HD3655 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_33b_8192_wr_dc_as_HD3656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as_HD3657 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as_HD3657 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_HD3658 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1_HD3659 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr_HD3660 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory_HD3661 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_4_HD3662 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_4_synth_HD3663 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top_HD3664 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr_HD3665 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec_HD3666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0_HD3667 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0_HD3668 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width_HD3669 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper_HD3670 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0_HD3671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0_HD3672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1_HD3673 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1_HD3674 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2_HD3675 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2_HD3676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3_HD3677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3_HD3678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4_HD3679 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4_HD3680 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5_HD3681 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5_HD3682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6_HD3683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6_HD3684 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo_HD3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_TOB_Link_output_FIFO_FSM | FIFO_to_MGT_TOB_FSM | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_clk_closs_pulse | clk_closs_pulse_fsm_102 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_frame_counter | cntr_up_dn_generic_103 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_raw_duration_counter | cntr_generic_9 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_tob_duration_counter | cntr_generic_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_real_time_40m_counter | cntr_generic_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_tob_bcn_tidemark | tide_mark_block_12 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_xtob_data_tidemark | tide_mark_block_13 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_bcn_l1a_valid_checker | bcn_l1a_valid_checker | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 350(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U17_bcn_l1a_valid_checker) | bcn_l1a_valid_checker | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 222(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_mismatch_cntr_block | cntr_generic__parameterized4 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_parity_err_cntr_block | cntr_generic__parameterized4_95 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_mismatch_cntr_block | cntr_generic__parameterized4_96 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_parity_err_cntr_block | cntr_generic__parameterized4_97 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_LO_fifo_tidemark | tide_mark_block_14 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_bcn_tidemark | tide_mark_block_15 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_data_tidemark | tide_mark_block_16 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_readout | RAW_data_rdout | 8297(2.40%) | 8295(2.39%) | 0(0.00%) | 2(0.01%) | 34481(4.98%) | 60(5.08%) | 50(2.12%) | 0(0.00%) | | (U1_RAW_readout) | RAW_data_rdout | 86(0.02%) | 85(0.02%) | 0(0.00%) | 1(0.01%) | 15091(2.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U1_gen_sync_280 | gen_sync_280M | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U2_PISO_RAW | PISO_RAW_data | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U3_DPRAM_RAW_Data | DPR_36b_1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U4_FIFO_RAW_Data | FIFO_36b_512 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[10].U2_PISO_RAW | PISO_RAW_data_47 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U4_FIFO_RAW_Data | FIFO_36b_512_HD4943 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD4944 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD4945 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4946 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4947 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4948 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4952 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4952 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4954 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4955 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4956 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4957 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4958 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4958 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4960 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4961 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4962 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD4964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD4965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[11].U2_PISO_RAW | PISO_RAW_data_48 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U4_FIFO_RAW_Data | FIFO_36b_512_HD4971 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD4972 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD4973 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4974 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4975 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4976 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4980 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4980 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4982 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4983 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4984 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4985 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4986 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4986 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4988 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4989 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4990 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD4992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD4993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[12].U2_PISO_RAW | PISO_RAW_data_49 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U4_FIFO_RAW_Data | FIFO_36b_512_HD4999 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5000 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5001 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5002 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5003 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5004 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5008 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5008 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5010 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5011 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5012 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5013 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5014 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5014 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5016 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5018 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[13].U2_PISO_RAW | PISO_RAW_data_50 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U4_FIFO_RAW_Data | FIFO_36b_512_HD5027 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5028 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5029 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5030 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5031 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5032 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5036 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5036 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5038 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5039 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5040 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5041 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5042 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5042 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5044 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5045 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5046 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[14].U2_PISO_RAW | PISO_RAW_data_51 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U4_FIFO_RAW_Data | FIFO_36b_512_HD5055 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5056 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5057 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5058 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5059 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5060 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5064 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5064 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5066 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5067 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5068 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5069 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5070 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5070 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5072 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5073 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5074 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[15].U2_PISO_RAW | PISO_RAW_data_52 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U4_FIFO_RAW_Data | FIFO_36b_512_HD5083 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5084 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5085 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5086 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5087 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5088 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5092 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5092 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5095 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5096 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5097 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5098 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5098 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5100 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5101 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5102 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[16].U2_PISO_RAW | PISO_RAW_data_53 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U4_FIFO_RAW_Data | FIFO_36b_512_HD5111 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5112 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5113 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5114 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5115 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5116 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5120 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5120 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5122 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5123 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5124 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5125 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5126 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5126 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5128 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5130 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[17].U2_PISO_RAW | PISO_RAW_data_54 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U4_FIFO_RAW_Data | FIFO_36b_512_HD5139 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5140 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5141 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5142 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5143 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5144 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5148 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5148 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5151 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5152 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5153 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5154 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5154 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5156 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5158 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[18].U2_PISO_RAW | PISO_RAW_data_55 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U4_FIFO_RAW_Data | FIFO_36b_512_HD5167 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5168 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5169 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5170 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5171 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5172 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5176 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5176 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5178 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5179 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5180 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5181 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5182 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5182 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5184 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5185 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5186 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[19].U2_PISO_RAW | PISO_RAW_data_56 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U4_FIFO_RAW_Data | FIFO_36b_512_HD5195 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5196 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5197 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5198 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5199 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5200 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5204 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5204 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5207 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5208 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5209 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5210 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5210 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5213 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5214 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[1].U2_PISO_RAW | PISO_RAW_data_57 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U4_FIFO_RAW_Data | FIFO_36b_512_HD5223 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5224 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5225 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5226 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5227 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5228 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5232 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5232 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5234 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5235 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5236 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5237 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5238 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5238 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5240 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5241 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5242 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[20].U2_PISO_RAW | PISO_RAW_data_58 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U4_FIFO_RAW_Data | FIFO_36b_512_HD5251 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5252 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5253 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5254 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5255 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5256 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5258 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5259 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5260 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5260 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5263 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5264 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5265 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5266 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5266 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5268 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5270 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[21].U2_PISO_RAW | PISO_RAW_data_59 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U4_FIFO_RAW_Data | FIFO_36b_512_HD5279 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5280 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5281 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5282 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5283 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5284 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5288 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5288 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5290 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5291 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5292 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5293 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5294 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5294 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5296 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5298 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[22].U2_PISO_RAW | PISO_RAW_data_60 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U4_FIFO_RAW_Data | FIFO_36b_512_HD5307 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5308 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5309 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5310 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5311 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5312 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5314 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5315 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5316 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5316 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5319 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5320 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5321 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5322 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5322 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5324 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5326 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[23].U2_PISO_RAW | PISO_RAW_data_61 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U4_FIFO_RAW_Data | FIFO_36b_512_HD5335 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5336 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5337 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5338 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5339 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5340 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5344 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5344 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5347 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5348 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5349 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5350 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5350 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5352 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5353 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5354 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[24].U2_PISO_RAW | PISO_RAW_data_62 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U4_FIFO_RAW_Data | FIFO_36b_512_HD5363 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5364 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5365 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5366 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5367 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5368 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5372 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5372 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5374 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5375 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5376 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5377 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5378 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5378 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5380 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5382 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[25].U2_PISO_RAW | PISO_RAW_data_63 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U4_FIFO_RAW_Data | FIFO_36b_512_HD5391 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5392 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5393 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5394 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5395 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5396 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5400 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5400 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5402 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5403 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5404 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5405 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5406 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5406 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5408 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5409 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5410 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[26].U2_PISO_RAW | PISO_RAW_data_64 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U4_FIFO_RAW_Data | FIFO_36b_512_HD5419 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5420 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5421 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5422 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5423 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5424 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5428 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5428 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5430 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5431 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5432 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5433 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5434 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5434 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5436 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5437 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5438 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[27].U2_PISO_RAW | PISO_RAW_data_65 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U4_FIFO_RAW_Data | FIFO_36b_512_HD5447 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5448 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5449 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5450 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5451 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5452 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5456 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5456 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5459 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5460 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5461 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5462 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5462 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5464 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5465 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5466 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[28].U2_PISO_RAW | PISO_RAW_data_66 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U4_FIFO_RAW_Data | FIFO_36b_512_HD5475 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5476 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5477 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5478 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5479 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5480 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5484 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5484 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5486 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5487 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5488 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5489 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5490 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5490 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5492 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5493 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5494 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[29].U2_PISO_RAW | PISO_RAW_data_67 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U4_FIFO_RAW_Data | FIFO_36b_512_HD5503 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5504 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5505 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5506 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5507 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5508 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5512 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5512 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5514 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5515 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5516 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5517 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5518 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5518 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5520 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5521 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5522 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[2].U2_PISO_RAW | PISO_RAW_data_68 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U4_FIFO_RAW_Data | FIFO_36b_512_HD5531 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5532 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5533 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5534 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5535 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5536 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5540 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5540 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5543 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5544 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5545 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5546 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5546 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5548 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5549 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5550 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[30].U2_PISO_RAW | PISO_RAW_data_69 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U4_FIFO_RAW_Data | FIFO_36b_512_HD5559 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5560 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5561 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5562 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5563 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5564 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5568 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5568 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5570 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5571 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5572 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5573 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5574 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5574 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5576 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5577 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5578 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[31].U2_PISO_RAW | PISO_RAW_data_70 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U4_FIFO_RAW_Data | FIFO_36b_512_HD5587 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5588 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5589 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5590 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5591 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5592 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5596 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5596 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5599 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5600 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5601 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5602 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5602 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5604 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5606 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[32].U2_PISO_RAW | PISO_RAW_data_71 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U4_FIFO_RAW_Data | FIFO_36b_512_HD5615 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5616 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5617 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5618 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5619 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5620 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5624 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5624 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5626 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5627 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5628 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5629 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5630 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5630 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5632 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5634 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[33].U2_PISO_RAW | PISO_RAW_data_72 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U4_FIFO_RAW_Data | FIFO_36b_512_HD5643 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5644 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5645 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5646 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5647 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5648 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5652 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5652 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5655 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5656 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5657 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5658 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5658 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5661 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5662 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[34].U2_PISO_RAW | PISO_RAW_data_73 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U4_FIFO_RAW_Data | FIFO_36b_512_HD5671 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5672 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5673 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5674 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5675 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5676 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5680 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5680 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5682 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5683 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5684 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5685 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5686 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5686 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5688 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5690 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[35].U2_PISO_RAW | PISO_RAW_data_74 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U4_FIFO_RAW_Data | FIFO_36b_512_HD5699 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5700 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5701 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5702 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5703 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5704 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5708 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5708 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5710 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5711 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5712 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5713 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5714 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5714 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5716 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5718 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[36].U2_PISO_RAW | PISO_RAW_data_75 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U4_FIFO_RAW_Data | FIFO_36b_512_HD5727 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5728 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5729 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5730 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5731 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5732 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5736 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5736 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5739 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5740 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5741 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5742 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5742 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5744 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5746 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[37].U2_PISO_RAW | PISO_RAW_data_76 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U4_FIFO_RAW_Data | FIFO_36b_512_HD5755 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5756 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5757 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5758 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5759 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5760 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5764 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5764 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5767 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5768 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5769 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5770 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5770 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5772 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5774 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[38].U2_PISO_RAW | PISO_RAW_data_77 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U4_FIFO_RAW_Data | FIFO_36b_512_HD5783 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5784 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5785 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5786 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5787 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5788 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5792 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5792 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5794 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5795 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5796 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5797 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5798 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5798 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5802 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[39].U2_PISO_RAW | PISO_RAW_data_78 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U4_FIFO_RAW_Data | FIFO_36b_512_HD5811 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5812 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5813 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5814 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5815 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5816 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5820 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5820 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5822 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5823 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5824 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5825 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5826 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5826 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5830 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[3].U2_PISO_RAW | PISO_RAW_data_79 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U4_FIFO_RAW_Data | FIFO_36b_512_HD5839 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5840 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5841 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5842 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5843 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5844 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5848 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5848 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5850 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5851 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5852 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5853 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5854 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5854 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5857 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5858 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[40].U2_PISO_RAW | PISO_RAW_data_80 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U4_FIFO_RAW_Data | FIFO_36b_512_HD5867 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5868 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5869 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5870 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5871 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5872 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5876 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5876 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5879 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5880 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5881 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5882 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5882 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5886 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[41].U2_PISO_RAW | PISO_RAW_data_81 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U4_FIFO_RAW_Data | FIFO_36b_512_HD5895 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5896 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5897 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5898 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5899 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5900 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5904 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5904 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5907 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5908 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5909 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5910 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5910 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5913 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5914 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[42].U2_PISO_RAW | PISO_RAW_data_82 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U4_FIFO_RAW_Data | FIFO_36b_512_HD5923 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5924 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5925 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5926 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5927 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5928 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5932 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5932 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5934 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5935 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5936 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5937 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5938 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5938 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5940 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5941 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5942 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[43].U2_PISO_RAW | PISO_RAW_data_83 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U4_FIFO_RAW_Data | FIFO_36b_512_HD5951 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5952 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5953 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5954 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5955 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5956 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5960 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5960 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5962 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5963 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5964 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5965 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5966 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5966 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5968 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5969 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5970 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD5972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD5973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[44].U2_PISO_RAW | PISO_RAW_data_84 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U4_FIFO_RAW_Data | FIFO_36b_512_HD5979 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD5980 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD5981 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5982 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5983 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5984 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5988 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5988 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5991 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5992 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5993 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5994 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5994 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5996 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5997 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5998 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[45].U2_PISO_RAW | PISO_RAW_data_85 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U4_FIFO_RAW_Data | FIFO_36b_512_HD6007 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6008 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6009 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6010 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6011 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6012 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6016 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6016 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6018 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6019 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6020 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6021 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6022 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6022 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6024 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6025 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6026 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[46].U2_PISO_RAW | PISO_RAW_data_86 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U4_FIFO_RAW_Data | FIFO_36b_512_HD6035 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6036 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6037 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6038 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6039 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6040 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6044 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6044 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6047 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6048 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6049 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6050 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6050 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6053 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6054 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[47].U2_PISO_RAW | PISO_RAW_data_87 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U4_FIFO_RAW_Data | FIFO_36b_512_HD6063 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6064 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6065 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6066 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6067 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6068 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6072 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6072 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6074 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6075 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6076 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6077 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6078 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6078 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6081 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6082 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[48].U2_PISO_RAW | PISO_RAW_data_88 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U4_FIFO_RAW_Data | FIFO_36b_512_HD6091 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6092 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6093 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6094 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6095 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6096 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6100 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6100 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6103 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6104 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6105 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6106 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6106 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6109 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6110 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[4].U2_PISO_RAW | PISO_RAW_data_89 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U4_FIFO_RAW_Data | FIFO_36b_512_HD6119 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6120 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6121 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6122 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6123 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6124 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6128 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6128 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6130 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6131 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6132 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6133 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6134 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6134 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6137 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6138 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[5].U2_PISO_RAW | PISO_RAW_data_90 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U4_FIFO_RAW_Data | FIFO_36b_512_HD6147 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6148 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6149 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6150 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6151 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6152 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6156 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6156 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6159 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6160 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6161 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6162 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6162 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6164 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6165 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6166 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[6].U2_PISO_RAW | PISO_RAW_data_91 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U4_FIFO_RAW_Data | FIFO_36b_512_HD6175 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6176 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6177 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6178 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6179 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6180 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6184 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6184 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6186 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6187 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6188 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6189 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6190 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6190 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6194 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[7].U2_PISO_RAW | PISO_RAW_data_92 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U4_FIFO_RAW_Data | FIFO_36b_512_HD6203 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6204 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6205 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6206 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6207 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6208 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6212 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6212 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6214 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6215 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6216 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6217 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6218 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6218 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6221 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6222 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[8].U2_PISO_RAW | PISO_RAW_data_93 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U4_FIFO_RAW_Data | FIFO_36b_512_HD6231 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6232 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6233 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6234 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6235 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6236 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6240 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6240 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6242 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6243 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6244 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6245 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6246 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6246 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6249 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6250 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[9].U2_PISO_RAW | PISO_RAW_data_94 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_4_HD4889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_4_synth_HD4890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U4_FIFO_RAW_Data | FIFO_36b_512_HD6259 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_5_HD6260 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_5_synth_HD6261 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6262 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6263 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6264 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6268 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6268 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6270 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6271 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6272 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6273 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6274 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6274 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6276 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6277 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6278 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_4_HD6280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_4_synth_HD6281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U10_RAW_frame_counter | cntr_up_dn_generic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U10_clk_closs_pulse | clk_closs_pulse_fsm | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_RAW_SPY_mem | ipbus_dpram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_busy_flag_fsm | busy_flag_fsm | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_FIFO_link_err | FIFO_54b_512 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_54b_512_fifo_generator_v13_2_5 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_54b_512_fifo_generator_v13_2_5_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_54b_512_fifo_generator_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbi.bi | FIFO_54b_512_fifo_generator_v13_2_5_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | FIFO_54b_512_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | FIFO_54b_512_builtin_top_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | FIFO_54b_512_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | FIFO_54b_512_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U5_RAW_fsm | fsm_RAW_data_wr_to_DPR | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U5_RAW_fsm) | fsm_RAW_data_wr_to_DPR | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_10b | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_link_err | link_errors_ORed | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5b_gen_full_flag | RAW_fifo_full_flag_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_FIFO_BCN_L1A | FIFO_47b_512 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_5 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_5_synth | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_47b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_4_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_rd_RAW_mux_fsm | fsm_RAW_to_muxPISO | 800(0.23%) | 800(0.23%) | 0(0.00%) | 0(0.00%) | 2086(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U7_rd_RAW_mux_fsm) | fsm_RAW_to_muxPISO | 774(0.22%) | 774(0.22%) | 0(0.00%) | 0(0.00%) | 2074(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_raw_payld_length | cntr_generic__parameterized2 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_RAW_Link_output_FIFO | FIFO_33b_8192 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_5 | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_5_synth | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_33b_8192_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_4 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_4_synth | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_RAW_Link_output_FIFO_FSM | FIFO_to_MGT_RAW_FSM | 54(0.02%) | 54(0.02%) | 0(0.00%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_rdout_ipb_slave | readout_ipb_slave | 511(0.15%) | 511(0.15%) | 0(0.00%) | 0(0.00%) | 961(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U4_rdout_ipb_slave) | readout_ipb_slave | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_Test_Cntl_Reg | ipbus_ctrlreg_v__parameterized2_17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_pulsed_register | ipbus_ctrlreg_v__parameterized2_18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_top_level_counters | ipbus_ctrlreg_v__parameterized4 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_ttc_parity_L1A_BCN | ipbus_ctrlreg_v__parameterized5 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_slave | slave_TOB_readout | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 544(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U11_LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_30 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_31 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U18_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_33 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOB_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_EG_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_35 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_TAU_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_36 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_SLICES_TO_RD | ipbus_ctrlreg_v__parameterized2_37 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_trigger_slice | ipbus_ctrlreg_v__parameterized2_38 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_TOB_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_TOB_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_40 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_41 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_42 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_EG_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_TAU_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_44 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_EG_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_TAU_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_46 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_RAW_slave | slave_RAW_readout | 155(0.04%) | 155(0.04%) | 0(0.00%) | 0(0.00%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U15_RAW_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_19 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_RAW_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_22 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_23 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_Link_output_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_27 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9A_RAW_FIFO_FULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_28 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9B_RAW_FIFO_FULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_29 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | proc_FPGAs | 5971(1.72%) | 5952(1.72%) | 0(0.00%) | 19(0.01%) | 2727(0.39%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_node_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | ipbus_ctrl | 5958(1.72%) | 5939(1.71%) | 0(0.00%) | 19(0.01%) | 2674(0.39%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (U_2) | ipbus_ctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 4443(1.28%) | 4443(1.28%) | 0(0.00%) | 0(0.00%) | 434(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 202(0.06%) | 202(0.06%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 4253(1.23%) | 4253(1.23%) | 0(0.00%) | 0(0.00%) | 299(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 1513(0.44%) | 1494(0.43%) | 0(0.00%) | 19(0.01%) | 2240(0.32%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 194(0.06%) | 193(0.06%) | 0(0.00%) | 1(0.01%) | 224(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 179(0.05%) | 179(0.05%) | 0(0.00%) | 0(0.00%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 108(0.03%) | 92(0.03%) | 0(0.00%) | 16(0.01%) | 353(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 143(0.04%) | 143(0.04%) | 0(0.00%) | 0(0.00%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 235(0.07%) | 235(0.07%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_5 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized1 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_resources | clk_resources | 23(0.01%) | 22(0.01%) | 0(0.00%) | 1(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_resources) | clk_resources | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Inputclk40M | ClockWizard | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | ClockWizard_ClockWizard_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk40_gen | clk_wiz_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_1_clk_wiz_1_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 21(0.01%) | 20(0.01%) | 0(0.00%) | 1(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 4(0.01%) | 3(0.01%) | 0(0.00%) | 1(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | slaves | 518(0.15%) | 518(0.15%) | 0(0.00%) | 0(0.00%) | 1289(0.19%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | bcmuxvalue_sync | ipbus_ctrlreg_v__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 425(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig__0 | ipbus_ctrlreg_v__parameterized2_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32 | 274(0.08%) | 274(0.08%) | 0(0.00%) | 0(0.00%) | 304(0.04%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bc_delay | ipbus_ctrlreg_v__parameterized1_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bus_delay | ipbus_ctrlreg_v__parameterized1_2 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_synch | ipbus_ctrlreg_v__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_orbit_length | ipbus_ctrlreg_v__parameterized2_4 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 152(0.04%) | 152(0.04%) | 0(0.00%) | 0(0.00%) | 367(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 152(0.04%) | 152(0.04%) | 0(0.00%) | 0(0.00%) | 366(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining