*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2602.508 ; gain = 0.000 ; free physical = 28184 ; free virtual = 50535 INFO: [Netlist 29-17] Analyzing 347 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:57] get_clocks: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3221.699 ; gain = 563.164 ; free physical = 27404 ; free virtual = 49786 Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] Finished Parsing XDC File [/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1715] 3 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 28 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3221.699 ; gain = 0.000 ; free physical = 27395 ; free virtual = 49778 INFO: [Project 1-111] Unisim Transformation Summary: A total of 49 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 17 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 3221.699 ; gain = 619.191 ; free physical = 27398 ; free virtual = 49781 source /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.88 . Memory (MB): peak = 3229.703 ; gain = 8.004 ; free physical = 27431 ; free virtual = 49815 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 198db4abe Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.65 . Memory (MB): peak = 3229.703 ; gain = 0.000 ; free physical = 27421 ; free virtual = 49796 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: dbbbd815 Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.86 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 28708 ; free virtual = 51084 INFO: [Opt 31-389] Phase Retarget created 44 cells and removed 344 cells INFO: [Opt 31-1021] In phase Retarget, 184 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 15ce0efe4 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 28717 ; free virtual = 51084 INFO: [Opt 31-389] Phase Constant propagation created 153 cells and removed 436 cells INFO: [Opt 31-1021] In phase Constant propagation, 182 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 1708ce81b Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 28816 ; free virtual = 51183 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 233 cells INFO: [Opt 31-1021] In phase Sweep, 310 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 4 BUFG optimization | Checksum: 12b0a741b Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 28901 ; free virtual = 51268 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 12b0a741b Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 28901 ; free virtual = 51268 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 9aea680f Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 28952 ; free virtual = 51319 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 183 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 44 | 344 | 184 | | Constant propagation | 153 | 436 | 182 | | Sweep | 6 | 233 | 310 | | BUFG optimization | 0 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 183 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3368.703 ; gain = 0.000 ; free physical = 30091 ; free virtual = 52458 Ending Logic Optimization Task | Checksum: d18c9a47 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3368.703 ; gain = 1.000 ; free physical = 30091 ; free virtual = 52458 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 23 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 46 Ending PowerOpt Patch Enables Task | Checksum: 19fef9e2b Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29955 ; free virtual = 52322 Ending Power Optimization Task | Checksum: 19fef9e2b Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 3698.734 ; gain = 330.031 ; free physical = 29960 ; free virtual = 52327 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 33210928 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29637 ; free virtual = 52004 Ending Final Cleanup Task | Checksum: 33210928 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29643 ; free virtual = 52010 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29643 ; free virtual = 52010 Ending Netlist Obfuscation Task | Checksum: 33210928 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29643 ; free virtual = 52010 INFO: [Common 17-83] Releasing license: Implementation 50 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3698.734 ; gain = 477.035 ; free physical = 29643 ; free virtual = 52010 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29121 ; free virtual = 51495 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Coretcl 2-168] The results of DRC are in file /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28497 ; free virtual = 50874 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1974d94d Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28496 ; free virtual = 50874 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28496 ; free virtual = 50874 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d66e643d Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28629 ; free virtual = 50997 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 14aefabe1 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29607 ; free virtual = 51979 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 14aefabe1 Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29603 ; free virtual = 51971 Phase 1 Placer Initialization | Checksum: 14aefabe1 Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29605 ; free virtual = 51973 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1d67a02a2 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29451 ; free virtual = 51819 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 14a0286fa Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 29307 ; free virtual = 51675 Phase 2.3 Global Placement Core Phase 2.3.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 518 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 235 nets or cells. Created 0 new cell, deleted 235 existing cells and moved 0 existing cell INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28155 ; free virtual = 50523 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 235 | 235 | 0 | 1 | 00:00:01 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 235 | 235 | 0 | 3 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1f67b839e Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28123 ; free virtual = 50491 Phase 2.3 Global Placement Core | Checksum: 231544442 Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28034 ; free virtual = 50403 Phase 2 Global Placement | Checksum: 231544442 Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 28032 ; free virtual = 50401 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26482bb8e Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27936 ; free virtual = 50304 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17c666db5 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27936 ; free virtual = 50304 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1e5eb4311 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27936 ; free virtual = 50304 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 14e3790ac Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27936 ; free virtual = 50304 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1e68c68f5 Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27802 ; free virtual = 50170 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1b6bf80c9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27730 ; free virtual = 50098 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 23385443f Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27717 ; free virtual = 50085 Phase 3 Detail Placement | Checksum: 23385443f Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27708 ; free virtual = 50076 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 5f46ce4a Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.891 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 2bb49eeb Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.93 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27294 ; free virtual = 49662 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 7050f12d Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.97 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27287 ; free virtual = 49655 Phase 4.1.1.1 BUFG Insertion | Checksum: 5f46ce4a Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27282 ; free virtual = 49650 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.891. For the most accurate timing information please run report_timing. Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27273 ; free virtual = 49642 Phase 4.1 Post Commit Optimization | Checksum: 9d75f790 Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27270 ; free virtual = 49638 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 9d75f790 Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27265 ; free virtual = 49633 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 9d75f790 Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27258 ; free virtual = 49626 Phase 4.3 Placer Reporting | Checksum: 9d75f790 Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27255 ; free virtual = 49623 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27253 ; free virtual = 49622 Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27253 ; free virtual = 49622 Phase 4 Post Placement Optimization and Clean-Up | Checksum: dbbed81c Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27249 ; free virtual = 49618 Ending Placer Task | Checksum: 94eda1de Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27178 ; free virtual = 49547 INFO: [Common 17-83] Releasing license: Implementation 82 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27203 ; free virtual = 49572 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.66 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27116 ; free virtual = 49501 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.37 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27076 ; free virtual = 49448 INFO: [runtcl-4] Executing : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 27089 ; free virtual = 49462 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 92 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3698.734 ; gain = 0.000 ; free physical = 26860 ; free virtual = 49250 INFO: [Common 17-1381] The checkpoint '/fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Running DRC as a precondition to command route_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Checksum: PlaceDB: 4d3e5f3a ConstDB: 0 ShapeSum: 47af42a4 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1124ced44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 3812.836 ; gain = 114.102 ; free physical = 29088 ; free virtual = 51468 Post Restoration Checksum: NetGraph: 4b44dc36 NumContArr: c708110e Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 1124ced44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 3812.836 ; gain = 114.102 ; free physical = 28750 ; free virtual = 51129 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 1124ced44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 3815.836 ; gain = 117.102 ; free physical = 28642 ; free virtual = 51022 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 1124ced44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 3815.836 ; gain = 117.102 ; free physical = 28625 ; free virtual = 51005 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 20b978364 Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 3883.047 ; gain = 184.312 ; free physical = 27885 ; free virtual = 50266 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=-0.300 | THS=-323.565| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 1c9cf0e1a Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 3883.047 ; gain = 184.312 ; free physical = 27645 ; free virtual = 50025 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1b2cd7118 Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 27645 ; free virtual = 50025 Phase 2 Router Initialization | Checksum: 1433d4d56 Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 27641 ; free virtual = 50021 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 10096 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 10094 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1433d4d56 Time (s): cpu = 00:00:54 ; elapsed = 00:00:55 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 27586 ; free virtual = 49967 Phase 3 Initial Routing | Checksum: 206907bae Time (s): cpu = 00:01:00 ; elapsed = 00:01:01 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26374 ; free virtual = 48756 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 881 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 24ae1b87e Time (s): cpu = 00:01:07 ; elapsed = 00:01:08 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26923 ; free virtual = 49305 Phase 4 Rip-up And Reroute | Checksum: 24ae1b87e Time (s): cpu = 00:01:07 ; elapsed = 00:01:08 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26923 ; free virtual = 49305 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 24ae1b87e Time (s): cpu = 00:01:07 ; elapsed = 00:01:08 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26923 ; free virtual = 49305 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 24ae1b87e Time (s): cpu = 00:01:07 ; elapsed = 00:01:08 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26923 ; free virtual = 49305 Phase 5 Delay and Skew Optimization | Checksum: 24ae1b87e Time (s): cpu = 00:01:07 ; elapsed = 00:01:08 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26923 ; free virtual = 49305 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 23d107592 Time (s): cpu = 00:01:08 ; elapsed = 00:01:09 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26961 ; free virtual = 49343 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.067 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1f6cb5c84 Time (s): cpu = 00:01:08 ; elapsed = 00:01:10 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26961 ; free virtual = 49343 Phase 6 Post Hold Fix | Checksum: 1f6cb5c84 Time (s): cpu = 00:01:08 ; elapsed = 00:01:10 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26961 ; free virtual = 49343 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.541891 % Global Horizontal Routing Utilization = 0.599402 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1a1e47c96 Time (s): cpu = 00:01:09 ; elapsed = 00:01:10 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26961 ; free virtual = 49343 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a1e47c96 Time (s): cpu = 00:01:09 ; elapsed = 00:01:10 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26961 ; free virtual = 49343 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 133769209 Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26935 ; free virtual = 49317 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.067 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 133769209 Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26932 ; free virtual = 49314 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26947 ; free virtual = 49329 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 106 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:15 ; elapsed = 00:01:16 . Memory (MB): peak = 3899.047 ; gain = 200.312 ; free physical = 26947 ; free virtual = 49329 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads source /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.0-71681FB INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_golden_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] The git SHA value 71681fb will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.0-71681FB INFO: [Hog:Msg-0] Creating /fast/gitlab-runner-home/builds/t3_BwBuQ-/1/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_control-v1.7.0-71681FB... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.