## Repository info
- Merge request number: 339
- Branch name: minor_version/new_everything

## MR Description
Combination of !334 and !338


## Changelog

- set Tau version to 2
- connect algo Tau BDT to top generic TAU_ALGO_VERSION
- fix eg version and tau version in infrastructure xml
- add new top generic ALGO_ID_VERSION that is fed to the status register and to the eg TOB
- add version field to eg TOB and resize iut to 2 bits also for Tau
- introduce FastMultiplier and use it for Hadron
- mux and sums are update. Only 16 cells are used for RHad

## efex_control


<p>
<details>
<summary>show/hide</summary> 

 ## efex_control Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.006165       |
| TNS:          | 0.000000       |
| WHS:          | 0.056009       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_control Synthesis Utilization report


                                                                                         
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        --- |         ---  |             ---  |                 
| Slice  LUTs*     |    30074    |   0         |    204000        |    14.74     |       
| Slice  Registers |    51056    |   0         |    408000        |    12.51     |       
| Block  RAM       Tile |        322 |         0    |             750  |         42.93 | 
| DSPs   |         0    |        0   |         1120 |             0.00 |                 
| Bonded IOB       |    404      |   0         |    600           |    67.33     |       
                                                                                         
## efex_control Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    38100    |     0         |    204000        |    18.68     |       
| Slice  Registers |    69615    |     0         |    408000        |    17.06     |       
| Block  RAM       Tile |        364.5 |         0    |             750  |         48.60 | 
| DSPs   |         0    |        0     |         1120 |             0.00 |                 
| Bonded IOB       |    372      |     360       |    600           |    62.00     |       
                                                                                           
## efex_control Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 71681fb        | 1.7.0       |
| Constraints                 | 5c744a9a       | 1.7.0       |
| IPbus XML                   | 4725337        | 1.7.0       |
| Top Directory               | d88faa0        | 0.15.0      |
| Hog                         | 219f277        | 8.15.4      |
| **Lib:** infrastructure_lib | 71681fb        | 1.7.0       |
| **Lib:** ips                | 5e39647        | 1.7.0       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |



</details>
</p>

 
## golden/efex_golden_control


<p>
<details>
<summary>show/hide</summary> 

 ## golden/efex_golden_control Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.150692       |
| TNS:          | 0.000000       |
| WHS:          | 0.067790       |
| THS:          | 0.000000       |


 Time requirements are met.



## golden/efex_golden_control Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    4958     |   0         |    204000        |    2.43      |      
| Slice  Registers |    5290     |   0         |    408000        |    1.30      |      
| Block  RAM       Tile |        22  |         0    |             750  |         2.93 | 
| DSPs   |         0    |        0   |         1120 |             0.00 |                
| Bonded IOB       |    143      |   0         |    600           |    23.83     |      
                                                                                        
## golden/efex_golden_control Implementation Utilization report


                                                                                         
| **Site Type**    |    **Used** |    **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        ---  |         ---  |             ---  |                
| Slice  LUTs      |    5062     |    0         |    204000        |    2.48      |      
| Slice  Registers |    5998     |    0         |    408000        |    1.47      |      
| Block  RAM       Tile |        22.5 |         0    |             750  |         3.00 | 
| DSPs   |         0    |        0    |         1120 |             0.00 |                
| Bonded IOB       |    167      |    155       |    600           |    27.83     |      
                                                                                         
## golden/efex_golden_control Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 71681fb        | 1.7.0       |
| Constraints                 | 2413478e       | 1.6.4       |
| IPbus XML                   | 4725337        | 1.7.0       |
| Top Directory               | 61e9503        | 0.17.0      |
| Hog                         | 219f277        | 8.15.4      |
| **Lib:** infrastructure_lib | 71681fb        | 1.7.0       |
| **Lib:** ips                | 82ffdd0        | 0.8.1       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |



</details>
</p>

 
## efex_processor.1


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.1 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.083790       |
| TNS:          | 0.000000       |
| WHS:          | 0.011437       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.1 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    182226   |   0         |    346400        |    52.61     |      
| Slice  Registers |    248604   |   0         |    692800        |    35.88     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    499      |   0         |    600           |    83.17     |      
                                                                                        
## efex_processor.1 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    189562   |     0         |    346400        |    54.72     |       
| Slice  Registers |    273205   |     0         |    692800        |    39.43     |       
| Block  RAM       Tile |        758.5 |         0    |             1180 |         64.28 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    447      |     447       |    600           |    74.50     |       
                                                                                           
## efex_processor.1 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | c857fdf        | 1.7.0       |
| Constraints                 | c857fdf0       | 1.7.0       |
| IPbus XML                   | 6995bf6        | 1.7.0       |
| Top Directory               | 6fb4826        | 0.14.0      |
| Hog                         | 219f277        | 8.15.4      |
| **Lib:** TOB_rdout_lib      | c2e48ed        | 1.7.0       |
| **Lib:** infrastructure_lib | 5c0a46a        | 1.7.0       |
| **Lib:** ips                | 4038eab        | 1.7.0       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** algolib            | a666257        | 1.7.0       |
| **Lib:** usr_ip             | e4b7ad6        | 1.7.0       |



</details>
</p>

 
## efex_processor.3


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.3 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.044304       |
| TNS:          | 0.000000       |
| WHS:          | 0.013830       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.3 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    178206   |   0         |    346400        |    51.45     |      
| Slice  Registers |    237107   |   0         |    692800        |    34.22     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    501      |   0         |    600           |    83.50     |      
                                                                                        
## efex_processor.3 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    186221   |     0         |    346400        |    53.76     |       
| Slice  Registers |    261705   |     0         |    692800        |    37.77     |       
| Block  RAM       Tile |        747.5 |         0    |             1180 |         63.35 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    251      |     249       |    600           |    41.83     |       
                                                                                           
## efex_processor.3 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 5c0a46a        | 1.7.0       |
| Constraints                 | d4f9ab3b       | 1.7.0       |
| IPbus XML                   | 6995bf6        | 1.7.0       |
| Top Directory               | 544c0a0        | 0.8.0       |
| Hog                         | 219f277        | 8.15.4      |
| **Lib:** TOB_rdout_lib      | c2e48ed        | 1.7.0       |
| **Lib:** algolib            | a666257        | 1.7.0       |
| **Lib:** infrastructure_lib | 5c0a46a        | 1.7.0       |
| **Lib:** ips                | 4038eab        | 1.7.0       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | e4b7ad6        | 1.7.0       |



</details>
</p>

 
## efex_processor.4


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.4 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.035475       |
| TNS:          | 0.000000       |
| WHS:          | 0.015777       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.4 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    178197   |   0         |    346400        |    51.44     |      
| Slice  Registers |    237107   |   0         |    692800        |    34.22     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    501      |   0         |    600           |    83.50     |      
                                                                                        
## efex_processor.4 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    186276   |     0         |    346400        |    53.77     |       
| Slice  Registers |    261993   |     0         |    692800        |    37.82     |       
| Block  RAM       Tile |        747.5 |         0    |             1180 |         63.35 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    251      |     249       |    600           |    41.83     |       
                                                                                           
## efex_processor.4 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | 5c0a46a        | 1.7.0       |
| Constraints                 | c66b0dea       | 1.7.0       |
| IPbus XML                   | 6995bf6        | 1.7.0       |
| Top Directory               | 544c0a0        | 0.8.0       |
| Hog                         | 219f277        | 8.15.4      |
| **Lib:** TOB_rdout_lib      | c2e48ed        | 1.7.0       |
| **Lib:** algolib            | a666257        | 1.7.0       |
| **Lib:** infrastructure_lib | 5c0a46a        | 1.7.0       |
| **Lib:** ips                | 4038eab        | 1.7.0       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | e4b7ad6        | 1.7.0       |



</details>
</p>

 
## efex_processor.2


<p>
<details>
<summary>show/hide</summary> 

 ## efex_processor.2 Timing summary
                                  
| **Parameter** | **value (ns)** |
| ---           | ---            |
| WNS:          | 0.083976       |
| TNS:          | 0.000000       |
| WHS:          | 0.010396       |
| THS:          | 0.000000       |


 Time requirements are met.



## efex_processor.2 Synthesis Utilization report


                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |    **Available** |    **Util%** |      
| ---    |         ---  |        --- |         ---  |             ---  |                
| Slice  LUTs*     |    182259   |   0         |    346400        |    52.62     |      
| Slice  Registers |    248613   |   0         |    692800        |    35.89     |      
| Block  RAM       Tile |        24  |         0    |             1180 |         2.03 | 
| DSPs   |         0    |        0   |         2880 |             0.00 |                
| Bonded IOB       |    499      |   0         |    600           |    83.17     |      
                                                                                        
## efex_processor.2 Implementation Utilization report


                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |    **Available** |    **Util%** |       
| ---    |         ---  |        ---   |         ---  |             ---  |                 
| Slice  LUTs      |    189986   |     0         |    346400        |    54.85     |       
| Slice  Registers |    273217   |     0         |    692800        |    39.44     |       
| Block  RAM       Tile |        758.5 |         0    |             1180 |         64.28 | 
| DSPs   |         96   |        0     |         2880 |             3.33 |                 
| Bonded IOB       |    447      |     447       |    600           |    74.50     |       
                                                                                           
## efex_processor.2 Version Table

| **File set**                | **Commit SHA** | **Version** |
| ---                         | ---            | ---         |
| Global                      | e030ecb        | 1.7.0       |
| Constraints                 | e030ecb9       | 1.7.0       |
| IPbus XML                   | 6995bf6        | 1.7.0       |
| Top Directory               | 544c0a0        | 0.8.0       |
| Hog                         | 219f277        | 8.15.4      |
| **Lib:** TOB_rdout_lib      | c2e48ed        | 1.7.0       |
| **Lib:** algolib            | a666257        | 1.7.0       |
| **Lib:** infrastructure_lib | 5c0a46a        | 1.7.0       |
| **Lib:** ips                | 4038eab        | 1.7.0       |
| **Lib:** ipbus_lib          | d6f4f62        | 1.0.0       |
| **Lib:** usr_ip             | e4b7ad6        | 1.7.0       |



</details>
</p>