Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024 | Date : Wed Apr 2 17:29:33 2025 | Host : runner-w-bkzzvvi-project-27372-concurrent-0-b1ehc2wf running 64-bit Ubuntu 22.04.5 LTS | Command : report_utilization -hierarchical -hierarchical_percentages -file /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.7.1-F1218C8/reports/hierarchical_utilization.txt | Design : top_efex_control | Device : xc7vx330tffg1157-2 | Speed File : -2 | Design State : Routed ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-----------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------+---------------+-------------+-------------+---------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-----------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------+---------------+-------------+-------------+---------------+-------------+-----------+------------+ | top_efex_control | (top) | 38778(19.01%) | 35919(17.61%) | 1440(2.05%) | 1419(2.02%) | 69663(17.07%) | 355(47.33%) | 19(1.27%) | 0(0.00%) | | (top_efex_control) | (top) | 287(0.14%) | 155(0.08%) | 0(0.00%) | 132(0.19%) | 978(0.24%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.MGT_TX_RX | top_mgt_cfpga | 1873(0.92%) | 1866(0.91%) | 0(0.00%) | 7(0.01%) | 3641(0.89%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.MGT_TX_RX) | top_mgt_cfpga | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 272(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_11G2 | mgt11g2_tx_rx_cfpga_gen | 1243(0.61%) | 1243(0.61%) | 0(0.00%) | 0(0.00%) | 2242(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_1quad_Rx_Tx | mgt11g2_tx_rx_cfpga_wrapper__xdcDup__1 | 623(0.31%) | 623(0.31%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_support_i | mgt11g2_tx_rx_cfpga_support__xdcDup__1 | 623(0.31%) | 623(0.31%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (mgt11g2_tx_rx_cfpga_support_i) | mgt11g2_tx_rx_cfpga_support__xdcDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | mgt11g2_tx_rx_cfpga_common_560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | mgt11g2_tx_rx_cfpga_common_reset_561 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_init_i | mgt11g2_tx_rx_cfpga_HD444 | 604(0.30%) | 604(0.30%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | mgt11g2_tx_rx_cfpga_init_HD445 | 604(0.30%) | 604(0.30%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | mgt11g2_tx_rx_cfpga_init_HD445 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_HD446 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_HD446 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_80_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_81_HD448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_HD449 | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_HD449 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_73_HD450 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_74_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_75_HD452 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_76_HD453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_77_HD454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_78_HD455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_79_HD456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN_HD457 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN_HD457 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_62_HD458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_63_HD459 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_HD460 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_64_HD461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_65_HD462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_66_HD463 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_67_HD464 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_68_HD465 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_69_HD466 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_70_HD467 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_71_HD468 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_72_HD469 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_HD470 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_HD470 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_56_HD471 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_57_HD472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_58_HD473 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_59_HD474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_60_HD475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_61_HD476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0_HD477 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0_HD477 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_54_HD478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_55_HD479 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1_HD480 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1_HD480 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_47_HD481 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_48_HD482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_49_HD483 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_50_HD484 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_51_HD485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_52_HD486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_53_HD487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2_HD488 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2_HD488 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_41_HD489 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_42_HD490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_43_HD491 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_44_HD492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_45_HD493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_46_HD494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3_HD495 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3_HD495 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_39_HD496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_40_HD497 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4_HD498 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4_HD498 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_32_HD499 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_33_HD500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_34_HD501 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_35_HD502 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_36_HD503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_37_HD504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_38_HD505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5_HD506 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5_HD506 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_26_HD507 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_27_HD508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_28_HD509 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_29_HD510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_30_HD511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_31_HD512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6_HD513 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6_HD513 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_24_HD514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_25_HD515 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7_HD516 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7_HD516 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_17_HD517 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_18_HD518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_19_HD519 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_20_HD520 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_21_HD521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_22_HD522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_23_HD523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8_HD524 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8_HD524 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_HD525 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_12_HD526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_13_HD527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_14_HD528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_15_HD529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_16_HD530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_multi_gt_HD531 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_HD532 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_9_HD533 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_10_HD534 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_11_HD535 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[1].mgt_1quad_Rx_Tx | mgt11g2_tx_rx_cfpga_wrapper | 620(0.30%) | 620(0.30%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_support_i | mgt11g2_tx_rx_cfpga_support | 620(0.30%) | 620(0.30%) | 0(0.00%) | 0(0.00%) | 1121(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (mgt11g2_tx_rx_cfpga_support_i) | mgt11g2_tx_rx_cfpga_support | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | mgt11g2_tx_rx_cfpga_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | mgt11g2_tx_rx_cfpga_common_reset | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_init_i | mgt11g2_tx_rx_cfpga | 601(0.29%) | 601(0.29%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | mgt11g2_tx_rx_cfpga_init | 601(0.29%) | 601(0.29%) | 0(0.00%) | 0(0.00%) | 1109(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | mgt11g2_tx_rx_cfpga_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_73 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_75 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_76 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | mgt11g2_tx_rx_cfpga_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_63 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | mgt11g2_tx_rx_cfpga_sync_pulse_72 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_56 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_55 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_1 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_47 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_2 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_41 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_40 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 | 68(0.03%) | 68(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_4 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_34 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 | 62(0.03%) | 62(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_5 | 56(0.03%) | 56(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_26 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | mgt11g2_tx_rx_cfpga_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | mgt11g2_tx_rx_cfpga_sync_block_25 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 | 68(0.03%) | 68(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | mgt11g2_tx_rx_cfpga_RX_STARTUP_FSM_7 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | mgt11g2_tx_rx_cfpga_sync_block_19 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | mgt11g2_tx_rx_cfpga_TX_STARTUP_FSM_8 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | mgt11g2_tx_rx_cfpga_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | mgt11g2_tx_rx_cfpga_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | mgt11g2_tx_rx_cfpga_sync_block_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | mgt11g2_tx_rx_cfpga_sync_block_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | mgt11g2_tx_rx_cfpga_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | mgt11g2_tx_rx_cfpga_sync_block_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_multi_gt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_mgt11g2_tx_rx_cfpga_i | mgt11g2_tx_rx_cfpga_GT_11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_6G4 | MGT_quad_gen | 630(0.31%) | 623(0.31%) | 0(0.00%) | 7(0.01%) | 1127(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_quad_Rx_Tx | mgt_tx_rx_6g4_wrapper | 630(0.31%) | 623(0.31%) | 0(0.00%) | 7(0.01%) | 1127(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | MGT_TX_RX_6G4_support | 630(0.31%) | 623(0.31%) | 0(0.00%) | 7(0.01%) | 1127(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | MGT_TX_RX_6G4_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_6G4_init_i | MGT_TX_RX_6G4 | 620(0.30%) | 613(0.30%) | 0(0.00%) | 7(0.01%) | 1115(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | MGT_TX_RX_6G4_init | 620(0.30%) | 613(0.30%) | 0(0.00%) | 7(0.01%) | 1115(0.27%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | MGT_TX_RX_6G4_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_multi_gt | 14(0.01%) | 7(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cpll_railing0_i | MGT_TX_RX_6G4_cpll_railing | 9(0.01%) | 2(0.01%) | 0(0.00%) | 7(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_GT_79 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_GT_80 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_MGT_TX_RX_6G4_i | MGT_TX_RX_6G4_GT_81 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | MGT_TX_RX_6G4_RX_STARTUP_FSM | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | MGT_TX_RX_6G4_RX_STARTUP_FSM | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_70 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_sync_block_71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_sync_block_72 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_73 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | MGT_TX_RX_6G4_TX_MANUAL_PHASE_ALIGN | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | MGT_TX_RX_6G4_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_sync_block_59 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_sync_block_60 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | MGT_TX_RX_6G4_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_sync_block_61 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | MGT_TX_RX_6G4_sync_pulse_63 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | MGT_TX_RX_6G4_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | MGT_TX_RX_6G4_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | MGT_TX_RX_6G4_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | MGT_TX_RX_6G4_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | MGT_TX_RX_6G4_TX_STARTUP_FSM | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | MGT_TX_RX_6G4_TX_STARTUP_FSM | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_53 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_55 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_sync_block_52 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | MGT_TX_RX_6G4_RX_STARTUP_FSM_1 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | MGT_TX_RX_6G4_RX_STARTUP_FSM_1 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_44 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_sync_block_46 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_47 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | MGT_TX_RX_6G4_TX_STARTUP_FSM_2 | 66(0.03%) | 66(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | MGT_TX_RX_6G4_TX_STARTUP_FSM_2 | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_38 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_40 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_sync_block_37 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | MGT_TX_RX_6G4_RX_STARTUP_FSM_4 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | MGT_TX_RX_6G4_RX_STARTUP_FSM_4 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_29 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_sync_block_31 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_32 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | MGT_TX_RX_6G4_TX_STARTUP_FSM_5 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | MGT_TX_RX_6G4_TX_STARTUP_FSM_5 | 59(0.03%) | 59(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_23 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_25 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | MGT_TX_RX_6G4_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | MGT_TX_RX_6G4_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | MGT_TX_RX_6G4_sync_block_22 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | MGT_TX_RX_6G4_RX_STARTUP_FSM_7 | 69(0.03%) | 69(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | MGT_TX_RX_6G4_RX_STARTUP_FSM_7 | 58(0.03%) | 58(0.03%) | 0(0.00%) | 0(0.00%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block_14 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | MGT_TX_RX_6G4_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | MGT_TX_RX_6G4_sync_block_16 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_17 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | MGT_TX_RX_6G4_TX_STARTUP_FSM_8 | 67(0.03%) | 67(0.03%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | MGT_TX_RX_6G4_TX_STARTUP_FSM_8 | 61(0.03%) | 61(0.03%) | 0(0.00%) | 0(0.00%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK | MGT_TX_RX_6G4_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | MGT_TX_RX_6G4_sync_block_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | MGT_TX_RX_6G4_sync_block_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | MGT_TX_RX_6G4_sync_block_11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | MGT_TX_RX_6G4_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | MGT_TX_RX_6G4_sync_block_13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | MGT_TX_RX_6G4_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | MGT_TX_RX_6G4_common_reset | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | MGT_TX_RX_6G4_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.backplane_reg | backplane_registers | 2309(1.13%) | 2309(1.13%) | 0(0.00%) | 0(0.00%) | 6935(1.70%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.backplane_reg) | backplane_registers | 205(0.10%) | 205(0.10%) | 0(0.00%) | 0(0.00%) | 3511(0.86%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[0].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[1].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[2].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_365 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[3].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[4].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[5].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_368 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[6].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_gt_txctl_generate_block[7].aurora_gt_txctl | ipbus_ctrlreg_v__parameterized2_370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_counter | cntr_generic_371 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[0].active_counter_block | cntr_generic_372 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[0].assert_counter_block | cntr_generic_373 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[0].total_counter_block | cntr_generic_374 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[10].active_counter_block | cntr_generic_375 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[10].assert_counter_block | cntr_generic_376 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[10].total_counter_block | cntr_generic_377 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[11].active_counter_block | cntr_generic_378 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[11].assert_counter_block | cntr_generic_379 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[11].total_counter_block | cntr_generic_380 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[12].active_counter_block | cntr_generic_381 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[12].assert_counter_block | cntr_generic_382 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[12].total_counter_block | cntr_generic_383 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[13].active_counter_block | cntr_generic_384 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[13].assert_counter_block | cntr_generic_385 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[13].total_counter_block | cntr_generic_386 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[14].active_counter_block | cntr_generic_387 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[14].assert_counter_block | cntr_generic_388 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[14].total_counter_block | cntr_generic_389 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[15].active_counter_block | cntr_generic_390 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[15].assert_counter_block | cntr_generic_391 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[15].total_counter_block | cntr_generic_392 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[16].active_counter_block | cntr_generic_393 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[16].assert_counter_block | cntr_generic_394 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[16].total_counter_block | cntr_generic_395 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[17].active_counter_block | cntr_generic_396 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[17].assert_counter_block | cntr_generic_397 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[17].total_counter_block | cntr_generic_398 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[18].active_counter_block | cntr_generic_399 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[18].assert_counter_block | cntr_generic_400 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[18].total_counter_block | cntr_generic_401 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[19].active_counter_block | cntr_generic_402 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[19].assert_counter_block | cntr_generic_403 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[19].total_counter_block | cntr_generic_404 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[1].active_counter_block | cntr_generic_405 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[1].assert_counter_block | cntr_generic_406 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[1].total_counter_block | cntr_generic_407 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[20].active_counter_block | cntr_generic_408 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[20].assert_counter_block | cntr_generic_409 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[20].total_counter_block | cntr_generic_410 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[21].active_counter_block | cntr_generic_411 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[21].assert_counter_block | cntr_generic_412 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[21].total_counter_block | cntr_generic_413 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[22].active_counter_block | cntr_generic_414 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[22].assert_counter_block | cntr_generic_415 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[22].total_counter_block | cntr_generic_416 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[23].active_counter_block | cntr_generic_417 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[23].assert_counter_block | cntr_generic_418 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[23].total_counter_block | cntr_generic_419 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[24].active_counter_block | cntr_generic_420 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[24].assert_counter_block | cntr_generic_421 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[24].total_counter_block | cntr_generic_422 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[25].active_counter_block | cntr_generic_423 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[25].assert_counter_block | cntr_generic_424 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[25].total_counter_block | cntr_generic_425 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[26].active_counter_block | cntr_generic_426 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[26].assert_counter_block | cntr_generic_427 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[26].total_counter_block | cntr_generic_428 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[27].active_counter_block | cntr_generic_429 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[27].assert_counter_block | cntr_generic_430 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[27].total_counter_block | cntr_generic_431 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[2].active_counter_block | cntr_generic_432 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[2].assert_counter_block | cntr_generic_433 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[2].total_counter_block | cntr_generic_434 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[3].active_counter_block | cntr_generic_435 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[3].assert_counter_block | cntr_generic_436 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[3].total_counter_block | cntr_generic_437 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[4].active_counter_block | cntr_generic_438 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[4].assert_counter_block | cntr_generic_439 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[4].total_counter_block | cntr_generic_440 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[5].active_counter_block | cntr_generic_441 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[5].assert_counter_block | cntr_generic_442 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[5].total_counter_block | cntr_generic_443 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[6].active_counter_block | cntr_generic_444 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[6].assert_counter_block | cntr_generic_445 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[6].total_counter_block | cntr_generic_446 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[7].active_counter_block | cntr_generic_447 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[7].assert_counter_block | cntr_generic_448 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[7].total_counter_block | cntr_generic_449 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[8].active_counter_block | cntr_generic_450 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[8].assert_counter_block | cntr_generic_451 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[8].total_counter_block | cntr_generic_452 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[9].active_counter_block | cntr_generic_453 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[9].assert_counter_block | cntr_generic_454 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_counter_generate_block[9].total_counter_block | cntr_generic_455 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[0].busy_xoff_status | ipbus_ctrlreg_v__parameterized5 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[10].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_456 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[11].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_457 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[12].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_458 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[13].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_459 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[1].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_460 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[2].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_461 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[3].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_462 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[4].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_463 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[5].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_464 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[6].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_465 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[7].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_466 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[8].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_467 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | busy_xoff_status_generate_block[9].busy_xoff_status | ipbus_ctrlreg_v__parameterized5_468 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | control | ipbus_ctrlreg_v__parameterized4 | 144(0.07%) | 144(0.07%) | 0(0.00%) | 0(0.00%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[0].rod_counter_block | cntr_generic_469 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[1].rod_counter_block | cntr_generic_470 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[2].rod_counter_block | cntr_generic_471 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[3].rod_counter_block | cntr_generic_472 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[4].rod_counter_block | cntr_generic_473 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[5].rod_counter_block | cntr_generic_474 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[6].rod_counter_block | cntr_generic_475 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_counter_generate_block[7].rod_counter_block | cntr_generic_476 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_link_status_generate_block[0].rod_link_status | ipbus_ctrlreg_v__parameterized6 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rod_link_status_generate_block[1].rod_link_status | ipbus_ctrlreg_v__parameterized6_477 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_counter_generate_block[0].ttc_counter_block | cntr_generic_478 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_counter_generate_block[1].ttc_counter_block | cntr_generic_479 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_counter_generate_block[2].ttc_counter_block | cntr_generic_480 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_counter_generate_block[3].ttc_counter_block | cntr_generic_481 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_status | ipbus_ctrlreg_v__parameterized5_482 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.combined_ttc_ila | ila_0 | 722(0.35%) | 594(0.29%) | 0(0.00%) | 128(0.18%) | 1309(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.combined_ttc_ila) | ila_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_16_ila | 722(0.35%) | 594(0.29%) | 0(0.00%) | 128(0.18%) | 1309(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_16_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_16_ila_core | 721(0.35%) | 593(0.29%) | 0(0.00%) | 128(0.18%) | 1303(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_16_ila_core | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_16_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_16_ila_cap_ctrl_legacy | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_16_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_2_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_2_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_2_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_16_ila_cap_addrgen | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_16_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_2_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_16_ila_cap_sample_counter | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_16_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_2_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_2_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_2_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_2_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_29 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_30 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_16_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_16_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_2_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_2_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_2_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_2_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_2_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_25 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_16_ila_register | 466(0.23%) | 465(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_16_ila_register | 248(0.12%) | 247(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_4_reg_p2s | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_4_reg_p2s__parameterized0 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_4_xsdbs | 77(0.04%) | 77(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_4_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_4_reg__parameterized27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_4_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_19 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_4_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_4_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_4_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_4_reg__parameterized11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_24 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_4_reg__parameterized12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_4_reg__parameterized13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_4_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_4_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_4_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_4_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_4_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_4_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_4_reg__parameterized39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_4_reg__parameterized41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_4_reg__parameterized14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_4_reg_p2s__parameterized1 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_4_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_0_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_16_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_16_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_2_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_2_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_16_ila_trigger | 78(0.04%) | 36(0.02%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_16_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_2_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_2_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_16_ila_trig_match | 72(0.04%) | 35(0.02%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_0_ila_v6_2_16_ila_trig_match | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_2_match__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_2_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_2_generic_memrd | 54(0.03%) | 52(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.crc_checker_hub1 | cntrl_crc_checker__1 | 67(0.03%) | 67(0.03%) | 0(0.00%) | 0(0.00%) | 133(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.crc_checker_hub1) | cntrl_crc_checker__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_488 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_sm | ttc_crc_sm_489 | 61(0.03%) | 61(0.03%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.crc_checker_hub2 | cntrl_crc_checker | 67(0.03%) | 67(0.03%) | 0(0.00%) | 0(0.00%) | 133(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.crc_checker_hub2) | cntrl_crc_checker | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 74(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc_sm | ttc_crc_sm | 61(0.03%) | 61(0.03%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.crc_ila_hub1 | ila_1_HD335 | 662(0.32%) | 567(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.crc_ila_hub1) | ila_1_HD335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_16_ila_HD336 | 662(0.32%) | 567(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_16_ila_HD336 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_16_ila_core_HD337 | 661(0.32%) | 566(0.28%) | 0(0.00%) | 95(0.14%) | 1162(0.28%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_16_ila_core_HD337 | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_16_ila_trace_memory_HD338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_9_HD339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_synth_HD340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_top_HD341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr_HD342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width_HD343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper_HD344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy_HD345 | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy_HD345 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_2_cfglut6__parameterized0_HD346 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_2_cfglut7_HD347 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_2_cfglut7__1_HD348 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_16_ila_cap_addrgen_HD349 | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_16_ila_cap_addrgen_HD349 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_2_cfglut6__1_HD350 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_16_ila_cap_sample_counter_HD351 | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_16_ila_cap_sample_counter_HD351 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_2_cfglut4__1_HD352 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_2_cfglut5__1_HD353 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_2_cfglut6_HD354 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_2_match_nodelay__1_HD355 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25_HD356 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25_HD356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26_HD357 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26_HD357 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_27_HD358 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_28_HD359 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_16_ila_cap_window_counter_HD360 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_16_ila_cap_window_counter_HD360 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_2_cfglut4_HD361 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_2_cfglut5_HD362 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_2_cfglut5__2_HD363 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_2_match_nodelay_HD364 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_HD365 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_HD365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_HD366 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_HD366 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_HD367 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_HD368 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_2_match_nodelay__2_HD369 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21_HD370 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22_HD371 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22_HD371 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_23_HD372 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_24_HD373 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_16_ila_register_HD374 | 463(0.23%) | 462(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_16_ila_register_HD374 | 245(0.12%) | 244(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s_HD375 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized0_HD376 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_4_xsdbs_HD377 | 77(0.04%) | 77(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_4_reg__parameterized26_HD378 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_17_HD379 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_4_reg__parameterized27_HD380 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_16_HD381 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_4_reg__parameterized28_HD382 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_15_HD383 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_4_reg__parameterized29_HD384 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_14_HD385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_4_reg__parameterized30_HD386 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_13_HD387 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_4_reg__parameterized31_HD388 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_12_HD389 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_4_reg__parameterized11_HD390 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_20_HD391 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_4_reg__parameterized12_HD392 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized0_HD393 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_4_reg__parameterized13_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_19_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_4_reg__parameterized32_HD396 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_11_HD397 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_4_reg__parameterized33_HD398 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_10_HD399 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_4_reg__parameterized34_HD400 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_HD401 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_4_reg__parameterized35_HD402 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_9_HD403 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_4_reg__parameterized36_HD404 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_8_HD405 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_4_reg__parameterized37_HD406 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_7_HD407 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_4_reg__parameterized39_HD408 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_6_HD409 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_4_reg__parameterized41_HD410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_5_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_4_reg__parameterized44_HD412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_4_reg__parameterized44_HD412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_4_HD413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_4_reg__parameterized14_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_18_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized1_HD416 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_4_reg_stream_HD417 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_HD418 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0_HD419 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0_HD419 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_HD420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_16_ila_reset_ctrl_HD421 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_16_ila_reset_ctrl_HD421 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection_HD422 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__2_HD423 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__3_HD424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__1_HD425 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer_HD426 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection__1_HD427 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_16_ila_trigger_HD428 | 45(0.02%) | 19(0.01%) | 0(0.00%) | 26(0.04%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_16_ila_trigger_HD428 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_2_match_HD429 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_2_match_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_HD430 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_HD430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA_HD431 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA_HD431 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_3_HD432 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_16_ila_trig_match_HD433 | 39(0.02%) | 18(0.01%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_16_ila_trig_match_HD433 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_2_match__parameterized0_HD434 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_2_match__parameterized0_HD434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0_HD435 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0_HD435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized0_HD436 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized0_HD436 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_HD437 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_0_HD438 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_1_HD439 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_2_HD440 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_HD441 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_2_generic_memrd_HD442 | 47(0.02%) | 45(0.02%) | 0(0.00%) | 2(0.01%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub1_axi_stream_fifo | axi_stream_fifo | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (GOLDEN_IF.hub1_axi_stream_fifo) | axi_stream_fifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_stream_fifo_fifo_generator_v13_2_11 | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | axi_stream_fifo_fifo_generator_v13_2_11_synth | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | axi_stream_fifo_fifo_generator_top | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | grf.rf | axi_stream_fifo_fifo_generator_ramfifo | 84(0.04%) | 82(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | axi_stream_fifo_clk_x_pntrs | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | axi_stream_fifo_clk_x_pntrs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | axi_stream_fifo_rd_logic | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | axi_stream_fifo_rd_fwft | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | axi_stream_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | axi_stream_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | axi_stream_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | axi_stream_fifo_rd_bin_cntr | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | axi_stream_fifo_wr_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | axi_stream_fifo_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | axi_stream_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | axi_stream_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | axi_stream_fifo_wr_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | axi_stream_fifo_memory | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 81(0.02%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | axi_stream_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | axi_stream_fifo_blk_mem_gen_v8_4_9 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | axi_stream_fifo_blk_mem_gen_v8_4_9_synth | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_stream_fifo_blk_mem_gen_top | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | valid.cstr | axi_stream_fifo_blk_mem_gen_generic_cstr | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | axi_stream_fifo_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[1].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[2].ram.r) | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | axi_stream_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | axi_stream_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | axi_stream_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | axi_stream_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub1_ufc_block | ufc_controller__1 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub2_axi_stream_fifo | axi_stream_fifo | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (GOLDEN_IF.hub2_axi_stream_fifo) | axi_stream_fifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | axi_stream_fifo_fifo_generator_v13_2_11 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | axi_stream_fifo_fifo_generator_v13_2_11_synth | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | axi_stream_fifo_fifo_generator_top | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | grf.rf | axi_stream_fifo_fifo_generator_ramfifo | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 255(0.06%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | axi_stream_fifo_clk_x_pntrs | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | axi_stream_fifo_clk_x_pntrs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | axi_stream_fifo_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | axi_stream_fifo_rd_logic | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | axi_stream_fifo_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | axi_stream_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | axi_stream_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | axi_stream_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | axi_stream_fifo_rd_bin_cntr | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | axi_stream_fifo_wr_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | axi_stream_fifo_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | axi_stream_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | axi_stream_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | axi_stream_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | axi_stream_fifo_wr_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | axi_stream_fifo_memory | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 81(0.02%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | axi_stream_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | axi_stream_fifo_blk_mem_gen_v8_4_9 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | axi_stream_fifo_blk_mem_gen_v8_4_9_synth | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | axi_stream_fifo_blk_mem_gen_top | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | valid.cstr | axi_stream_fifo_blk_mem_gen_generic_cstr | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 2(0.27%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | axi_stream_fifo_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[1].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[2].ram.r) | axi_stream_fifo_blk_mem_gen_prim_width__parameterized1 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | axi_stream_fifo_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | axi_stream_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | axi_stream_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | axi_stream_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | axi_stream_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | axi_stream_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.hub2_ufc_block | ufc_controller | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.mgt_slaves | mgt_cntrl_slaves | 1298(0.64%) | 1298(0.64%) | 0(0.00%) | 0(0.00%) | 976(0.24%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.mgt_slaves) | mgt_cntrl_slaves | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fabric | ipbus_fabric_sel__parameterized3 | 55(0.03%) | 55(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | quad_0 | cntrl_mgt_quad_slaves | 397(0.19%) | 397(0.19%) | 0(0.00%) | 0(0.00%) | 348(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (quad_0) | cntrl_mgt_quad_slaves | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information_536 | 83(0.04%) | 83(0.04%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_556 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_557 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_558 | 41(0.02%) | 41(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter_559 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information_537 | 91(0.04%) | 91(0.04%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_552 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_553 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_554 | 49(0.02%) | 49(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter_555 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information_538 | 61(0.03%) | 61(0.03%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_549 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_550 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_551 | 36(0.02%) | 36(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information_539 | 68(0.03%) | 68(0.03%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_546 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_547 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_548 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_540 | 31(0.02%) | 31(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_541 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_542 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_543 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_544 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_545 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | quad_1 | cntrl_mgt_quad_slaves__parameterized0 | 422(0.21%) | 422(0.21%) | 0(0.00%) | 0(0.00%) | 314(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (quad_1) | cntrl_mgt_quad_slaves__parameterized0 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information_514 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_533 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_534 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_535 | 41(0.02%) | 41(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information_515 | 98(0.05%) | 98(0.05%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_530 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_531 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_532 | 57(0.03%) | 57(0.03%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information_516 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_527 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_528 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_529 | 41(0.02%) | 41(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information_517 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_524 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_525 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_526 | 41(0.02%) | 41(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_518 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_519 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_520 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_521 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_522 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_523 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | quad_2 | cntrl_mgt_quad_slaves__parameterized1 | 421(0.21%) | 421(0.21%) | 0(0.00%) | 0(0.00%) | 314(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (quad_2) | cntrl_mgt_quad_slaves__parameterized1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_511 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_512 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_513 | 41(0.02%) | 41(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information_495 | 91(0.04%) | 91(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_508 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_509 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_510 | 50(0.02%) | 50(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information_496 | 89(0.04%) | 89(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter_505 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_506 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_507 | 48(0.02%) | 48(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information_497 | 81(0.04%) | 81(0.04%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter_503 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter_504 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_498 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_499 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_500 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_501 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_502 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.output_channel1_ila | ila_0_HD2 | 722(0.35%) | 594(0.29%) | 0(0.00%) | 128(0.18%) | 1309(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.output_channel1_ila) | ila_0_HD2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_16_ila_HD3 | 722(0.35%) | 594(0.29%) | 0(0.00%) | 128(0.18%) | 1309(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_16_ila_HD3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_16_ila_core_HD4 | 721(0.35%) | 593(0.29%) | 0(0.00%) | 128(0.18%) | 1303(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_16_ila_core_HD4 | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_16_ila_trace_memory_HD5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_9_HD6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_9_synth_HD7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_top_HD8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr_HD9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width_HD10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper_HD11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width__parameterized0_HD12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper__parameterized0_HD13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_16_ila_cap_ctrl_legacy_HD14 | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_16_ila_cap_ctrl_legacy_HD14 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_2_cfglut6__parameterized0_HD15 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_2_cfglut7_HD16 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_2_cfglut7__1_HD17 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_16_ila_cap_addrgen_HD18 | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_16_ila_cap_addrgen_HD18 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_2_cfglut6__1_HD19 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_16_ila_cap_sample_counter_HD20 | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_16_ila_cap_sample_counter_HD20 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_2_cfglut4__1_HD21 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_2_cfglut5__1_HD22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_2_cfglut6_HD23 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_2_match_nodelay__1_HD24 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_29_HD25 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_29_HD25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_30_HD26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_30_HD26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_31_HD27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_32_HD28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_16_ila_cap_window_counter_HD29 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_16_ila_cap_window_counter_HD29 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_2_cfglut4_HD30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_2_cfglut5_HD31 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_2_cfglut5__2_HD32 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_2_match_nodelay_HD33 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_HD34 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_HD34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_HD35 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_HD35 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_HD36 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_HD37 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_2_match_nodelay__2_HD38 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_25_HD39 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_25_HD39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_26_HD40 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_26_HD40 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_27_HD41 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_28_HD42 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_16_ila_register_HD43 | 466(0.23%) | 465(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_16_ila_register_HD43 | 248(0.12%) | 247(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_4_reg_p2s_HD44 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_4_reg_p2s__parameterized0_HD45 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_4_xsdbs_HD46 | 77(0.04%) | 77(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_4_reg__parameterized26_HD47 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_21_HD48 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_4_reg__parameterized27_HD49 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_20_HD50 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_4_reg__parameterized28_HD51 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_19_HD52 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_4_reg__parameterized29_HD53 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_18_HD54 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_4_reg__parameterized30_HD55 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_17_HD56 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_4_reg__parameterized31_HD57 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_16_HD58 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_4_reg__parameterized11_HD59 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_24_HD60 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_4_reg__parameterized12_HD61 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized0_HD62 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_4_reg__parameterized13_HD63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_23_HD64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_4_reg__parameterized32_HD65 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_15_HD66 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_4_reg__parameterized33_HD67 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_14_HD68 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_4_reg__parameterized34_HD69 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_HD70 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_4_reg__parameterized35_HD71 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_13_HD72 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_4_reg__parameterized36_HD73 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_12_HD74 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_4_reg__parameterized37_HD75 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_11_HD76 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_4_reg__parameterized39_HD77 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_10_HD78 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_4_reg__parameterized41_HD79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_9_HD80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_4_reg__parameterized44_HD81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_4_reg__parameterized44_HD81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_8_HD82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_4_reg__parameterized14_HD83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_22_HD84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_4_reg_p2s__parameterized1_HD85 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_4_reg_stream_HD86 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_HD87 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_4_reg_stream__parameterized0_HD88 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_0_xsdbs_v1_0_4_reg_stream__parameterized0_HD88 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_HD89 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_16_ila_reset_ctrl_HD90 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_16_ila_reset_ctrl_HD90 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_2_rising_edge_detection_HD91 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__2_HD92 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__3_HD93 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__1_HD94 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer_HD95 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_2_rising_edge_detection__1_HD96 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_16_ila_trigger_HD97 | 78(0.04%) | 36(0.02%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_16_ila_trigger_HD97 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_2_match_HD98 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_2_match_HD98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_HD99 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_HD99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA_HD100 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA_HD100 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice_7_HD101 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_16_ila_trig_match_HD102 | 72(0.04%) | 35(0.02%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_0_ila_v6_2_16_ila_trig_match_HD102 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_2_match__parameterized0_HD103 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_2_match__parameterized0_HD103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA__parameterized0_HD104 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA__parameterized0_HD104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized0_HD105 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized0_HD105 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_HD106 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_0_HD107 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_1_HD108 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_2_HD109 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_3_HD110 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_4_HD111 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_5_HD112 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_6_HD113 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice_HD114 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_2_generic_memrd_HD115 | 54(0.03%) | 52(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.output_channel2_ila | ila_0 | 721(0.35%) | 593(0.29%) | 0(0.00%) | 128(0.18%) | 1309(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.output_channel2_ila) | ila_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_0_ila_v6_2_16_ila | 721(0.35%) | 593(0.29%) | 0(0.00%) | 128(0.18%) | 1309(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_0_ila_v6_2_16_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_0_ila_v6_2_16_ila_core | 720(0.35%) | 592(0.29%) | 0(0.00%) | 128(0.18%) | 1303(0.32%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_0_ila_v6_2_16_ila_core | 36(0.02%) | 0(0.00%) | 0(0.00%) | 36(0.05%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_0_ila_v6_2_16_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_0_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_0_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_0_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_0_ila_v6_2_16_ila_cap_ctrl_legacy | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_0_ila_v6_2_16_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_0_ltlib_v1_0_2_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_0_ltlib_v1_0_2_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_0_ltlib_v1_0_2_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_0_ila_v6_2_16_ila_cap_addrgen | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_0_ila_v6_2_16_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_0_ltlib_v1_0_2_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_0_ila_v6_2_16_ila_cap_sample_counter | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_0_ila_v6_2_16_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_0_ltlib_v1_0_2_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_0_ltlib_v1_0_2_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_0_ltlib_v1_0_2_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_0_ltlib_v1_0_2_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_29 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_30 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_30 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_31 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_32 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_0_ila_v6_2_16_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_0_ila_v6_2_16_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_0_ltlib_v1_0_2_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_0_ltlib_v1_0_2_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_0_ltlib_v1_0_2_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_0_ltlib_v1_0_2_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_0_ltlib_v1_0_2_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_25 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA_nodelay_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized1_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized2_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_0_ila_v6_2_16_ila_register | 465(0.23%) | 464(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_0_ila_v6_2_16_ila_register | 248(0.12%) | 247(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_0_xsdbs_v1_0_4_reg_p2s | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_0_xsdbs_v1_0_4_reg_p2s__parameterized0 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_0_xsdbs_v1_0_4_xsdbs | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_0_xsdbs_v1_0_4_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_21 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_0_xsdbs_v1_0_4_reg__parameterized27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_0_xsdbs_v1_0_4_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_19 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_0_xsdbs_v1_0_4_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_18 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_0_xsdbs_v1_0_4_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_0_xsdbs_v1_0_4_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_0_xsdbs_v1_0_4_reg__parameterized11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_24 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_0_xsdbs_v1_0_4_reg__parameterized12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_0_xsdbs_v1_0_4_reg__parameterized13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_0_xsdbs_v1_0_4_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_0_xsdbs_v1_0_4_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_0_xsdbs_v1_0_4_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_0_xsdbs_v1_0_4_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_0_xsdbs_v1_0_4_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_0_xsdbs_v1_0_4_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_0_xsdbs_v1_0_4_reg__parameterized39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_0_xsdbs_v1_0_4_reg__parameterized41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_0_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_0_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_0_xsdbs_v1_0_4_reg__parameterized14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_0_xsdbs_v1_0_4_reg_p2s__parameterized1 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_0_xsdbs_v1_0_4_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_0_xsdbs_v1_0_4_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_0_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_0_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_0_xsdbs_v1_0_4_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_0_ila_v6_2_16_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_0_ila_v6_2_16_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_0_ltlib_v1_0_2_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_0_ltlib_v1_0_2_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_0_ltlib_v1_0_2_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_0_ila_v6_2_16_ila_trigger | 78(0.04%) | 36(0.02%) | 0(0.00%) | 42(0.06%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_0_ila_v6_2_16_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_0_ltlib_v1_0_2_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_0_ltlib_v1_0_2_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice_7 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_0_ila_v6_2_16_ila_trig_match | 72(0.04%) | 35(0.02%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_0_ila_v6_2_16_ila_trig_match | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_0_ltlib_v1_0_2_match__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 142(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_0_ltlib_v1_0_2_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_0_ltlib_v1_0_2_allx_typeA__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 141(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_0_ltlib_v1_0_2_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 140(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_0_ltlib_v1_0_2_all_typeA__parameterized0 | 37(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_0_ltlib_v1_0_2_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[5].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_4 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[6].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_5 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[7].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice__parameterized0_6 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[8].U_ALL_SRL_SLICE | ila_0_ltlib_v1_0_2_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_0_ltlib_v1_0_2_generic_memrd | 54(0.03%) | 52(0.03%) | 0(0.00%) | 2(0.01%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.readout_packet_block | packet_block | 22128(10.85%) | 20179(9.89%) | 1320(1.88%) | 629(0.90%) | 41870(10.26%) | 322(42.93%) | 16(1.07%) | 0(0.00%) | | (GOLDEN_IF.readout_packet_block) | packet_block | 253(0.12%) | 252(0.12%) | 0(0.00%) | 1(0.01%) | 158(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].MGT_object | mgt_buffer__parameterized7 | 317(0.16%) | 315(0.15%) | 0(0.00%) | 2(0.01%) | 750(0.18%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[0].MGT_object) | mgt_buffer__parameterized7 | 49(0.02%) | 49(0.02%) | 0(0.00%) | 0(0.00%) | 283(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver | 186(0.09%) | 186(0.09%) | 0(0.00%) | 0(0.00%) | 249(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD666 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11_HD667 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth_HD668 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD669 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD670 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD671 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD671 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray_HD672 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2_HD673 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD674 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD675 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD676 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1_HD677 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2_HD678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD679 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD680 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD681 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD681 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD684 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD685 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9_HD686 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth_HD687 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD688 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD689 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD690 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD690 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD692 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD692 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2_HD694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_A | packet_fifo | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_B | packet_fifo_25 | 171(0.08%) | 105(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_reset_block | packet_fifo_reset_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_fifo_selector | fifo_selector | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[0].raw_ram_fifo | packet_ram_fifo__parameterized3 | 160(0.08%) | 160(0.08%) | 0(0.00%) | 0(0.00%) | 218(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Bulk_sources[1].MGT_object | mgt_buffer__parameterized9 | 304(0.15%) | 302(0.15%) | 0(0.00%) | 2(0.01%) | 751(0.18%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[1].MGT_object) | mgt_buffer__parameterized9 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 283(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized1 | 175(0.09%) | 175(0.09%) | 0(0.00%) | 0(0.00%) | 250(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD697 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11_HD698 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth_HD699 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD700 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD701 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD702 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD702 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray_HD703 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2_HD704 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD705 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD706 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD707 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1_HD708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2_HD709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD710 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD711 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD715 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD716 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9_HD717 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth_HD718 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD719 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD720 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD721 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD721 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD723 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD723 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2_HD725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_A | packet_fifo_26 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_B | packet_fifo_27 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_reset_block | packet_fifo_reset_block_28 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_fifo_selector | fifo_selector_29 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[1].raw_ram_fifo | packet_ram_fifo__parameterized3_30 | 160(0.08%) | 160(0.08%) | 0(0.00%) | 0(0.00%) | 220(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Bulk_sources[2].MGT_object | mgt_buffer__parameterized11 | 335(0.16%) | 333(0.16%) | 0(0.00%) | 2(0.01%) | 751(0.18%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[2].MGT_object) | mgt_buffer__parameterized11 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 283(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_352 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized3 | 172(0.08%) | 172(0.08%) | 0(0.00%) | 0(0.00%) | 250(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD573 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11_HD574 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth_HD575 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD576 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD577 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD578 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD578 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray_HD579 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2_HD580 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD581 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD582 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1_HD584 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2_HD585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD586 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD587 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD588 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD588 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD590 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD591 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD592 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9_HD593 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth_HD594 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD595 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD596 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD597 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD597 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD599 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD599 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2_HD601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_A | packet_fifo_31 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_B | packet_fifo_32 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_reset_block | packet_fifo_reset_block_33 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_fifo_selector | fifo_selector_34 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[2].raw_ram_fifo | packet_ram_fifo__parameterized3_35 | 157(0.08%) | 157(0.08%) | 0(0.00%) | 0(0.00%) | 216(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Bulk_sources[3].MGT_object | mgt_buffer__parameterized13 | 300(0.15%) | 298(0.15%) | 0(0.00%) | 2(0.01%) | 751(0.18%) | 3(0.40%) | 0(0.00%) | 0(0.00%) | | (Bulk_sources[3].MGT_object) | mgt_buffer__parameterized13 | 47(0.02%) | 47(0.02%) | 0(0.00%) | 0(0.00%) | 283(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized5 | 171(0.08%) | 171(0.08%) | 0(0.00%) | 0(0.00%) | 250(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 217(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 43(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_A | packet_fifo_36 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_B | packet_fifo_37 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_reset_block | packet_fifo_reset_block_38 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_fifo_selector | fifo_selector_39 | 77(0.04%) | 77(0.04%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Bulk_sources[3].raw_ram_fifo | packet_ram_fifo__parameterized3_40 | 154(0.08%) | 154(0.08%) | 0(0.00%) | 0(0.00%) | 215(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | IPBusblock | packet_status_block | 4760(2.33%) | 4760(2.33%) | 0(0.00%) | 0(0.00%) | 16340(4.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (IPBusblock) | packet_status_block | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 1346(0.33%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_rdout_ipb_slave | rdout_ipb_slave | 2839(1.39%) | 2839(1.39%) | 0(0.00%) | 0(0.00%) | 8419(2.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_rdout_ipb_slave) | rdout_ipb_slave | 211(0.10%) | 211(0.10%) | 0(0.00%) | 0(0.00%) | 7907(1.94%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | control_registers | ipbus_ctrlreg_v__parameterized3_309 | 101(0.05%) | 101(0.05%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_control | ipbus_ctrlreg_v__parameterized10 | 468(0.23%) | 468(0.23%) | 0(0.00%) | 0(0.00%) | 384(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[0].fifo_status | ipbus_ctrlreg_v__parameterized8 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[10].fifo_status | ipbus_ctrlreg_v__parameterized8_310 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[11].fifo_status | ipbus_ctrlreg_v__parameterized8_311 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[12].fifo_status | ipbus_ctrlreg_v__parameterized8_312 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[13].fifo_status | ipbus_ctrlreg_v__parameterized8_313 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[14].fifo_status | ipbus_ctrlreg_v__parameterized8_314 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[15].fifo_status | ipbus_ctrlreg_v__parameterized8_315 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[1].fifo_status | ipbus_ctrlreg_v__parameterized8_316 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[2].fifo_status | ipbus_ctrlreg_v__parameterized8_317 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[3].fifo_status | ipbus_ctrlreg_v__parameterized8_318 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[4].fifo_status | ipbus_ctrlreg_v__parameterized8_319 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[5].fifo_status | ipbus_ctrlreg_v__parameterized8_320 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[6].fifo_status | ipbus_ctrlreg_v__parameterized8_321 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[7].fifo_status | ipbus_ctrlreg_v__parameterized8_322 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[8].fifo_status | ipbus_ctrlreg_v__parameterized8_323 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo_status_generate_block[9].fifo_status | ipbus_ctrlreg_v__parameterized8_324 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[0].merger_channel_status | ipbus_ctrlreg_v__parameterized9 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[1].merger_channel_status | ipbus_ctrlreg_v__parameterized9_325 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[2].merger_channel_status | ipbus_ctrlreg_v__parameterized9_326 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[3].merger_channel_status | ipbus_ctrlreg_v__parameterized9_327 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[4].merger_channel_status | ipbus_ctrlreg_v__parameterized9_328 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[5].merger_channel_status | ipbus_ctrlreg_v__parameterized9_329 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[6].merger_channel_status | ipbus_ctrlreg_v__parameterized9_330 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_channel_status_generate_block[7].merger_channel_status | ipbus_ctrlreg_v__parameterized9_331 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_overall_status_generate_block[0].merger_overall_status | ipbus_ctrlreg_v__parameterized0 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | merger_overall_status_generate_block[1].merger_overall_status | ipbus_ctrlreg_v__parameterized0_332 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[0].mgt_status | ipbus_ctrlreg_v__parameterized7 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[1].mgt_status | ipbus_ctrlreg_v__parameterized7_333 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[2].mgt_status | ipbus_ctrlreg_v__parameterized7_334 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[3].mgt_status | ipbus_ctrlreg_v__parameterized7_335 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[4].mgt_status | ipbus_ctrlreg_v__parameterized7_336 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[5].mgt_status | ipbus_ctrlreg_v__parameterized7_337 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[6].mgt_status | ipbus_ctrlreg_v__parameterized7_338 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_status_generate_block[7].mgt_status | ipbus_ctrlreg_v__parameterized7_339 | 64(0.03%) | 64(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[0].mux_channel_status | ipbus_ctrlreg_v__parameterized9_340 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[10].mux_channel_status | ipbus_ctrlreg_v__parameterized9_341 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[11].mux_channel_status | ipbus_ctrlreg_v__parameterized9_342 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[1].mux_channel_status | ipbus_ctrlreg_v__parameterized9_343 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[2].mux_channel_status | ipbus_ctrlreg_v__parameterized9_344 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[3].mux_channel_status | ipbus_ctrlreg_v__parameterized9_345 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[4].mux_channel_status | ipbus_ctrlreg_v__parameterized9_346 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[5].mux_channel_status | ipbus_ctrlreg_v__parameterized9_347 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[6].mux_channel_status | ipbus_ctrlreg_v__parameterized9_348 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[7].mux_channel_status | ipbus_ctrlreg_v__parameterized9_349 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[8].mux_channel_status | ipbus_ctrlreg_v__parameterized9_350 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mux_channel_status_generate_block[9].mux_channel_status | ipbus_ctrlreg_v__parameterized9_351 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rdout_err_cnt | rdout_err_cnt | 900(0.44%) | 900(0.44%) | 0(0.00%) | 0(0.00%) | 2880(0.71%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U2_rdout_err_cnt) | rdout_err_cnt | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U2_tob_fifo_error_A | cntr_generic_219 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U3_tob_fifo_error_B | cntr_generic_220 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[0].U4_raw_fifo_error | cntr_generic_221 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U2_tob_fifo_error_A | cntr_generic_222 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U3_tob_fifo_error_B | cntr_generic_223 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[1].U4_raw_fifo_error | cntr_generic_224 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U2_tob_fifo_error_A | cntr_generic_225 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U3_tob_fifo_error_B | cntr_generic_226 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[2].U4_raw_fifo_error | cntr_generic_227 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U2_tob_fifo_error_A | cntr_generic_228 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U3_tob_fifo_error_B | cntr_generic_229 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_1[3].U4_raw_fifo_error | cntr_generic_230 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[0].U5_merged_fifo_error_A | cntr_generic_231 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[0].U6_merged_fifo_error_B | cntr_generic_232 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[1].U5_merged_fifo_error_A | cntr_generic_233 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_2[1].U6_merged_fifo_error_B | cntr_generic_234 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U2_TOB_packet_merged_A | cntr_generic_235 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U3_TOB_packet_missing_A | cntr_generic_236 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U4_debug_packet_created_A | cntr_generic_237 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U5_TOB_packet_merged_B | cntr_generic_238 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U6_TOB_packet_missing_B | cntr_generic_239 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].U7_debug_packet_created_B | cntr_generic_240 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U2_TOB_packet_merged_A | cntr_generic_241 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U3_TOB_packet_missing_A | cntr_generic_242 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U4_debug_packet_created_A | cntr_generic_243 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U5_TOB_packet_merged_B | cntr_generic_244 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U6_TOB_packet_missing_B | cntr_generic_245 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].U7_debug_packet_created_B | cntr_generic_246 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U2_TOB_packet_merged_A | cntr_generic_247 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U3_TOB_packet_missing_A | cntr_generic_248 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U4_debug_packet_created_A | cntr_generic_249 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U5_TOB_packet_merged_B | cntr_generic_250 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U6_TOB_packet_missing_B | cntr_generic_251 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].U7_debug_packet_created_B | cntr_generic_252 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U2_TOB_packet_merged_A | cntr_generic_253 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U3_TOB_packet_missing_A | cntr_generic_254 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U4_debug_packet_created_A | cntr_generic_255 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U5_TOB_packet_merged_B | cntr_generic_256 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U6_TOB_packet_missing_B | cntr_generic_257 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].U7_debug_packet_created_B | cntr_generic_258 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].raw_mgt_length_err | cntr_generic_259 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].raw_mgt_packet_err | cntr_generic_260 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].raw_mgt_packet_received | cntr_generic_261 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].raw_mgt_safe_mode | cntr_generic_262 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].tob_mgt_bcn_err | cntr_generic_263 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].tob_mgt_length_err | cntr_generic_264 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].tob_mgt_packet_err | cntr_generic_265 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].tob_mgt_packet_received | cntr_generic_266 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].tob_mgt_safe_mode | cntr_generic_267 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].raw_mgt_length_err | cntr_generic_268 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].raw_mgt_packet_err | cntr_generic_269 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].raw_mgt_packet_received | cntr_generic_270 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].raw_mgt_safe_mode | cntr_generic_271 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].tob_mgt_bcn_err | cntr_generic_272 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].tob_mgt_length_err | cntr_generic_273 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].tob_mgt_packet_err | cntr_generic_274 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].tob_mgt_packet_received | cntr_generic_275 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].tob_mgt_safe_mode | cntr_generic_276 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].raw_mgt_length_err | cntr_generic_277 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].raw_mgt_packet_err | cntr_generic_278 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].raw_mgt_packet_received | cntr_generic_279 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].raw_mgt_safe_mode | cntr_generic_280 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].tob_mgt_bcn_err | cntr_generic_281 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].tob_mgt_length_err | cntr_generic_282 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].tob_mgt_packet_err | cntr_generic_283 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].tob_mgt_packet_received | cntr_generic_284 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].tob_mgt_safe_mode | cntr_generic_285 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].raw_mgt_length_err | cntr_generic_286 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].raw_mgt_packet_err | cntr_generic_287 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].raw_mgt_packet_received | cntr_generic_288 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].raw_mgt_safe_mode | cntr_generic_289 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].tob_mgt_bcn_err | cntr_generic_290 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].tob_mgt_length_err | cntr_generic_291 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].tob_mgt_packet_err | cntr_generic_292 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].tob_mgt_packet_received | cntr_generic_293 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].tob_mgt_safe_mode | cntr_generic_294 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[0].mux_a_pkt_cnt | cntr_generic_295 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[0].mux_b_pkt_cnt | cntr_generic_296 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[1].mux_a_pkt_cnt | cntr_generic_297 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[1].mux_b_pkt_cnt | cntr_generic_298 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[2].mux_a_pkt_cnt | cntr_generic_299 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[2].mux_b_pkt_cnt | cntr_generic_300 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[3].mux_a_pkt_cnt | cntr_generic_301 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[3].mux_b_pkt_cnt | cntr_generic_302 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[4].mux_a_pkt_cnt | cntr_generic_303 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[4].mux_b_pkt_cnt | cntr_generic_304 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[5].mux_a_pkt_cnt | cntr_generic_305 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_5[5].mux_b_pkt_cnt | cntr_generic_306 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1A_cnt_merger_A_block | cntr_generic_307 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | L1A_cnt_merger_B_block | cntr_generic_308 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_monitoring_block | rdout_monitor | 861(0.42%) | 861(0.42%) | 0(0.00%) | 0(0.00%) | 3059(0.75%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U3_monitoring_block) | rdout_monitor | 42(0.02%) | 42(0.02%) | 0(0.00%) | 0(0.00%) | 168(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].busy_active_count | cntr_generic__parameterized0 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].busy_assert_counter | cntr_generic | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[0].busy_count | cntr_generic__parameterized0_136 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[10].busy_active_count | cntr_generic__parameterized0_137 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[10].busy_assert_counter | cntr_generic_138 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[10].busy_count | cntr_generic__parameterized0_139 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[11].busy_active_count | cntr_generic__parameterized0_140 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[11].busy_assert_counter | cntr_generic_141 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[11].busy_count | cntr_generic__parameterized0_142 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].busy_active_count | cntr_generic__parameterized0_143 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].busy_assert_counter | cntr_generic_144 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[1].busy_count | cntr_generic__parameterized0_145 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].busy_active_count | cntr_generic__parameterized0_146 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].busy_assert_counter | cntr_generic_147 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[2].busy_count | cntr_generic__parameterized0_148 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].busy_active_count | cntr_generic__parameterized0_149 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].busy_assert_counter | cntr_generic_150 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[3].busy_count | cntr_generic__parameterized0_151 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[4].busy_active_count | cntr_generic__parameterized0_152 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[4].busy_assert_counter | cntr_generic_153 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[4].busy_count | cntr_generic__parameterized0_154 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[5].busy_active_count | cntr_generic__parameterized0_155 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[5].busy_assert_counter | cntr_generic_156 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[5].busy_count | cntr_generic__parameterized0_157 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[6].busy_active_count | cntr_generic__parameterized0_158 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[6].busy_assert_counter | cntr_generic_159 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[6].busy_count | cntr_generic__parameterized0_160 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[7].busy_active_count | cntr_generic__parameterized0_161 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[7].busy_assert_counter | cntr_generic_162 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[7].busy_count | cntr_generic__parameterized0_163 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[8].busy_active_count | cntr_generic__parameterized0_164 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[8].busy_assert_counter | cntr_generic_165 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[8].busy_count | cntr_generic__parameterized0_166 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[9].busy_active_count | cntr_generic__parameterized0_167 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[9].busy_assert_counter | cntr_generic_168 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_3[9].busy_count | cntr_generic__parameterized0_169 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].xoff_active_count | cntr_generic__parameterized0_170 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].xoff_assert_counter | cntr_generic_171 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[0].xoff_count | cntr_generic__parameterized0_172 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[10].xoff_active_count | cntr_generic__parameterized0_173 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[10].xoff_assert_counter | cntr_generic_174 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[10].xoff_count | cntr_generic__parameterized0_175 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[11].xoff_active_count | cntr_generic__parameterized0_176 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[11].xoff_assert_counter | cntr_generic_177 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[11].xoff_count | cntr_generic__parameterized0_178 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[12].xoff_active_count | cntr_generic__parameterized0_179 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[12].xoff_assert_counter | cntr_generic_180 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[12].xoff_count | cntr_generic__parameterized0_181 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[13].xoff_active_count | cntr_generic__parameterized0_182 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[13].xoff_assert_counter | cntr_generic_183 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[13].xoff_count | cntr_generic__parameterized0_184 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[14].xoff_active_count | cntr_generic__parameterized0_185 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[14].xoff_assert_counter | cntr_generic_186 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[14].xoff_count | cntr_generic__parameterized0_187 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[15].xoff_active_count | cntr_generic__parameterized0_188 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[15].xoff_assert_counter | cntr_generic_189 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[15].xoff_count | cntr_generic__parameterized0_190 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].xoff_active_count | cntr_generic__parameterized0_191 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].xoff_assert_counter | cntr_generic_192 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[1].xoff_count | cntr_generic__parameterized0_193 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].xoff_active_count | cntr_generic__parameterized0_194 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].xoff_assert_counter | cntr_generic_195 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[2].xoff_count | cntr_generic__parameterized0_196 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].xoff_active_count | cntr_generic__parameterized0_197 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].xoff_assert_counter | cntr_generic_198 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[3].xoff_count | cntr_generic__parameterized0_199 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[4].xoff_active_count | cntr_generic__parameterized0_200 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[4].xoff_assert_counter | cntr_generic_201 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[4].xoff_count | cntr_generic__parameterized0_202 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[5].xoff_active_count | cntr_generic__parameterized0_203 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[5].xoff_assert_counter | cntr_generic_204 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[5].xoff_count | cntr_generic__parameterized0_205 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[6].xoff_active_count | cntr_generic__parameterized0_206 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[6].xoff_assert_counter | cntr_generic_207 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[6].xoff_count | cntr_generic__parameterized0_208 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[7].xoff_active_count | cntr_generic__parameterized0_209 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[7].xoff_assert_counter | cntr_generic_210 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[7].xoff_count | cntr_generic__parameterized0_211 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[8].xoff_active_count | cntr_generic__parameterized0_212 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[8].xoff_assert_counter | cntr_generic_213 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[8].xoff_count | cntr_generic__parameterized0_214 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[9].xoff_active_count | cntr_generic__parameterized0_215 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[9].xoff_assert_counter | cntr_generic_216 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GENERATE_4[9].xoff_count | cntr_generic__parameterized0_217 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_count | cntr_generic__parameterized0_218 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | packet_tide_mark_block | packet_tide_mark_block | 142(0.07%) | 142(0.07%) | 0(0.00%) | 0(0.00%) | 636(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[0].MUX_register_A | fwft_register | 67(0.03%) | 67(0.03%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[0].MUX_register_B | fwft_register_41 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[1].MUX_register_A | fwft_register_42 | 68(0.03%) | 68(0.03%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[1].MUX_register_B | fwft_register_43 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[2].MUX_register_A | fwft_register_44 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[2].MUX_register_B | fwft_register_45 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[3].MUX_register_A | fwft_register_46 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[3].MUX_register_B | fwft_register_47 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[4].MUX_register_A | fwft_register_48 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[4].MUX_register_B | fwft_register_49 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[5].MUX_register_A | fwft_register_50 | 54(0.03%) | 54(0.03%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MUX_registers[5].MUX_register_B | fwft_register_51 | 73(0.04%) | 73(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Merged_FIFOs[0].merged_fifo_A | packet_fifo_block__parameterized2 | 379(0.19%) | 313(0.15%) | 66(0.09%) | 0(0.00%) | 324(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[0].merged_fifo_A) | packet_fifo_block__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_134 | 171(0.08%) | 105(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo__parameterized1_135 | 209(0.10%) | 209(0.10%) | 0(0.00%) | 0(0.00%) | 226(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[0].merged_fifo_B | packet_fifo_block__parameterized2_52 | 319(0.16%) | 253(0.12%) | 66(0.09%) | 0(0.00%) | 320(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[0].merged_fifo_B) | packet_fifo_block__parameterized2_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_132 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo__parameterized1_133 | 149(0.07%) | 149(0.07%) | 0(0.00%) | 0(0.00%) | 222(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[0].merged_fifo_reset_block_A | packet_fifo_reset_block_53 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Merged_FIFOs[0].merged_fifo_reset_block_B | packet_fifo_reset_block_54 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Merged_FIFOs[1].merged_fifo_A | packet_fifo_block__parameterized2_55 | 379(0.19%) | 313(0.15%) | 66(0.09%) | 0(0.00%) | 323(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[1].merged_fifo_A) | packet_fifo_block__parameterized2_55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_130 | 170(0.08%) | 104(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo__parameterized1_131 | 209(0.10%) | 209(0.10%) | 0(0.00%) | 0(0.00%) | 225(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[1].merged_fifo_B | packet_fifo_block__parameterized2_56 | 319(0.16%) | 253(0.12%) | 66(0.09%) | 0(0.00%) | 324(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (Merged_FIFOs[1].merged_fifo_B) | packet_fifo_block__parameterized2_56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_129 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo__parameterized1 | 148(0.07%) | 148(0.07%) | 0(0.00%) | 0(0.00%) | 226(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | Merged_FIFOs[1].merged_fifo_reset_block_A | packet_fifo_reset_block_57 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Merged_FIFOs[1].merged_fifo_reset_block_B | packet_fifo_reset_block_58 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_MUX_A | efex_packet_mux__parameterized1 | 193(0.09%) | 193(0.09%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_MUX_B | efex_packet_mux__parameterized1_59 | 176(0.09%) | 176(0.09%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[0].Packet_Builder | efex_packet_builder | 409(0.20%) | 409(0.20%) | 0(0.00%) | 0(0.00%) | 412(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[0].Packet_Builder) | efex_packet_builder | 119(0.06%) | 119(0.06%) | 0(0.00%) | 0(0.00%) | 354(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_block | CRC20__parameterized1_127 | 223(0.11%) | 223(0.11%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc9_block | CRC20_128 | 84(0.04%) | 84(0.04%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[0].Packet_Builder_register | fwft_register_60 | 75(0.04%) | 75(0.04%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[0].built_fifo_spy | fifo_spy__parameterized1 | 99(0.05%) | 99(0.05%) | 0(0.00%) | 0(0.00%) | 236(0.06%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[0].built_fifo_spy) | fifo_spy__parameterized1 | 83(0.04%) | 83(0.04%) | 0(0.00%) | 0(0.00%) | 235(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram64__parameterized1_126 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | Packet_builders[1].Packet_Builder | efex_packet_builder_61 | 412(0.20%) | 412(0.20%) | 0(0.00%) | 0(0.00%) | 412(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[1].Packet_Builder) | efex_packet_builder_61 | 123(0.06%) | 123(0.06%) | 0(0.00%) | 0(0.00%) | 354(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc20_block | CRC20__parameterized1 | 221(0.11%) | 221(0.11%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | crc9_block | CRC20 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[1].Packet_Builder_register | fwft_register_62 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Packet_builders[1].built_fifo_spy | fifo_spy__parameterized1_63 | 134(0.07%) | 134(0.07%) | 0(0.00%) | 0(0.00%) | 236(0.06%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | (Packet_builders[1].built_fifo_spy) | fifo_spy__parameterized1_63 | 84(0.04%) | 84(0.04%) | 0(0.00%) | 0(0.00%) | 235(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram64__parameterized1 | 50(0.02%) | 50(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].MGT_object | mgt_buffer | 1006(0.49%) | 909(0.45%) | 0(0.00%) | 97(0.14%) | 1962(0.48%) | 4(0.53%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[0].MGT_object) | mgt_buffer | 85(0.04%) | 85(0.04%) | 0(0.00%) | 0(0.00%) | 319(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_357 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver_358 | 165(0.08%) | 165(0.08%) | 0(0.00%) | 0(0.00%) | 256(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_block.mgt_ila | ila_1 | 672(0.33%) | 577(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_block.mgt_ila) | ila_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_16_ila | 672(0.33%) | 577(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_16_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_16_ila_core | 671(0.33%) | 576(0.28%) | 0(0.00%) | 95(0.14%) | 1162(0.28%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_16_ila_core | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_16_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_2_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_2_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_2_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_16_ila_cap_addrgen | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_16_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_2_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_16_ila_cap_sample_counter | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_16_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_2_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_2_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_2_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_2_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_16_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_16_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_2_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_2_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_2_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_2_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_2_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_16_ila_register | 473(0.23%) | 472(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_16_ila_register | 255(0.13%) | 254(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized0 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_4_xsdbs | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_4_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_4_reg__parameterized27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_4_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_4_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_4_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_4_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_4_reg__parameterized11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_4_reg__parameterized12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_4_reg__parameterized13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_4_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_4_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_10 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_4_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_4_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_4_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_8 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_4_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_7 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_4_reg__parameterized39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_4_reg__parameterized41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_4_reg__parameterized14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized1 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_4_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_16_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_16_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_16_ila_trigger | 45(0.02%) | 19(0.01%) | 0(0.00%) | 26(0.04%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_16_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_2_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_2_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_16_ila_trig_match | 39(0.02%) | 18(0.01%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_16_ila_trig_match | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_2_match__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_2_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_2_generic_memrd | 47(0.02%) | 45(0.02%) | 0(0.00%) | 2(0.01%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11 | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo | 83(0.04%) | 81(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 44(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].TOB_register_A | fwft_register_64 | 94(0.05%) | 94(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].TOB_register_B | fwft_register_65 | 94(0.05%) | 94(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_fifo_A | packet_fifo_block | 325(0.16%) | 259(0.13%) | 66(0.09%) | 0(0.00%) | 323(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[0].tob_fifo_A) | packet_fifo_block | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_124 | 169(0.08%) | 103(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_125 | 156(0.08%) | 156(0.08%) | 0(0.00%) | 0(0.00%) | 224(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[0].tob_fifo_B | packet_fifo_block_66 | 323(0.16%) | 257(0.13%) | 66(0.09%) | 0(0.00%) | 258(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[0].tob_fifo_B) | packet_fifo_block_66 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_122 | 170(0.08%) | 104(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_123 | 154(0.08%) | 154(0.08%) | 0(0.00%) | 0(0.00%) | 159(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[0].tob_fifo_reset_A | packet_fifo_reset_block_67 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_fifo_reset_B | packet_fifo_reset_block_68 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_fifo_selector | fifo_selector_69 | 41(0.02%) | 9(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].MGT_object | mgt_buffer__parameterized1 | 987(0.48%) | 890(0.44%) | 0(0.00%) | 97(0.14%) | 1956(0.48%) | 4(0.53%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[1].MGT_object) | mgt_buffer__parameterized1 | 81(0.04%) | 81(0.04%) | 0(0.00%) | 0(0.00%) | 319(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_361 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized1_362 | 161(0.08%) | 161(0.08%) | 0(0.00%) | 0(0.00%) | 250(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_block.mgt_ila | ila_1_HD119 | 661(0.32%) | 566(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_block.mgt_ila) | ila_1_HD119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_16_ila_HD120 | 661(0.32%) | 566(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_16_ila_HD120 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_16_ila_core_HD121 | 660(0.32%) | 565(0.28%) | 0(0.00%) | 95(0.14%) | 1162(0.28%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_16_ila_core_HD121 | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_16_ila_trace_memory_HD122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_9_HD123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_synth_HD124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_top_HD125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr_HD126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width_HD127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper_HD128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy_HD129 | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy_HD129 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_2_cfglut6__parameterized0_HD130 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_2_cfglut7_HD131 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_2_cfglut7__1_HD132 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_16_ila_cap_addrgen_HD133 | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_16_ila_cap_addrgen_HD133 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_2_cfglut6__1_HD134 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_16_ila_cap_sample_counter_HD135 | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_16_ila_cap_sample_counter_HD135 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_2_cfglut4__1_HD136 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_2_cfglut5__1_HD137 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_2_cfglut6_HD138 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_2_match_nodelay__1_HD139 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25_HD140 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25_HD140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26_HD141 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26_HD141 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_27_HD142 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_28_HD143 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_16_ila_cap_window_counter_HD144 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_16_ila_cap_window_counter_HD144 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_2_cfglut4_HD145 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_2_cfglut5_HD146 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_2_cfglut5__2_HD147 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_2_match_nodelay_HD148 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_HD149 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_HD149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_HD150 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_HD150 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_HD151 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_HD152 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_2_match_nodelay__2_HD153 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21_HD154 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21_HD154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22_HD155 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22_HD155 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_23_HD156 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_24_HD157 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_16_ila_register_HD158 | 462(0.23%) | 461(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_16_ila_register_HD158 | 245(0.12%) | 244(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s_HD159 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized0_HD160 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_4_xsdbs_HD161 | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_4_reg__parameterized26_HD162 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_17_HD163 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_4_reg__parameterized27_HD164 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_16_HD165 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_4_reg__parameterized28_HD166 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_15_HD167 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_4_reg__parameterized29_HD168 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_14_HD169 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_4_reg__parameterized30_HD170 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_13_HD171 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_4_reg__parameterized31_HD172 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_12_HD173 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_4_reg__parameterized11_HD174 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_20_HD175 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_4_reg__parameterized12_HD176 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized0_HD177 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_4_reg__parameterized13_HD178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_19_HD179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_4_reg__parameterized32_HD180 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_11_HD181 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_4_reg__parameterized33_HD182 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_10_HD183 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_4_reg__parameterized34_HD184 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_HD185 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_4_reg__parameterized35_HD186 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_9_HD187 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_4_reg__parameterized36_HD188 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_8_HD189 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_4_reg__parameterized37_HD190 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_7_HD191 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_4_reg__parameterized39_HD192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_6_HD193 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_4_reg__parameterized41_HD194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_5_HD195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_4_reg__parameterized44_HD196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_4_reg__parameterized44_HD196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_4_HD197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_4_reg__parameterized14_HD198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_18_HD199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized1_HD200 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_4_reg_stream_HD201 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_HD202 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0_HD203 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0_HD203 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_HD204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_16_ila_reset_ctrl_HD205 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_16_ila_reset_ctrl_HD205 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection_HD206 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__2_HD207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__3_HD208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__1_HD209 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer_HD210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection__1_HD211 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_16_ila_trigger_HD212 | 45(0.02%) | 19(0.01%) | 0(0.00%) | 26(0.04%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_16_ila_trigger_HD212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_2_match_HD213 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_2_match_HD213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_HD214 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_HD214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA_HD215 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA_HD215 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_3_HD216 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_16_ila_trig_match_HD217 | 39(0.02%) | 18(0.01%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_16_ila_trig_match_HD217 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_2_match__parameterized0_HD218 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_2_match__parameterized0_HD218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0_HD219 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized0_HD220 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized0_HD220 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_HD221 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_0_HD222 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_1_HD223 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_2_HD224 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_HD225 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_2_generic_memrd_HD226 | 47(0.02%) | 45(0.02%) | 0(0.00%) | 2(0.01%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD542 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11_HD543 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth_HD544 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD545 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD546 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD547 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD547 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray_HD548 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2_HD549 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD550 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD551 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD552 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1_HD553 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2_HD554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD555 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD556 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD557 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD557 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD559 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD560 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD561 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 44(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9_HD562 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth_HD563 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD564 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD565 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD566 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD566 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD568 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD568 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].TOB_register_A | fwft_register_70 | 92(0.05%) | 92(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].TOB_register_B | fwft_register_71 | 92(0.05%) | 92(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_fifo_A | packet_fifo_block_72 | 326(0.16%) | 260(0.13%) | 66(0.09%) | 0(0.00%) | 317(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[1].tob_fifo_A) | packet_fifo_block_72 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_120 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_121 | 154(0.08%) | 154(0.08%) | 0(0.00%) | 0(0.00%) | 218(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[1].tob_fifo_B | packet_fifo_block_73 | 326(0.16%) | 260(0.13%) | 66(0.09%) | 0(0.00%) | 257(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[1].tob_fifo_B) | packet_fifo_block_73 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_118 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_119 | 154(0.08%) | 154(0.08%) | 0(0.00%) | 0(0.00%) | 158(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[1].tob_fifo_reset_A | packet_fifo_reset_block_74 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_fifo_reset_B | packet_fifo_reset_block_75 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_fifo_selector | fifo_selector_76 | 39(0.02%) | 7(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].MGT_object | mgt_buffer__parameterized3 | 995(0.49%) | 898(0.44%) | 0(0.00%) | 97(0.14%) | 1974(0.48%) | 4(0.53%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[2].MGT_object) | mgt_buffer__parameterized3 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 319(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_355 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized3_356 | 164(0.08%) | 164(0.08%) | 0(0.00%) | 0(0.00%) | 268(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_block.mgt_ila | ila_1 | 665(0.33%) | 570(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_block.mgt_ila) | ila_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_16_ila | 665(0.33%) | 570(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_16_ila | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_16_ila_core | 664(0.33%) | 569(0.28%) | 0(0.00%) | 95(0.14%) | 1162(0.28%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_16_ila_core | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_16_ila_trace_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_2_cfglut6__parameterized0 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_2_cfglut7 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_2_cfglut7__1 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_16_ila_cap_addrgen | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_16_ila_cap_addrgen | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_2_cfglut6__1 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_16_ila_cap_sample_counter | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_16_ila_cap_sample_counter | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_2_cfglut4__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_2_cfglut5__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_2_cfglut6 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_2_match_nodelay__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_27 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_28 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_16_ila_cap_window_counter | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_16_ila_cap_window_counter | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_2_cfglut4 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_2_cfglut5 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_2_cfglut5__2 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_2_match_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_2_match_nodelay__2 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_23 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_24 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_16_ila_register | 466(0.23%) | 465(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_16_ila_register | 248(0.12%) | 247(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized0 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_4_xsdbs | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_4_reg__parameterized26 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_17 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_4_reg__parameterized27 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_16 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_4_reg__parameterized28 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_4_reg__parameterized29 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_14 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_4_reg__parameterized30 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_13 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_4_reg__parameterized31 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_4_reg__parameterized11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_20 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_4_reg__parameterized12 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_4_reg__parameterized13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_4_reg__parameterized32 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_11 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_4_reg__parameterized33 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_10 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_4_reg__parameterized34 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_4_reg__parameterized35 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_9 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_4_reg__parameterized36 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_8 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_4_reg__parameterized37 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_7 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_4_reg__parameterized39 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_4_reg__parameterized41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_4_reg__parameterized44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_4_reg__parameterized14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized1 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_4_reg_stream | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_16_ila_reset_ctrl | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_16_ila_reset_ctrl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_16_ila_trigger | 45(0.02%) | 19(0.01%) | 0(0.00%) | 26(0.04%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_16_ila_trigger | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_2_match | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_2_match | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_3 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_16_ila_trig_match | 39(0.02%) | 18(0.01%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_16_ila_trig_match | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_2_match__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_2_match__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized0 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized0 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_1 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_2 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_2_generic_memrd | 47(0.02%) | 45(0.02%) | 0(0.00%) | 2(0.01%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD604 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11_HD605 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth_HD606 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD607 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD608 | 82(0.04%) | 80(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD609 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD609 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray_HD610 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2_HD611 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD612 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD613 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD614 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1_HD615 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2_HD616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD617 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD618 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD619 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD619 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD621 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD622 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD623 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 44(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9_HD624 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth_HD625 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD626 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD627 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD628 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD628 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD630 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD630 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2_HD632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].TOB_register_A | fwft_register_77 | 94(0.05%) | 94(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].TOB_register_B | fwft_register_78 | 94(0.05%) | 94(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_fifo_A | packet_fifo_block_79 | 332(0.16%) | 266(0.13%) | 66(0.09%) | 0(0.00%) | 258(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[2].tob_fifo_A) | packet_fifo_block_79 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_116 | 173(0.08%) | 107(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_117 | 158(0.08%) | 158(0.08%) | 0(0.00%) | 0(0.00%) | 159(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[2].tob_fifo_B | packet_fifo_block_80 | 329(0.16%) | 263(0.13%) | 66(0.09%) | 0(0.00%) | 323(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[2].tob_fifo_B) | packet_fifo_block_80 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_114 | 172(0.08%) | 106(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_115 | 156(0.08%) | 156(0.08%) | 0(0.00%) | 0(0.00%) | 224(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[2].tob_fifo_reset_A | packet_fifo_reset_block_81 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_fifo_reset_B | packet_fifo_reset_block_82 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_fifo_selector | fifo_selector_83 | 39(0.02%) | 7(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].MGT_object | mgt_buffer__parameterized5 | 992(0.49%) | 895(0.44%) | 0(0.00%) | 97(0.14%) | 1960(0.48%) | 4(0.53%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[3].MGT_object) | mgt_buffer__parameterized5 | 82(0.04%) | 82(0.04%) | 0(0.00%) | 0(0.00%) | 319(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram_359 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | MGT_receiver | mgt_readout_receiver__parameterized5_360 | 164(0.08%) | 164(0.08%) | 0(0.00%) | 0(0.00%) | 254(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_block.mgt_ila | ila_1_HD227 | 663(0.33%) | 568(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_block.mgt_ila) | ila_1_HD227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | ila_1_ila_v6_2_16_ila_HD228 | 663(0.33%) | 568(0.28%) | 0(0.00%) | 95(0.14%) | 1168(0.29%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (U0) | ila_1_ila_v6_2_16_ila_HD228 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_core_inst | ila_1_ila_v6_2_16_ila_core_HD229 | 662(0.32%) | 567(0.28%) | 0(0.00%) | 95(0.14%) | 1162(0.28%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ila_core_inst) | ila_1_ila_v6_2_16_ila_core_HD229 | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 78(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ila_trace_memory_inst | ila_1_ila_v6_2_16_ila_trace_memory_HD230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | SUBCORE_RAM_BLK_MEM_1.trace_block_memory | ila_1_blk_mem_gen_v8_4_9_HD231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_synth_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_top_HD233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_generic_cstr_HD234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_width_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | ila_1_blk_mem_gen_v8_4_9_blk_mem_gen_prim_wrapper_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | u_ila_cap_ctrl | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy_HD237 | 78(0.04%) | 31(0.02%) | 0(0.00%) | 47(0.07%) | 127(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_cap_ctrl) | ila_1_ila_v6_2_16_ila_cap_ctrl_legacy_HD237 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CDONE | ila_1_ltlib_v1_0_2_cfglut6__parameterized0_HD238 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS0 | ila_1_ltlib_v1_0_2_cfglut7_HD239 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_NS1 | ila_1_ltlib_v1_0_2_cfglut7__1_HD240 | 5(0.01%) | 1(0.01%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_addrgen | ila_1_ila_v6_2_16_ila_cap_addrgen_HD241 | 63(0.03%) | 26(0.01%) | 0(0.00%) | 37(0.05%) | 121(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_addrgen) | ila_1_ila_v6_2_16_ila_cap_addrgen_HD241 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMPRESET | ila_1_ltlib_v1_0_2_cfglut6__1_HD242 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_sample_counter | ila_1_ila_v6_2_16_ila_cap_sample_counter_HD243 | 31(0.02%) | 18(0.01%) | 0(0.00%) | 13(0.02%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_sample_counter) | ila_1_ila_v6_2_16_ila_cap_sample_counter_HD243 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCE | ila_1_ltlib_v1_0_2_cfglut4__1_HD244 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCMPCE | ila_1_ltlib_v1_0_2_cfglut5__1_HD245 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SCRST | ila_1_ltlib_v1_0_2_cfglut6_HD246 | 3(0.01%) | 1(0.01%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_scnt_cmp | ila_1_ltlib_v1_0_2_match_nodelay__1_HD247 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25_HD248 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_25_HD248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26_HD249 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_26_HD249 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_27_HD250 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_28_HD251 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_cap_window_counter | ila_1_ila_v6_2_16_ila_cap_window_counter_HD252 | 29(0.01%) | 8(0.01%) | 0(0.00%) | 21(0.03%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_cap_window_counter) | ila_1_ila_v6_2_16_ila_cap_window_counter_HD252 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WCE | ila_1_ltlib_v1_0_2_cfglut4_HD253 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WHCMPCE | ila_1_ltlib_v1_0_2_cfglut5_HD254 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WLCMPCE | ila_1_ltlib_v1_0_2_cfglut5__2_HD255 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_hcmp | ila_1_ltlib_v1_0_2_match_nodelay_HD256 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_HD257 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_HD257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_HD258 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_HD258 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_HD259 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_HD260 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_wcnt_lcmp | ila_1_ltlib_v1_0_2_match_nodelay__2_HD261 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21_HD262 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_nodelay_21_HD262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22_HD263 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized1_22_HD263 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized1_23_HD264 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized2_24_HD265 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_regs | ila_1_ila_v6_2_16_ila_register_HD266 | 464(0.23%) | 463(0.23%) | 0(0.00%) | 1(0.01%) | 789(0.19%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_regs) | ila_1_ila_v6_2_16_ila_register_HD266 | 246(0.12%) | 245(0.12%) | 0(0.00%) | 1(0.01%) | 157(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MU_SRL[0].mu_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s_HD267 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TC_SRL[0].tc_srl_reg | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized0_HD268 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_SLAVE | ila_1_xsdbs_v1_0_4_xsdbs_HD269 | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 213(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_15 | ila_1_xsdbs_v1_0_4_reg__parameterized26_HD270 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_17_HD271 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_16 | ila_1_xsdbs_v1_0_4_reg__parameterized27_HD272 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_16_HD273 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_17 | ila_1_xsdbs_v1_0_4_reg__parameterized28_HD274 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_15_HD275 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_18 | ila_1_xsdbs_v1_0_4_reg__parameterized29_HD276 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_14_HD277 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_19 | ila_1_xsdbs_v1_0_4_reg__parameterized30_HD278 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_13_HD279 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_1a | ila_1_xsdbs_v1_0_4_reg__parameterized31_HD280 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_12_HD281 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_6 | ila_1_xsdbs_v1_0_4_reg__parameterized11_HD282 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_20_HD283 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_7 | ila_1_xsdbs_v1_0_4_reg__parameterized12_HD284 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized0_HD285 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_8 | ila_1_xsdbs_v1_0_4_reg__parameterized13_HD286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_19_HD287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_80 | ila_1_xsdbs_v1_0_4_reg__parameterized32_HD288 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_11_HD289 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_81 | ila_1_xsdbs_v1_0_4_reg__parameterized33_HD290 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_10_HD291 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_82 | ila_1_xsdbs_v1_0_4_reg__parameterized34_HD292 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl__parameterized1_HD293 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_83 | ila_1_xsdbs_v1_0_4_reg__parameterized35_HD294 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_9_HD295 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_84 | ila_1_xsdbs_v1_0_4_reg__parameterized36_HD296 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_8_HD297 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_85 | ila_1_xsdbs_v1_0_4_reg__parameterized37_HD298 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_7_HD299 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_887 | ila_1_xsdbs_v1_0_4_reg__parameterized39_HD300 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_6_HD301 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_88d | ila_1_xsdbs_v1_0_4_reg__parameterized41_HD302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_5_HD303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_890 | ila_1_xsdbs_v1_0_4_reg__parameterized44_HD304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_890) | ila_1_xsdbs_v1_0_4_reg__parameterized44_HD304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_4_HD305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_9 | ila_1_xsdbs_v1_0_4_reg__parameterized14_HD306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_18_HD307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_srl_fff | ila_1_xsdbs_v1_0_4_reg_p2s__parameterized1_HD308 | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffd | ila_1_xsdbs_v1_0_4_reg_stream_HD309 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_CTL_EQ1.U_CTL | ila_1_xsdbs_v1_0_4_reg_ctl_HD310 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reg_stream_ffe | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0_HD311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reg_stream_ffe) | ila_1_xsdbs_v1_0_4_reg_stream__parameterized0_HD311 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_EN_STAT_EQ1.U_STAT | ila_1_xsdbs_v1_0_4_reg_stat_HD312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_ila_reset_ctrl | ila_1_ila_v6_2_16_ila_reset_ctrl_HD313 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_ila_reset_ctrl) | ila_1_ila_v6_2_16_ila_reset_ctrl_HD313 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arm_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection_HD314 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__2_HD315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.arm_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__3_HD316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_in_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer__1_HD317 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | asyncrounous_transfer.halt_out_transfer_inst | ila_1_ltlib_v1_0_2_async_edge_xfer_HD318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | halt_detection_inst | ila_1_ltlib_v1_0_2_rising_edge_detection__1_HD319 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | u_trig | ila_1_ila_v6_2_16_ila_trigger_HD320 | 45(0.02%) | 19(0.01%) | 0(0.00%) | 26(0.04%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (u_trig) | ila_1_ila_v6_2_16_ila_trigger_HD320 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_TC.N_DDR_TC_INST[0].U_TC | ila_1_ltlib_v1_0_2_match_HD321 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_TC.N_DDR_TC_INST[0].U_TC) | ila_1_ltlib_v1_0_2_match_HD321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA_HD322 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA_HD322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA_HD323 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA_HD323 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_3_HD324 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TM | ila_1_ila_v6_2_16_ila_trig_match_HD325 | 39(0.02%) | 18(0.01%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_TM) | ila_1_ila_v6_2_16_ila_trig_match_HD325 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | N_DDR_MODE.G_NMU[0].U_M | ila_1_ltlib_v1_0_2_match__parameterized0_HD326 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (N_DDR_MODE.G_NMU[0].U_M) | ila_1_ltlib_v1_0_2_match__parameterized0_HD326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0_HD327 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (allx_typeA_match_detection.ltlib_v1_0_2_allx_typeA_inst) | ila_1_ltlib_v1_0_2_allx_typeA__parameterized0_HD327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DUT | ila_1_ltlib_v1_0_2_all_typeA__parameterized0_HD328 | 21(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.03%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (DUT) | ila_1_ltlib_v1_0_2_all_typeA__parameterized0_HD328 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_HD329 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_0_HD330 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_1_HD331 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice__parameterized0_2_HD332 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | I_WHOLE_SLICE.G_SLICE_IDX[4].U_ALL_SRL_SLICE | ila_1_ltlib_v1_0_2_all_typeA_slice_HD333 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xsdb_memory_read_inst | ila_1_ltlib_v1_0_2_generic_memrd_HD334 | 47(0.02%) | 45(0.02%) | 0(0.00%) | 2(0.01%) | 58(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | mgt_fifo | mgt_axi_fifo_HD635 | 81(0.04%) | 79(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_axi_fifo_fifo_generator_v13_2_11_HD636 | 81(0.04%) | 79(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | mgt_axi_fifo_fifo_generator_v13_2_11_synth_HD637 | 81(0.04%) | 79(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mgt_axi_fifo_fifo_generator_top_HD638 | 81(0.04%) | 79(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | grf.rf | mgt_axi_fifo_fifo_generator_ramfifo_HD639 | 81(0.04%) | 79(0.04%) | 0(0.00%) | 2(0.01%) | 218(0.05%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mgt_axi_fifo_clk_x_pntrs_HD640 | 38(0.02%) | 38(0.02%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mgt_axi_fifo_clk_x_pntrs_HD640 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray_HD641 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mgt_axi_fifo_xpm_cdc_gray__2_HD642 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mgt_axi_fifo_rd_logic_HD643 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mgt_axi_fifo_rd_fwft_HD644 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mgt_axi_fifo_rd_status_flags_as_HD645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | mgt_axi_fifo_rd_status_flags_as_HD645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | mgt_axi_fifo_compare_1_HD646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_2_HD647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mgt_axi_fifo_rd_bin_cntr_HD648 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mgt_axi_fifo_wr_logic_HD649 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mgt_axi_fifo_wr_status_flags_as_HD650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | mgt_axi_fifo_wr_status_flags_as_HD650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | mgt_axi_fifo_compare_HD651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | mgt_axi_fifo_compare_0_HD652 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mgt_axi_fifo_wr_bin_cntr_HD653 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mgt_axi_fifo_memory_HD654 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 44(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mgt_axi_fifo_memory_HD654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mgt_axi_fifo_blk_mem_gen_v8_4_9_HD655 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_v8_4_9_synth_HD656 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_axi_fifo_blk_mem_gen_top_HD657 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_axi_fifo_blk_mem_gen_generic_cstr_HD658 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_axi_fifo_blk_mem_gen_prim_width_HD659 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | (ramloop[0].ram.r) | mgt_axi_fifo_blk_mem_gen_prim_width_HD659 | 4(0.01%) | 2(0.01%) | 0(0.00%) | 2(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_axi_fifo_blk_mem_gen_prim_wrapper_HD660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | rstblk | mgt_axi_fifo_reset_blk_ramfifo_HD661 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mgt_axi_fifo_reset_blk_ramfifo_HD661 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mgt_axi_fifo_xpm_cdc_single_HD662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mgt_axi_fifo_xpm_cdc_single__2_HD663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst_HD664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mgt_axi_fifo_xpm_cdc_sync_rst__2_HD665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].TOB_register_A | fwft_register_84 | 95(0.05%) | 95(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].TOB_register_B | fwft_register_85 | 94(0.05%) | 94(0.05%) | 0(0.00%) | 0(0.00%) | 201(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_fifo_A | packet_fifo_block_86 | 394(0.19%) | 328(0.16%) | 66(0.09%) | 0(0.00%) | 258(0.06%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[3].tob_fifo_A) | packet_fifo_block_86 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_112 | 171(0.08%) | 105(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo_113 | 222(0.11%) | 222(0.11%) | 0(0.00%) | 0(0.00%) | 159(0.04%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[3].tob_fifo_B | packet_fifo_block_87 | 331(0.16%) | 265(0.13%) | 66(0.09%) | 0(0.00%) | 318(0.08%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | (TOB_sources[3].tob_fifo_B) | packet_fifo_block_87 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_fifo | packet_fifo_111 | 171(0.08%) | 105(0.05%) | 66(0.09%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_ram_fifo | packet_ram_fifo | 161(0.08%) | 161(0.08%) | 0(0.00%) | 0(0.00%) | 219(0.05%) | 16(2.13%) | 1(0.07%) | 0(0.00%) | | TOB_sources[3].tob_fifo_reset_A | packet_fifo_reset_block_88 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_fifo_reset_B | packet_fifo_reset_block_89 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_fifo_selector | fifo_selector_90 | 40(0.02%) | 8(0.01%) | 0(0.00%) | 32(0.05%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_merge_A | efex_tob_merger | 1041(0.51%) | 1022(0.50%) | 0(0.00%) | 19(0.03%) | 1010(0.25%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tob_merge_A) | efex_tob_merger | 102(0.05%) | 87(0.04%) | 0(0.00%) | 15(0.02%) | 337(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_MUX | efex_packet_mux_101 | 296(0.15%) | 296(0.15%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_merger | efex_packet_merger__parameterized1_102 | 218(0.11%) | 218(0.11%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_processer | efex_tob_processer_103 | 105(0.05%) | 104(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[0].tob_processer) | efex_tob_processer_103 | 92(0.05%) | 91(0.04%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_110 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_processer | efex_tob_processer_104 | 105(0.05%) | 104(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[1].tob_processer) | efex_tob_processer_104 | 93(0.05%) | 92(0.05%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_109 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_processer | efex_tob_processer_105 | 108(0.05%) | 107(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[2].tob_processer) | efex_tob_processer_105 | 92(0.05%) | 91(0.04%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_108 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_processer | efex_tob_processer_106 | 107(0.05%) | 106(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[3].tob_processer) | efex_tob_processer_106 | 95(0.05%) | 94(0.05%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_107 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_merge_B | efex_tob_merger_91 | 1033(0.51%) | 1014(0.50%) | 0(0.00%) | 19(0.03%) | 1010(0.25%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tob_merge_B) | efex_tob_merger_91 | 103(0.05%) | 88(0.04%) | 0(0.00%) | 15(0.02%) | 337(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_MUX | efex_packet_mux | 296(0.15%) | 296(0.15%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_merger | efex_packet_merger__parameterized1 | 221(0.11%) | 221(0.11%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[0].tob_processer | efex_tob_processer | 102(0.05%) | 101(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[0].tob_processer) | efex_tob_processer | 89(0.04%) | 88(0.04%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_100 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[1].tob_processer | efex_tob_processer_95 | 102(0.05%) | 101(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[1].tob_processer) | efex_tob_processer_95 | 90(0.04%) | 89(0.04%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_99 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[2].tob_processer | efex_tob_processer_96 | 105(0.05%) | 104(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[2].tob_processer) | efex_tob_processer_96 | 89(0.04%) | 88(0.04%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger_98 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_sources[3].tob_processer | efex_tob_processer_97 | 105(0.05%) | 104(0.05%) | 0(0.00%) | 1(0.01%) | 159(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOB_sources[3].tob_processer) | efex_tob_processer_97 | 92(0.05%) | 91(0.04%) | 0(0.00%) | 1(0.01%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Debug_packet_merger | efex_packet_merger | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_spy_A | tob_merger_spy | 110(0.05%) | 110(0.05%) | 0(0.00%) | 0(0.00%) | 301(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (tob_spy_A) | tob_merger_spy | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | debug_spy | fifo_spy_93 | 106(0.05%) | 106(0.05%) | 0(0.00%) | 0(0.00%) | 229(0.06%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (debug_spy) | fifo_spy_93 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 228(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram64_94 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | tob_spy_B | tob_merger_spy_92 | 144(0.07%) | 144(0.07%) | 0(0.00%) | 0(0.00%) | 429(0.11%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (tob_spy_B) | tob_merger_spy_92 | 100(0.05%) | 100(0.05%) | 0(0.00%) | 0(0.00%) | 200(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | debug_spy | fifo_spy | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 229(0.06%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (debug_spy) | fifo_spy | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 228(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPbus_RAM | ipbus_dpram64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | ttc_fifos | ttc_fifo_block | 110(0.05%) | 44(0.02%) | 0(0.00%) | 66(0.09%) | 107(0.03%) | 18(2.40%) | 0(0.00%) | 0(0.00%) | | (ttc_fifos) | ttc_fifo_block | 89(0.04%) | 26(0.01%) | 0(0.00%) | 63(0.09%) | 77(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_A | fifo_40M_160M | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | U0 | fifo_40M_160M_fifo_generator_v13_2_11 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_40M_160M_fifo_generator_v13_2_11_synth | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_40M_160M_fifo_generator_top | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gbi.bi | fifo_40M_160M_fifo_generator_v13_2_11_builtin | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | fifo_40M_160M_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | fifo_40M_160M_builtin_top_v6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[2].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[3].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[4].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[5].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[6].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_B | fifo_40M_160M | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | U0 | fifo_40M_160M_fifo_generator_v13_2_11 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_40M_160M_fifo_generator_v13_2_11_synth | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_40M_160M_fifo_generator_top | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gbi.bi | fifo_40M_160M_fifo_generator_v13_2_11_builtin | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | fifo_40M_160M_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | fifo_40M_160M_builtin_top_v6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[2].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[3].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[4].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[5].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[6].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | ttc_fifo_delay | fifo_40M_160M_HD729 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | U0 | fifo_40M_160M_fifo_generator_v13_2_11_HD730 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | fifo_40M_160M_fifo_generator_v13_2_11_synth_HD731 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | fifo_40M_160M_fifo_generator_top_HD732 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gbi.bi | fifo_40M_160M_fifo_generator_v13_2_11_builtin_HD733 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | fifo_40M_160M_reset_builtin_HD734 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | fifo_40M_160M_builtin_top_v6_HD735 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.80%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_HD736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_9_HD737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[2].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_0_HD738 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_8_HD739 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[3].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_1_HD740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_7_HD741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[4].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_2_HD742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_6_HD743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[5].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_3_HD744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_5_HD745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gextw[6].gnll_fifo.inst_extd | fifo_40M_160M_builtin_extdepth_v6_4_HD746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | fifo_40M_160M_builtin_prim_v6_HD747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.synch_hub2_combined_ttc | top_cntrl_synch | 33(0.02%) | 13(0.01%) | 0(0.00%) | 20(0.03%) | 381(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.synch_hub2_combined_ttc) | top_cntrl_synch | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | ctrl_synch_latch | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | first_stage_synch | 20(0.01%) | 1(0.01%) | 0(0.00%) | 19(0.03%) | 357(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | first_stage_synch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 357(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_ctrl | SRL16E_cntrl | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.synch_ttc_combined | top_cntrl_synch__1 | 33(0.02%) | 13(0.01%) | 0(0.00%) | 20(0.03%) | 381(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GOLDEN_IF.synch_ttc_combined) | top_cntrl_synch__1 | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_490 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | ctrl_synch_latch_491 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_492 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | first_stage_synch_493 | 20(0.01%) | 1(0.01%) | 0(0.00%) | 19(0.03%) | 357(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | first_stage_synch_493 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 357(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_ctrl | SRL16E_cntrl_494 | 19(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.top_aurora_hub1 | aurora_hub2__xdcDup__1 | 467(0.23%) | 429(0.21%) | 0(0.00%) | 38(0.05%) | 932(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_core | aurora_wrapper_hub2__xdcDup__1 | 402(0.20%) | 364(0.18%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | efex_aurora_hub2_support__xdcDup__1 | 402(0.20%) | 364(0.18%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | efex_aurora_hub2_support__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | efex_aurora_hub2_CLOCK_MODULE_484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_i | efex_aurora_hub2_HD749 | 400(0.20%) | 362(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | efex_aurora_hub2_core_HD750 | 400(0.20%) | 362(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | efex_aurora_hub2_core_HD750 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_to_ll_pdu_i | efex_aurora_hub2_AXI_TO_LL_HD751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | efex_aurora_hub2_RESET_LOGIC_HD752 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | efex_aurora_hub2_RESET_LOGIC_HD752 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_23_HD753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_24_HD754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | efex_aurora_hub2_cdc_sync_HD755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | efex_aurora_hub2_GT_WRAPPER_HD756 | 126(0.06%) | 94(0.05%) | 0(0.00%) | 32(0.05%) | 175(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | efex_aurora_hub2_GT_WRAPPER_HD756 | 6(0.01%) | 2(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_multi_gt_i | efex_aurora_hub2_multi_gt_HD757 | 49(0.02%) | 21(0.01%) | 0(0.00%) | 28(0.04%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_efex_aurora_hub2_i | efex_aurora_hub2_gt_HD758 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_efex_aurora_hub2_i | efex_aurora_hub2_gt_20_HD759 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_efex_aurora_hub2_i | efex_aurora_hub2_gt_21_HD760 | 13(0.01%) | 6(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_efex_aurora_hub2_i | efex_aurora_hub2_gt_22_HD761 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_txresetfsm_i | efex_aurora_hub2_tx_startup_fsm_HD762 | 71(0.03%) | 71(0.03%) | 0(0.00%) | 0(0.00%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_txresetfsm_i) | efex_aurora_hub2_tx_startup_fsm_HD762 | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | efex_aurora_hub2_cdc_sync_13_HD763 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_15_HD765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | efex_aurora_hub2_cdc_sync_16_HD766 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_17_HD767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_18_HD768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_19_HD769 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | efex_aurora_hub2_cdc_sync_0_HD771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | standard_cc_module_i | efex_aurora_hub2_STANDARD_CC_MODULE_HD772 | 13(0.01%) | 11(0.01%) | 0(0.00%) | 2(0.01%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_0_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_HD773 | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_10_HD774 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11_HD775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12_HD776 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_1_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1_HD777 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_7_HD778 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8_HD779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9_HD780 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_2_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2_HD781 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_4_HD782 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5_HD783 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6_HD784 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_3_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3_HD785 | 39(0.02%) | 39(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_HD786 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_HD787 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_HD788 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_global_logic_simplex_i | efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX_HD789 | 59(0.03%) | 55(0.03%) | 0(0.00%) | 4(0.01%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | idle_and_ver_gen_i | efex_aurora_hub2_IDLE_AND_VER_GEN_HD790 | 12(0.01%) | 10(0.01%) | 0(0.00%) | 2(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_err_detect_simplex_i | efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX_HD791 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_init_sm_simplex_i | efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX_HD792 | 32(0.02%) | 30(0.01%) | 0(0.00%) | 2(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_i | efex_aurora_hub2_TX_LL_HD793 | 49(0.02%) | 49(0.02%) | 0(0.00%) | 0(0.00%) | 281(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_control_i | efex_aurora_hub2_TX_LL_CONTROL_HD794 | 31(0.02%) | 31(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_datapath_i | efex_aurora_hub2_TX_LL_DATAPATH_HD795 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 244(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_common_support | efex_aurora_hub2_gt_common_wrapper_485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | efex_aurora_hub2_SUPPORT_RESET_LOGIC_486 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | efex_aurora_hub2_SUPPORT_RESET_LOGIC_486 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | efex_aurora_hub2_cdc_sync_exdes_487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset_483 | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GOLDEN_IF.top_aurora_hub2 | aurora_hub2 | 467(0.23%) | 429(0.21%) | 0(0.00%) | 38(0.05%) | 932(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_core | aurora_wrapper_hub2 | 402(0.20%) | 364(0.18%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | aurora_module_i | efex_aurora_hub2_support | 402(0.20%) | 364(0.18%) | 0(0.00%) | 38(0.05%) | 892(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (aurora_module_i) | efex_aurora_hub2_support | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_module_i | efex_aurora_hub2_CLOCK_MODULE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_i | efex_aurora_hub2 | 400(0.20%) | 362(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | efex_aurora_hub2_core | 400(0.20%) | 362(0.18%) | 0(0.00%) | 38(0.05%) | 878(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | efex_aurora_hub2_core | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | axi_to_ll_pdu_i | efex_aurora_hub2_AXI_TO_LL | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | core_reset_logic_i | efex_aurora_hub2_RESET_LOGIC | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (core_reset_logic_i) | efex_aurora_hub2_RESET_LOGIC | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | link_reset_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lock_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_reset_cdc_sync | efex_aurora_hub2_cdc_sync | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_wrapper_i | efex_aurora_hub2_GT_WRAPPER | 125(0.06%) | 93(0.05%) | 0(0.00%) | 32(0.05%) | 175(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_wrapper_i) | efex_aurora_hub2_GT_WRAPPER | 6(0.01%) | 2(0.01%) | 0(0.00%) | 4(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_aurora_hub2_multi_gt_i | efex_aurora_hub2_multi_gt | 49(0.02%) | 21(0.01%) | 0(0.00%) | 28(0.04%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_efex_aurora_hub2_i | efex_aurora_hub2_gt | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_efex_aurora_hub2_i | efex_aurora_hub2_gt_20 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_efex_aurora_hub2_i | efex_aurora_hub2_gt_21 | 13(0.01%) | 6(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_efex_aurora_hub2_i | efex_aurora_hub2_gt_22 | 12(0.01%) | 5(0.01%) | 0(0.00%) | 7(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_txresetfsm_i | efex_aurora_hub2_tx_startup_fsm | 70(0.03%) | 70(0.03%) | 0(0.00%) | 0(0.00%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt_txresetfsm_i) | efex_aurora_hub2_tx_startup_fsm | 62(0.03%) | 62(0.03%) | 0(0.00%) | 0(0.00%) | 80(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_CPLLLOCK_cdc_sync | efex_aurora_hub2_cdc_sync_13 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked_cdc_sync | efex_aurora_hub2_cdc_sync_16 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int_cdc_sync | efex_aurora_hub2_cdc_sync__parameterized2_19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_sync_user_clk_cdc_sync | efex_aurora_hub2_cdc_sync_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | standard_cc_module_i | efex_aurora_hub2_STANDARD_CC_MODULE | 13(0.01%) | 11(0.01%) | 0(0.00%) | 2(0.01%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_0_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5 | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_10 | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_1_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_1 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_7 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_2_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_2 | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN_4 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX_6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_aurora_lane_simplex_v5_3_i | efex_aurora_hub2_TX_AURORA_LANE_SIMPLEX_V5_3 | 39(0.02%) | 39(0.02%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sym_gen_i | efex_aurora_hub2_SYM_GEN | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_err_detect_simplex_i | efex_aurora_hub2_TX_ERR_DETECT_SIMPLEX | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_lane_init_simplex_sm_i | efex_aurora_hub2_TX_LANE_INIT_SM_SIMPLEX | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_global_logic_simplex_i | efex_aurora_hub2_TX_GLOBAL_LOGIC_SIMPLEX | 59(0.03%) | 55(0.03%) | 0(0.00%) | 4(0.01%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | idle_and_ver_gen_i | efex_aurora_hub2_IDLE_AND_VER_GEN | 12(0.01%) | 10(0.01%) | 0(0.00%) | 2(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_err_detect_simplex_i | efex_aurora_hub2_TX_CHANNEL_ERR_DETECT_SIMPLEX | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_channel_init_sm_simplex_i | efex_aurora_hub2_TX_CHANNEL_INIT_SM_SIMPLEX | 32(0.02%) | 30(0.01%) | 0(0.00%) | 2(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_i | efex_aurora_hub2_TX_LL | 50(0.02%) | 50(0.02%) | 0(0.00%) | 0(0.00%) | 281(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_control_i | efex_aurora_hub2_TX_LL_CONTROL | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ll_datapath_i | efex_aurora_hub2_TX_LL_DATAPATH | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 244(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_common_support | efex_aurora_hub2_gt_common_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | support_reset_logic_i | efex_aurora_hub2_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (support_reset_logic_i) | efex_aurora_hub2_SUPPORT_RESET_LOGIC | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_rst_r_cdc_sync | efex_aurora_hub2_cdc_sync_exdes | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_timer | aurora_reset | 65(0.03%) | 65(0.03%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | top_udp_config_FPGA | 4634(2.27%) | 4515(2.21%) | 80(0.11%) | 39(0.06%) | 3645(0.89%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | U_0 | interface_proc_fpga | 121(0.06%) | 101(0.05%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_23 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_24 | 110(0.05%) | 90(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interface_proc_fpga_14 | 121(0.06%) | 101(0.05%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_21 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_22 | 112(0.05%) | 92(0.05%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | interface_proc_fpga_15 | 115(0.06%) | 95(0.05%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if_19 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo_20 | 106(0.05%) | 86(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_3 | interface_proc_fpga_16 | 114(0.06%) | 94(0.05%) | 20(0.03%) | 0(0.00%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_hub_if | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | UDP_hub_fifo | 105(0.05%) | 85(0.04%) | 20(0.03%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_4 | mac_arbiter | 33(0.02%) | 33(0.02%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_5 | ipbus_ctrl | 4033(1.98%) | 3994(1.96%) | 0(0.00%) | 39(0.06%) | 3288(0.81%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | (U_5) | ipbus_ctrl | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 1743(0.85%) | 1743(0.85%) | 0(0.00%) | 0(0.00%) | 373(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cfg__0 | transactor_cfg | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 194(0.10%) | 194(0.10%) | 0(0.00%) | 0(0.00%) | 137(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 1549(0.76%) | 1549(0.76%) | 0(0.00%) | 0(0.00%) | 234(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 2287(1.12%) | 2248(1.10%) | 0(0.00%) | 39(0.06%) | 2915(0.71%) | 17(2.27%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 231(0.11%) | 231(0.11%) | 0(0.00%) | 0(0.00%) | 263(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(1.07%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 183(0.09%) | 183(0.09%) | 0(0.00%) | 0(0.00%) | 196(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ARP | udp_build_arp | 89(0.04%) | 89(0.04%) | 0(0.00%) | 0(0.00%) | 134(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.IPAM_block | udp_ipam_block | 269(0.13%) | 269(0.13%) | 0(0.00%) | 0(0.00%) | 168(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | primary_mode.ping | udp_build_ping | 119(0.06%) | 119(0.06%) | 0(0.00%) | 0(0.00%) | 106(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 259(0.13%) | 222(0.11%) | 0(0.00%) | 37(0.05%) | 517(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 60(0.03%) | 60(0.03%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 144(0.07%) | 144(0.07%) | 0(0.00%) | 0(0.00%) | 171(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 349(0.17%) | 349(0.17%) | 0(0.00%) | 0(0.00%) | 434(0.11%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_17 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 214(0.10%) | 214(0.10%) | 0(0.00%) | 0(0.00%) | 221(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized0_18 | 103(0.05%) | 103(0.05%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 134(0.07%) | 134(0.07%) | 0(0.00%) | 0(0.00%) | 264(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_6 | udp_hub_rarp | 85(0.04%) | 85(0.04%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_7 | unique_address | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_12 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_13 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | interconnect_0 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_2) | interconnect_0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_10 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_11 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_3 | interconnect_1 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_3) | interconnect_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen_8 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker_9 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_4 | interconnect_2 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_4) | interconnect_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 28(0.01%) | 27(0.01%) | 0(0.00%) | 1(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 14(0.01%) | 13(0.01%) | 0(0.00%) | 1(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reg | common_id_registers | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fabric_common_IDversion | ipbus_fabric_sel__parameterized0 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | reconfig | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dbg_hub | dbg_hub | 526(0.26%) | 502(0.25%) | 24(0.03%) | 0(0.00%) | 821(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (dbg_hub) | dbg_hub | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | dbg_hub_xsdbm_v3_0_3_xsdbm | 526(0.26%) | 502(0.25%) | 24(0.03%) | 0(0.00%) | 821(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BSCANID.u_xsdbm_id | dbg_hub_xsdbm_v3_0_3_xsdbm_id | 526(0.26%) | 502(0.25%) | 24(0.03%) | 0(0.00%) | 821(0.20%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (BSCANID.u_xsdbm_id) | dbg_hub_xsdbm_v3_0_3_xsdbm_id | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.UUT_MASTER | dbg_hub_xsdbm_v3_0_3_icon2xsdb | 350(0.17%) | 326(0.16%) | 24(0.03%) | 0(0.00%) | 634(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_ICON_INTERFACE | dbg_hub_xsdbm_v3_0_3_if | 190(0.09%) | 166(0.08%) | 24(0.03%) | 0(0.00%) | 492(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_ICON_INTERFACE) | dbg_hub_xsdbm_v3_0_3_if | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD1 | dbg_hub_xsdbm_v3_0_3_ctl_reg | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD2 | dbg_hub_xsdbm_v3_0_3_stat_reg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD3 | dbg_hub_xsdbm_v3_0_3_stat_reg__parameterized0 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD4 | dbg_hub_xsdbm_v3_0_3_ctl_reg__parameterized0 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD5 | dbg_hub_xsdbm_v3_0_3_ctl_reg__parameterized1 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_RD | dbg_hub_xsdbm_v3_0_3_rdreg | 68(0.03%) | 56(0.03%) | 12(0.02%) | 0(0.00%) | 134(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_RD) | dbg_hub_xsdbm_v3_0_3_rdreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_FIFO | dbg_hub_xsdbm_v3_0_3_rdfifo | 66(0.03%) | 54(0.03%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_RD_FIFO) | dbg_hub_xsdbm_v3_0_3_rdfifo | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_3_rdfifo_inst | dbg_hub_fifo_generator_v13_1_5__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_3_rdfifo_inst) | dbg_hub_fifo_generator_v13_1_5__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_5_synth__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo__parameterized0 | 47(0.02%) | 35(0.02%) | 12(0.02%) | 0(0.00%) | 114(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs_6 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs_6 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_21 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | dbg_hub_rd_fwft | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr_17 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic__parameterized0 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as_13 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr_15 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory__parameterized0 | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | dbg_hub_memory__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem_12 | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo_7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo_7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD6_WR | dbg_hub_xsdbm_v3_0_3_wrreg | 45(0.02%) | 33(0.02%) | 12(0.02%) | 0(0.00%) | 110(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_CMD6_WR) | dbg_hub_xsdbm_v3_0_3_wrreg | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_WR_FIFO | dbg_hub_xsdbm_v3_0_3_wrfifo | 43(0.02%) | 31(0.02%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_WR_FIFO) | dbg_hub_xsdbm_v3_0_3_wrfifo | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SUBCORE_FIFO.xsdbm_v3_0_3_wrfifo_inst | dbg_hub_fifo_generator_v13_1_5 | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (SUBCORE_FIFO.xsdbm_v3_0_3_wrfifo_inst) | dbg_hub_fifo_generator_v13_1_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | dbg_hub_fifo_generator_v13_1_5_synth | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | dbg_hub_fifo_generator_top | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grf.rf | dbg_hub_fifo_generator_ramfifo | 42(0.02%) | 30(0.01%) | 12(0.02%) | 0(0.00%) | 90(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | dbg_hub_clk_x_pntrs | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | dbg_hub_clk_x_pntrs | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[1].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].rd_stg_inst | dbg_hub_synchronizer_ff__parameterized0_4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gnxpm_cdc.gsync_stage[2].wr_stg_inst | dbg_hub_synchronizer_ff__parameterized0_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | dbg_hub_rd_logic | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | dbg_hub_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | dbg_hub_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | dbg_hub_rd_bin_cntr | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | dbg_hub_wr_logic | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | dbg_hub_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwhf.whf | dbg_hub_wr_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | dbg_hub_wr_bin_cntr | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | dbg_hub_memory | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gdm.dm_gen.dm | dbg_hub_dmem | 12(0.01%) | 0(0.00%) | 12(0.02%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rstblk | dbg_hub_reset_blk_ramfifo | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | dbg_hub_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst | dbg_hub_synchronizer_ff | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst | dbg_hub_synchronizer_ff_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst | dbg_hub_synchronizer_ff_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst | dbg_hub_synchronizer_ff_2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_CTL | dbg_hub_xsdbm_v3_0_3_ctl_reg__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD7_STAT | dbg_hub_xsdbm_v3_0_3_stat_reg__parameterized1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STATIC_STATUS | dbg_hub_xsdbm_v3_0_3_if_static_status | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_ADDRESS_CONTROLLER | dbg_hub_xsdbm_v3_0_3_addr_ctl | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BURST_WD_LEN_CONTROLLER | dbg_hub_xsdbm_v3_0_3_burst_wdlen_ctl | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_CONTROLLER | dbg_hub_xsdbm_v3_0_3_bus_ctl | 86(0.04%) | 86(0.04%) | 0(0.00%) | 0(0.00%) | 86(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_CONTROLLER) | dbg_hub_xsdbm_v3_0_3_bus_ctl | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 75(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_ABORT_FLAG | dbg_hub_xsdbm_v3_0_3_bus_ctl_flg__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_REQ_FLAG | dbg_hub_xsdbm_v3_0_3_bus_ctl_flg | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_TIMER | dbg_hub_xsdbm_v3_0_3_bus_ctl_cnt | 67(0.03%) | 67(0.03%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_XSDB_BUS_MSTR2SL_PORT_IFACE | dbg_hub_xsdbm_v3_0_3_bus_mstr2sl_if | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_XSDB_BUS_MSTR2SL_PORT_IFACE) | dbg_hub_xsdbm_v3_0_3_bus_mstr2sl_if | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_RD_DIN_BUS_MUX | dbg_hub_ltlib_v1_0_2_generic_mux | 32(0.02%) | 32(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE_XSDB.U_ICON | dbg_hub_xsdbm_v3_0_3_icon | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (CORE_XSDB.U_ICON) | dbg_hub_xsdbm_v3_0_3_icon | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_CMD | dbg_hub_xsdbm_v3_0_3_cmd_decode | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_STAT | dbg_hub_xsdbm_v3_0_3_stat | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_SYNC | dbg_hub_xsdbm_v3_0_3_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_inst | dbg_hub_ltlib_v1_0_2_bscan | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SWITCH_N_EXT_BSCAN.bscan_switch | dbg_hub_xsdbm_v3_0_3_bscan_switch | 124(0.06%) | 124(0.06%) | 0(0.00%) | 0(0.00%) | 125(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eth | eth_7s_gmii | 579(0.28%) | 551(0.27%) | 16(0.02%) | 12(0.02%) | 794(0.19%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (eth) | eth_7s_gmii | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | emac0 | temac_gbe_v9_0 | 527(0.26%) | 502(0.25%) | 16(0.02%) | 9(0.01%) | 680(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | temac_gbe_v9_0_block | 527(0.26%) | 502(0.25%) | 16(0.02%) | 9(0.01%) | 680(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_interface | temac_gbe_v9_0_gmii_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | temac_gbe_v9_0_core | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35 | 527(0.26%) | 502(0.25%) | 16(0.02%) | 9(0.01%) | 680(0.17%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (temac_gbe_v9_0_core) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | addr_filter_top | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_addr_filter_wrap | 43(0.02%) | 26(0.01%) | 16(0.02%) | 1(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | address_filter_inst | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_addr_filter | 43(0.02%) | 26(0.01%) | 16(0.02%) | 1(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (address_filter_inst) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_addr_filter | 42(0.02%) | 25(0.01%) | 16(0.02%) | 1(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resync_promiscuous_mode | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_block_7 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | flow | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_control | 121(0.06%) | 121(0.06%) | 0(0.00%) | 0(0.00%) | 156(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (flow) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_control | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pfc_tx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_pfc_tx_cntl | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_rx_cntl | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_pause | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_rx_sync_req | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_enable | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_block | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_enable | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_block_5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_tx_cntl | 53(0.03%) | 53(0.03%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_pause | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_tx_pause | 44(0.02%) | 44(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_pause) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_tx_pause | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_good_rx | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_block_6 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_rx_gen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_gmii_mii_rx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gmii_mii_tx_gen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_gmii_mii_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | no_avb_tx_axi_intf.tx_axi_shim | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_tx_axi_intf | 79(0.04%) | 79(0.04%) | 0(0.00%) | 0(0.00%) | 76(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_axi_shim | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_rx_axi_intf | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rxgen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_rx | 154(0.08%) | 146(0.07%) | 0(0.00%) | 8(0.01%) | 181(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rxgen) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_rx | 26(0.01%) | 18(0.01%) | 0(0.00%) | 8(0.01%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FCS_CHECK | temac_gbe_v9_0_CRC32_8 | 46(0.02%) | 46(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_CHECKER | temac_gbe_v9_0_PARAM_CHECK | 28(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FRAME_DECODER | temac_gbe_v9_0_DECODE_FRAME | 42(0.02%) | 42(0.02%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX_SM | temac_gbe_v9_0_STATE_MACHINES | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_axi_rx_rstn_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_reset__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_reset__parameterized0_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_glbl_rstn_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_reset__parameterized0_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_rx_rst_mgmt_rx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_reset | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_int_tx_rst_mgmt_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_reset_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_axi_rstn_tx_clk | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_sync_reset__parameterized0_4 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txgen | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_tx | 122(0.06%) | 122(0.06%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (txgen) | temac_gbe_v9_0_tri_mode_ethernet_mac_v9_0_35_tx | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TX_SM1 | temac_gbe_v9_0_TX_STATE_MACH | 122(0.06%) | 122(0.06%) | 0(0.00%) | 0(0.00%) | 126(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TX_SM1) | temac_gbe_v9_0_TX_STATE_MACH | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 94(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CRCGEN | temac_gbe_v9_0_CRC32_8__1 | 46(0.02%) | 46(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fifo | mac_fifo_axi4 | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | U0 | mac_fifo_axi4_fifo_generator_v13_2_11 | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | inst_fifo_gen | mac_fifo_axi4_fifo_generator_v13_2_11_synth | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gaxis_fifo.gaxisf.axisf | mac_fifo_axi4_fifo_generator_top | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | grf.rf | mac_fifo_axi4_fifo_generator_ramfifo | 49(0.02%) | 46(0.02%) | 0(0.00%) | 3(0.01%) | 114(0.03%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | mac_fifo_axi4_clk_x_pntrs | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | mac_fifo_axi4_clk_x_pntrs | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | mac_fifo_axi4_xpm_cdc_gray | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | mac_fifo_axi4_xpm_cdc_gray__2 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | mac_fifo_axi4_rd_logic | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gr1.gr1_int.rfwft | mac_fifo_axi4_rd_fwft | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | mac_fifo_axi4_rd_status_flags_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | mac_fifo_axi4_rd_bin_cntr | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | mac_fifo_axi4_wr_logic | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | mac_fifo_axi4_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | mac_fifo_axi4_wr_bin_cntr | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | mac_fifo_axi4_memory | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 18(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (gntv_or_sync_fifo.mem) | mac_fifo_axi4_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | mac_fifo_axi4_blk_mem_gen_v8_4_9 | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | inst_blk_mem_gen | mac_fifo_axi4_blk_mem_gen_v8_4_9_synth | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mac_fifo_axi4_blk_mem_gen_top | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | valid.cstr | mac_fifo_axi4_blk_mem_gen_generic_cstr | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | ramloop[0].ram.r | mac_fifo_axi4_blk_mem_gen_prim_width | 6(0.01%) | 3(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | (ramloop[0].ram.r) | mac_fifo_axi4_blk_mem_gen_prim_width | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mac_fifo_axi4_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.07%) | 0(0.00%) | | rstblk | mac_fifo_axi4_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | mac_fifo_axi4_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | mac_fifo_axi4_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | mac_fifo_axi4_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | mac_fifo_axi4_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | mac_fifo_axi4_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | infrastructure_control | infrastructure_slaves_cntrl | 841(0.41%) | 841(0.41%) | 0(0.00%) | 0(0.00%) | 1258(0.31%) | 5(0.67%) | 0(0.00%) | 0(0.00%) | | (infrastructure_control) | infrastructure_slaves_cntrl | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | i2c_0 | ipbus_i2c_master_arb | 198(0.10%) | 198(0.10%) | 0(0.00%) | 0(0.00%) | 221(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 76(0.04%) | 76(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | i2c_arp | ipbus_i2c_master | 122(0.06%) | 122(0.06%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | i2c | i2c_master_top | 122(0.06%) | 122(0.06%) | 0(0.00%) | 0(0.00%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (i2c) | i2c_master_top | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bit_controller | i2c_master_bit_ctrl | 63(0.03%) | 63(0.03%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | byte_controller | i2c_master_byte_ctrl | 35(0.02%) | 35(0.02%) | 0(0.00%) | 0(0.00%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | registers | i2c_master_registers | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 53(0.03%) | 53(0.03%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig | ipbus_ctrlreg_v__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32__parameterized0 | 274(0.13%) | 274(0.13%) | 0(0.00%) | 0(0.00%) | 304(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32__parameterized0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog_3 | 132(0.06%) | 132(0.06%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized2 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash__parameterized1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control__parameterized0 | 72(0.04%) | 72(0.04%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_pll | ipbus_spi32 | 263(0.13%) | 263(0.13%) | 0(0.00%) | 0(0.00%) | 299(0.07%) | 2(0.27%) | 0(0.00%) | 0(0.00%) | | (spi_pll) | ipbus_spi32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog_4 | 132(0.06%) | 132(0.06%) | 0(0.00%) | 0(0.00%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse_5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3_6 | 36(0.02%) | 36(0.02%) | 0(0.00%) | 0(0.00%) | 128(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 43(0.02%) | 43(0.02%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.13%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync_7 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 55(0.03%) | 55(0.03%) | 0(0.00%) | 0(0.00%) | 367(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 55(0.03%) | 55(0.03%) | 0(0.00%) | 0(0.00%) | 366(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | pll_sel | pll_selector | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_pll | nreset_pll | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (reset_pll) | nreset_pll | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reset_gen | nreset_gen | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_clk | clk_ttc | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_ttc_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-----------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------+---------------+-------------+-------------+---------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining