Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
| Date         : Wed Apr  2 17:10:56 2025
| Host         : runner-w-bkzzvvi-project-27372-concurrent-0-b1ehc2wf running 64-bit Ubuntu 22.04.5 LTS
| Command      : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx
| Design       : top_efex_control
| Device       : xc7vx330tffg1157-2
| Speed File   : -2
| Design State : Synthesized
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max checks: <unlimited>
             Checks found: 5
+----------+------------------+--------------------------+--------+
| Rule     | Severity         | Description              | Checks |
+----------+------------------+--------------------------+--------+
| AVAL-326 | Critical Warning | Hard_block_must_have_LOC | 2      |
| REQP-45  | Warning          | must_use_ref_clock       | 3      |
+----------+------------------+--------------------------+--------+

2. REPORT DETAILS
-----------------
AVAL-326#1 Critical Warning
Hard_block_must_have_LOC  
The hard block GTHE2_CHANNEL cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt2_MGT_TX_RX_6G4_i/gthe2_i is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems.
Related violations: <none>

AVAL-326#2 Critical Warning
Hard_block_must_have_LOC  
The hard block GTHE2_CHANNEL cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt3_MGT_TX_RX_6G4_i/gthe2_i is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems.
Related violations: <none>

REQP-45#1 Warning
must_use_ref_clock  
GTHE2_COMMON cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/common0_i/gthe2_common_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set QPLLREFCLKSEL[2:0] appropriately) must be used (unless this cell is just to set needed configuration).
Related violations: <none>

REQP-45#2 Warning
must_use_ref_clock  
GTHE2_COMMON cell GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/gt_common_support/gthe2_common_lane1_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set QPLLREFCLKSEL[2:0] appropriately) must be used (unless this cell is just to set needed configuration).
Related violations: <none>

REQP-45#3 Warning
must_use_ref_clock  
GTHE2_COMMON cell GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/gt_common_support/gthe2_common_lane1_i: An input reference clock pin (GTREFCLK0, GTREFCLK1, GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1 and set QPLLREFCLKSEL[2:0] appropriately) must be used (unless this cell is just to set needed configuration).
Related violations: <none>


