*** Running vivado with args -log AlgoParameterRAM.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source AlgoParameterRAM.tcl ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Wed Apr 2 17:05:48 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source AlgoParameterRAM.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1767.637 ; gain = 139.836 ; free physical = 23937 ; free virtual = 42095 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: AlgoParameterRAM Command: synth_design -top AlgoParameterRAM -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3859 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2683.941 ; gain = 421.797 ; free physical = 22711 ; free virtual = 40869 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'AlgoParameterRAM' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/synth/AlgoParameterRAM.vhd:76] WARNING: [Synth 8-3819] Generic 'GLOBAL_DATE' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_TIME' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'GLOBAL_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOP_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'HOG_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'CON_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'XML_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOB_RDOUT_LIB_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'TOB_RDOUT_LIB_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'ALGOLIB_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'ALGOLIB_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'INFRASTRUCTURE_LIB_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'INFRASTRUCTURE_LIB_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPS_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPBUS_LIB_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPBUS_LIB_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'USR_IP_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'USR_IP_SHA' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'FLAVOUR' not present in instantiated entity will be ignored Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_XDEVICEFAMILY bound to: virtex7 - type: string Parameter C_ELABORATION_DIR bound to: ./ - type: string Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string Parameter C_HAS_AXI_ID bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_MEM_TYPE bound to: 2 - type: integer Parameter C_BYTE_SIZE bound to: 9 - type: integer Parameter C_ALGORITHM bound to: 2 - type: integer Parameter C_PRIM_TYPE bound to: 1 - type: integer Parameter C_LOAD_INIT_FILE bound to: 0 - type: integer Parameter C_INIT_FILE_NAME bound to: no_coe_file_loaded - type: string Parameter C_INIT_FILE bound to: AlgoParameterRAM.mem - type: string Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer Parameter C_DEFAULT_DATA bound to: 0 - type: string Parameter C_HAS_RSTA bound to: 0 - type: integer Parameter C_RST_PRIORITY_A bound to: CE - type: string Parameter C_RSTRAM_A bound to: 0 - type: integer Parameter C_INITA_VAL bound to: 0 - type: string Parameter C_HAS_ENA bound to: 1 - type: integer Parameter C_HAS_REGCEA bound to: 0 - type: integer Parameter C_USE_BYTE_WEA bound to: 0 - type: integer Parameter C_WEA_WIDTH bound to: 1 - type: integer Parameter C_WRITE_MODE_A bound to: READ_FIRST - type: string Parameter C_WRITE_WIDTH_A bound to: 32 - type: integer Parameter C_READ_WIDTH_A bound to: 32 - type: integer Parameter C_WRITE_DEPTH_A bound to: 40 - type: integer Parameter C_READ_DEPTH_A bound to: 40 - type: integer Parameter C_ADDRA_WIDTH bound to: 6 - type: integer Parameter C_HAS_RSTB bound to: 0 - type: integer Parameter C_RST_PRIORITY_B bound to: CE - type: string Parameter C_RSTRAM_B bound to: 0 - type: integer Parameter C_INITB_VAL bound to: 0 - type: string Parameter C_HAS_ENB bound to: 1 - type: integer Parameter C_HAS_REGCEB bound to: 0 - type: integer Parameter C_USE_BYTE_WEB bound to: 0 - type: integer Parameter C_WEB_WIDTH bound to: 1 - type: integer Parameter C_WRITE_MODE_B bound to: NO_CHANGE - type: string Parameter C_WRITE_WIDTH_B bound to: 256 - type: integer Parameter C_READ_WIDTH_B bound to: 256 - type: integer Parameter C_WRITE_DEPTH_B bound to: 5 - type: integer Parameter C_READ_DEPTH_B bound to: 5 - type: integer Parameter C_ADDRB_WIDTH bound to: 3 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 1 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer Parameter C_USE_SOFTECC bound to: 0 - type: integer Parameter C_USE_ECC bound to: 0 - type: integer Parameter C_EN_ECC_PIPE bound to: 0 - type: integer Parameter C_READ_LATENCY_A bound to: 1 - type: integer Parameter C_READ_LATENCY_B bound to: 1 - type: integer Parameter C_HAS_INJECTERR bound to: 0 - type: integer Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string Parameter C_COMMON_CLK bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer Parameter C_USE_URAM bound to: 0 - type: integer Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer Parameter C_COUNT_36K_BRAM bound to: 8 - type: string Parameter C_COUNT_18K_BRAM bound to: 0 - type: string Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 42.564596 mW - type: string INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_9' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195208' bound to instance 'U0' of component 'blk_mem_gen_v8_4_9' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/synth/AlgoParameterRAM.vhd:252] INFO: [Synth 8-256] done synthesizing module 'AlgoParameterRAM' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/synth/AlgoParameterRAM.vhd:76] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOB_RDOUT_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic TOB_RDOUT_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ALGOLIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ALGOLIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic INFRASTRUCTURE_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic INFRASTRUCTURE_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic USR_IP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic USR_IP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic FLAVOUR WARNING: [Synth 8-7129] Port CLKB in module blk_mem_output_block is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR_I in module blk_mem_output_block is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR_I in module blk_mem_output_block is either unconnected or has no load WARNING: [Synth 8-7129] Port RDADDRECC_I[2] in module blk_mem_output_block is either unconnected or has no load WARNING: [Synth 8-7129] Port RDADDRECC_I[1] in module blk_mem_output_block is either unconnected or has no load WARNING: [Synth 8-7129] Port RDADDRECC_I[0] in module blk_mem_output_block is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized2 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized1 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port SBITERR in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port DBITERR in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRA in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port SSRB in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port SLEEP in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTSBITERR in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port INJECTDBITERR in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port ECCPIPECE in module blk_mem_gen_prim_wrapper is either unconnected or has no load WARNING: [Synth 8-7129] Port RSTA[0] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEA[3] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEA[2] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEA[1] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port RSTB[0] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[28] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[27] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[26] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[25] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[24] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[23] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[22] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[21] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[20] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[19] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[18] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[17] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[16] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[15] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[14] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[13] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[12] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[11] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[10] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[9] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[8] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[7] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[6] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[5] in module blk_mem_gen_generic_cstr is either unconnected or has no load WARNING: [Synth 8-7129] Port WEB[4] in module blk_mem_gen_generic_cstr is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2962.387 ; gain = 700.242 ; free physical = 22453 ; free virtual = 40612 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2962.387 ; gain = 700.242 ; free physical = 22453 ; free virtual = 40612 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2962.387 ; gain = 700.242 ; free physical = 22453 ; free virtual = 40612 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2962.387 ; gain = 0.000 ; free physical = 22453 ; free virtual = 40612 INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM_ooc.xdc] for cell 'U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/AlgoParameterRAM_synth_1/dont_touch.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/AlgoParameterRAM_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3026.418 ; gain = 0.000 ; free physical = 22492 ; free virtual = 40651 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3026.418 ; gain = 0.000 ; free physical = 22492 ; free virtual = 40651 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 3026.418 ; gain = 764.273 ; free physical = 22522 ; free virtual = 40682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22522 ; free virtual = 40682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/AlgoParameterRAM_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22522 ; free virtual = 40681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22521 ; free virtual = 40682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22531 ; free virtual = 40691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22573 ; free virtual = 40733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22573 ; free virtual = 40733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 3034.422 ; gain = 772.277 ; free physical = 22573 ; free virtual = 40733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22513 ; free virtual = 40673 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22513 ; free virtual = 40673 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22509 ; free virtual = 40669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22509 ; free virtual = 40669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22509 ; free virtual = 40669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22509 ; free virtual = 40669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB36E1 | 8| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.234 ; gain = 862.090 ; free physical = 22509 ; free virtual = 40669 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 152 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.234 ; gain = 798.059 ; free physical = 22509 ; free virtual = 40669 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3124.242 ; gain = 862.090 ; free physical = 22509 ; free virtual = 40669 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3124.242 ; gain = 0.000 ; free physical = 22640 ; free virtual = 40800 INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3133.141 ; gain = 0.000 ; free physical = 22681 ; free virtual = 40841 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: a7dfe9ae INFO: [Common 17-83] Releasing license: Synthesis 22 Infos, 151 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 3133.141 ; gain = 1348.660 ; free physical = 22681 ; free virtual = 40841 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2500.270; main = 2346.992; forked = 291.051 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3966.164; main = 3133.145; forked = 931.738 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/AlgoParameterRAM_synth_1/AlgoParameterRAM.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP AlgoParameterRAM, cache-ID = ce8f7b6c93a9ef9a INFO: [Coretcl 2-1174] Renamed 20 cell refs. INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.1/efex_processor.1.runs/AlgoParameterRAM_synth_1/AlgoParameterRAM.dcp' has been generated. INFO: [Vivado 12-24828] Executing command : report_utilization -file AlgoParameterRAM_utilization_synth.rpt -pb AlgoParameterRAM_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed Apr 2 17:06:39 2025...