Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024 | Date : Wed Apr 2 19:19:34 2025 | Host : runner-knmyf9bh-project-27372-concurrent-1-4ut7r744 running 64-bit Ubuntu 22.04.5 LTS | Command : report_utilization -hierarchical -hierarchical_percentages -file /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.2-v1.7.1-4A2152C/reports/hierarchical_utilization.txt | Design : top_efex_processor | Device : xc7vx550tffg1927-2 | Speed File : -2 | Design State : Routed -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-------------------------------------------------------------------------------------------+------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-------------------------------------------------------------------------------------------+------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ | top_efex_processor | (top) | 201817(58.26%) | 187896(54.24%) | 0(0.00%) | 13921(7.99%) | 273522(39.48%) | 717(60.76%) | 83(3.52%) | 96(3.33%) | | (top_efex_processor) | (top) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 283(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_PATH_IF.data_path_Module | data_path_block | 138782(40.06%) | 125033(36.09%) | 0(0.00%) | 13749(7.89%) | 180380(26.04%) | 8(0.68%) | 0(0.00%) | 96(3.33%) | | (DATA_PATH_IF.data_path_Module) | data_path_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Sorting_Module | IPBusTopSortingModule | 3245(0.94%) | 3232(0.93%) | 0(0.00%) | 13(0.01%) | 6825(0.99%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (Sorting_Module) | IPBusTopSortingModule | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BCN_Delay | GeneralDelay__parameterized6 | 29(0.01%) | 17(0.01%) | 0(0.00%) | 12(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_SORTING_REGISTERS | ipbus_ctrlreg_v__parameterized9 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_eg | TopSortingModule | 1593(0.46%) | 1592(0.46%) | 0(0.00%) | 1(0.01%) | 3341(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_eg) | TopSortingModule | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 290(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5888 | 222(0.06%) | 221(0.06%) | 0(0.00%) | 1(0.01%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5888 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5907 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5908 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5889 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5889 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5905 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5906 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5890 | 216(0.06%) | 216(0.06%) | 0(0.00%) | 0(0.00%) | 437(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5890 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5903 | 124(0.04%) | 124(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5904 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0_5891 | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0_5891 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5901 | 132(0.04%) | 132(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5902 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5892 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5892 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5899 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5900 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5893 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5893 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5897 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5898 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5894 | 227(0.07%) | 227(0.07%) | 0(0.00%) | 0(0.00%) | 438(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5894 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5895 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5896 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TopSorting_tau | TopSortingModule_5867 | 1579(0.46%) | 1579(0.46%) | 0(0.00%) | 0(0.00%) | 3335(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TopSorting_tau) | TopSortingModule_5867 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 288(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5868 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 433(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5868 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5886 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5887 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter_5869 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter_5869 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5884 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5885 | 88(0.03%) | 88(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER | ParallelSorter_5870 | 217(0.06%) | 217(0.06%) | 0(0.00%) | 0(0.00%) | 435(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifAll.sorter_gen[1].PAR_SORTER) | ParallelSorter_5870 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5882 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5883 | 90(0.03%) | 90(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized0 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized0 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5880 | 133(0.04%) | 133(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5881 | 92(0.03%) | 92(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized0_5871 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized0_5871 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5878 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5879 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER | ParallelSorter__parameterized0_5872 | 226(0.07%) | 226(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[2].PAR_SORTER) | ParallelSorter__parameterized0_5872 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5876 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5877 | 94(0.03%) | 94(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER | ParallelSorter__parameterized0_5873 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 436(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[2].ifFirst.sorter_gen0[3].PAR_SORTER) | ParallelSorter__parameterized0_5873 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_5874 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_5875 | 95(0.03%) | 95(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | algorithm_block | IPBusTopAlgoModule | 114185(32.96%) | 112947(32.61%) | 0(0.00%) | 1238(0.71%) | 136031(19.63%) | 8(0.68%) | 0(0.00%) | 96(3.33%) | | (algorithm_block) | IPBusTopAlgoModule | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | INPUT_STAGE | AlgoInputStage | 5322(1.54%) | 5322(1.54%) | 0(0.00%) | 0(0.00%) | 19478(2.81%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (INPUT_STAGE) | AlgoInputStage | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].EnergyConverterH | EnergyConverter | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1604 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1605 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1606 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1607 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1608 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1609 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1610 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1611 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1612 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1613 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].EnergyConverterH | EnergyConverter_1614 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1615 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1616 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1617 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1618 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1619 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1620 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1621 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1622 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1623 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1624 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].EnergyConverterH | EnergyConverter_1625 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1626 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1627 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1628 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1629 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1630 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1631 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1632 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1633 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1634 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1635 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].EnergyConverterH | EnergyConverter_1636 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1637 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1638 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1639 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1640 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1641 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1642 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1643 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1644 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1645 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1646 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].EnergyConverterH | EnergyConverter_1647 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1648 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1649 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1650 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1651 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1652 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1653 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1654 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1655 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1656 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1657 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].EnergyConverterH | EnergyConverter_1658 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1659 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1660 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1661 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1662 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1663 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1664 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1665 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1666 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1667 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1668 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].EnergyConverterH | EnergyConverter_1669 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1670 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1671 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1672 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1673 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1674 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1675 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1676 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1677 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1678 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1679 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].EnergyConverterH | EnergyConverter_1680 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1681 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1682 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1683 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1684 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1685 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1686 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1687 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1688 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1689 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1690 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].EnergyConverterH | EnergyConverter_1691 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1692 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1693 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1694 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1695 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1696 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1697 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1698 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1699 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1700 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1701 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].EnergyConverterH | EnergyConverter_1702 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1703 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1704 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1705 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1706 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1707 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1708 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1709 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1710 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1711 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[0].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1712 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].EnergyConverterH | EnergyConverter_1713 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1714 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1715 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1716 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1717 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1718 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1719 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1720 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1721 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1722 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1723 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].EnergyConverterH | EnergyConverter_1724 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1725 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1726 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1727 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1728 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1729 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1730 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1731 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1732 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1733 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1734 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].EnergyConverterH | EnergyConverter_1735 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1736 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1737 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1738 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1739 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1740 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1741 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1742 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1743 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1744 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1745 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].EnergyConverterH | EnergyConverter_1746 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1747 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1748 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1749 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1750 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1751 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1752 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1753 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1754 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1755 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1756 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].EnergyConverterH | EnergyConverter_1757 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1758 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1759 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1760 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1761 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1762 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1763 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1764 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1765 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1766 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1767 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].EnergyConverterH | EnergyConverter_1768 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1769 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1770 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1771 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1772 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1773 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1774 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1775 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1776 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1777 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1778 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].EnergyConverterH | EnergyConverter_1779 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1780 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1781 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1782 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1783 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1784 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1785 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1786 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1787 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1788 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1789 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].EnergyConverterH | EnergyConverter_1790 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1791 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1792 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1793 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1794 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1795 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1796 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1797 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1798 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1799 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1800 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].EnergyConverterH | EnergyConverter_1801 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1802 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1803 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1804 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1805 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1806 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1807 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1808 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1809 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1810 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1811 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].EnergyConverterH | EnergyConverter_1812 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1813 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1814 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1815 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1816 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1817 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1818 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1819 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1820 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1821 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[1].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1822 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].EnergyConverterH | EnergyConverter_1823 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1824 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1825 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1826 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1827 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1828 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1829 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1830 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1831 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1832 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1833 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].EnergyConverterH | EnergyConverter_1834 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1835 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1836 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1837 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1838 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1839 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1840 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1841 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1842 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1843 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1844 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].EnergyConverterH | EnergyConverter_1845 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1846 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1847 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1848 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1849 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1850 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1851 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1852 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1853 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1854 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1855 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].EnergyConverterH | EnergyConverter_1856 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1857 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1858 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1859 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1860 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1861 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1862 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1863 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1864 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1865 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1866 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].EnergyConverterH | EnergyConverter_1867 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1868 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1869 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1870 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1871 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1872 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1873 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1874 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1875 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1876 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1877 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].EnergyConverterH | EnergyConverter_1878 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1879 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1880 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1881 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1882 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1883 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1884 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1885 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1886 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1887 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1888 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].EnergyConverterH | EnergyConverter_1889 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_1890 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_1891 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_1892 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_1893 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_1894 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_1895 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_1896 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_1897 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_1898 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_1899 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].EnergyConverterH | EnergyConverter_1900 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_1901 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_1902 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_1903 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_1904 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_1905 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_1906 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_1907 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_1908 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_1909 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_1910 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].EnergyConverterH | EnergyConverter_1911 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_1912 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_1913 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_1914 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_1915 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_1916 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_1917 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_1918 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_1919 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_1920 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_1921 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].EnergyConverterH | EnergyConverter_1922 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_1923 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_1924 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_1925 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_1926 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_1927 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_1928 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_1929 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_1930 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_1931 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[2].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_1932 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].EnergyConverterH | EnergyConverter_1933 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_1934 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_1935 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_1936 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_1937 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_1938 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_1939 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_1940 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_1941 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_1942 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_1943 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].EnergyConverterH | EnergyConverter_1944 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_1945 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_1946 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_1947 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_1948 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_1949 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_1950 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_1951 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_1952 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_1953 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_1954 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].EnergyConverterH | EnergyConverter_1955 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_1956 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_1957 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_1958 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_1959 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_1960 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_1961 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_1962 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_1963 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_1964 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_1965 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].EnergyConverterH | EnergyConverter_1966 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_1967 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_1968 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_1969 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_1970 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_1971 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_1972 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_1973 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_1974 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_1975 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_1976 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].EnergyConverterH | EnergyConverter_1977 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_1978 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_1979 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_1980 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_1981 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_1982 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_1983 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_1984 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_1985 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_1986 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_1987 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].EnergyConverterH | EnergyConverter_1988 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_1989 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_1990 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_1991 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_1992 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_1993 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_1994 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_1995 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_1996 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_1997 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_1998 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].EnergyConverterH | EnergyConverter_1999 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2000 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2001 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2002 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2003 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2004 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2005 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2006 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2007 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2008 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2009 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].EnergyConverterH | EnergyConverter_2010 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2011 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2012 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2013 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2014 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2015 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2016 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2017 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2018 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2019 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2020 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].EnergyConverterH | EnergyConverter_2021 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2022 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2023 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2024 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2025 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2026 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2027 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2028 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2029 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2030 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2031 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].EnergyConverterH | EnergyConverter_2032 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2033 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2034 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2035 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2036 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2037 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2038 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2039 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2040 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2041 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[3].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2042 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].EnergyConverterH | EnergyConverter_2043 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2044 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2045 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2046 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2047 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2048 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2049 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2050 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2051 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2052 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2053 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].EnergyConverterH | EnergyConverter_2054 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2055 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2056 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2057 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2058 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2059 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2060 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2061 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2062 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2063 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2064 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].EnergyConverterH | EnergyConverter_2065 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2066 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2067 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2068 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2069 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2070 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2071 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2072 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2073 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2074 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2075 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].EnergyConverterH | EnergyConverter_2076 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2077 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2078 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2079 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2080 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2081 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2082 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2084 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2085 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2086 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].EnergyConverterH | EnergyConverter_2087 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2088 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2089 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2090 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2091 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2092 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2093 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2094 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2095 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2096 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2097 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].EnergyConverterH | EnergyConverter_2098 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2099 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2100 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2101 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2102 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2103 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2104 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2105 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2106 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2107 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2108 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].EnergyConverterH | EnergyConverter_2109 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2110 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2111 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2112 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2113 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2114 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2115 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2116 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2117 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2118 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2119 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].EnergyConverterH | EnergyConverter_2120 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2121 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2122 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2123 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2124 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2125 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2126 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2127 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2128 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2129 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2130 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].EnergyConverterH | EnergyConverter_2131 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2132 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2133 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2134 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2135 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2136 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2137 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2138 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2139 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2140 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2141 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].EnergyConverterH | EnergyConverter_2142 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2143 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2144 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2145 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2146 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2147 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2148 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2149 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2150 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2151 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[4].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2152 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].EnergyConverterH | EnergyConverter_2153 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer0_for[0].EnergyConverter0 | EnergyConverter_2154 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[0].EnergyConverter1 | EnergyConverter_2155 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[1].EnergyConverter1 | EnergyConverter_2156 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[2].EnergyConverter1 | EnergyConverter_2157 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer1_for[3].EnergyConverter1 | EnergyConverter_2158 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[0].EnergyConverter2 | EnergyConverter_2159 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[1].EnergyConverter2 | EnergyConverter_2160 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[2].EnergyConverter2 | EnergyConverter_2161 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer2_for[3].EnergyConverter2 | EnergyConverter_2162 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[0].layer3_for[0].EnergyConverter3 | EnergyConverter_2163 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].EnergyConverterH | EnergyConverter_2164 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer0_for[0].EnergyConverter0 | EnergyConverter_2165 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[0].EnergyConverter1 | EnergyConverter_2166 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[1].EnergyConverter1 | EnergyConverter_2167 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[2].EnergyConverter1 | EnergyConverter_2168 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer1_for[3].EnergyConverter1 | EnergyConverter_2169 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[0].EnergyConverter2 | EnergyConverter_2170 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[1].EnergyConverter2 | EnergyConverter_2171 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[2].EnergyConverter2 | EnergyConverter_2172 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer2_for[3].EnergyConverter2 | EnergyConverter_2173 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[1].layer3_for[0].EnergyConverter3 | EnergyConverter_2174 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].EnergyConverterH | EnergyConverter_2175 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer0_for[0].EnergyConverter0 | EnergyConverter_2176 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[0].EnergyConverter1 | EnergyConverter_2177 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[1].EnergyConverter1 | EnergyConverter_2178 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[2].EnergyConverter1 | EnergyConverter_2179 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer1_for[3].EnergyConverter1 | EnergyConverter_2180 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[0].EnergyConverter2 | EnergyConverter_2181 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[1].EnergyConverter2 | EnergyConverter_2182 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[2].EnergyConverter2 | EnergyConverter_2183 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer2_for[3].EnergyConverter2 | EnergyConverter_2184 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[2].layer3_for[0].EnergyConverter3 | EnergyConverter_2185 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].EnergyConverterH | EnergyConverter_2186 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer0_for[0].EnergyConverter0 | EnergyConverter_2187 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[0].EnergyConverter1 | EnergyConverter_2188 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[1].EnergyConverter1 | EnergyConverter_2189 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[2].EnergyConverter1 | EnergyConverter_2190 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer1_for[3].EnergyConverter1 | EnergyConverter_2191 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[0].EnergyConverter2 | EnergyConverter_2192 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[1].EnergyConverter2 | EnergyConverter_2193 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[2].EnergyConverter2 | EnergyConverter_2194 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer2_for[3].EnergyConverter2 | EnergyConverter_2195 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[3].layer3_for[0].EnergyConverter3 | EnergyConverter_2196 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].EnergyConverterH | EnergyConverter_2197 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer0_for[0].EnergyConverter0 | EnergyConverter_2198 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[0].EnergyConverter1 | EnergyConverter_2199 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[1].EnergyConverter1 | EnergyConverter_2200 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[2].EnergyConverter1 | EnergyConverter_2201 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer1_for[3].EnergyConverter1 | EnergyConverter_2202 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[0].EnergyConverter2 | EnergyConverter_2203 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[1].EnergyConverter2 | EnergyConverter_2204 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[2].EnergyConverter2 | EnergyConverter_2205 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer2_for[3].EnergyConverter2 | EnergyConverter_2206 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[4].layer3_for[0].EnergyConverter3 | EnergyConverter_2207 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].EnergyConverterH | EnergyConverter_2208 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer0_for[0].EnergyConverter0 | EnergyConverter_2209 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[0].EnergyConverter1 | EnergyConverter_2210 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[1].EnergyConverter1 | EnergyConverter_2211 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[2].EnergyConverter1 | EnergyConverter_2212 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer1_for[3].EnergyConverter1 | EnergyConverter_2213 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[0].EnergyConverter2 | EnergyConverter_2214 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[1].EnergyConverter2 | EnergyConverter_2215 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[2].EnergyConverter2 | EnergyConverter_2216 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer2_for[3].EnergyConverter2 | EnergyConverter_2217 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[5].layer3_for[0].EnergyConverter3 | EnergyConverter_2218 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].EnergyConverterH | EnergyConverter_2219 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer0_for[0].EnergyConverter0 | EnergyConverter_2220 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[0].EnergyConverter1 | EnergyConverter_2221 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[1].EnergyConverter1 | EnergyConverter_2222 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[2].EnergyConverter1 | EnergyConverter_2223 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer1_for[3].EnergyConverter1 | EnergyConverter_2224 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[0].EnergyConverter2 | EnergyConverter_2225 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[1].EnergyConverter2 | EnergyConverter_2226 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[2].EnergyConverter2 | EnergyConverter_2227 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer2_for[3].EnergyConverter2 | EnergyConverter_2228 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[6].layer3_for[0].EnergyConverter3 | EnergyConverter_2229 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].EnergyConverterH | EnergyConverter_2230 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer0_for[0].EnergyConverter0 | EnergyConverter_2231 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[0].EnergyConverter1 | EnergyConverter_2232 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[1].EnergyConverter1 | EnergyConverter_2233 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[2].EnergyConverter1 | EnergyConverter_2234 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer1_for[3].EnergyConverter1 | EnergyConverter_2235 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[0].EnergyConverter2 | EnergyConverter_2236 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[1].EnergyConverter2 | EnergyConverter_2237 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[2].EnergyConverter2 | EnergyConverter_2238 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer2_for[3].EnergyConverter2 | EnergyConverter_2239 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[7].layer3_for[0].EnergyConverter3 | EnergyConverter_2240 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].EnergyConverterH | EnergyConverter_2241 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer0_for[0].EnergyConverter0 | EnergyConverter_2242 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[0].EnergyConverter1 | EnergyConverter_2243 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[1].EnergyConverter1 | EnergyConverter_2244 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[2].EnergyConverter1 | EnergyConverter_2245 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer1_for[3].EnergyConverter1 | EnergyConverter_2246 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[0].EnergyConverter2 | EnergyConverter_2247 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[1].EnergyConverter2 | EnergyConverter_2248 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[2].EnergyConverter2 | EnergyConverter_2249 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer2_for[3].EnergyConverter2 | EnergyConverter_2250 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[8].layer3_for[0].EnergyConverter3 | EnergyConverter_2251 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].EnergyConverterH | EnergyConverter_2252 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer0_for[0].EnergyConverter0 | EnergyConverter_2253 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[0].EnergyConverter1 | EnergyConverter_2254 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[1].EnergyConverter1 | EnergyConverter_2255 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[2].EnergyConverter1 | EnergyConverter_2256 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer1_for[3].EnergyConverter1 | EnergyConverter_2257 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[0].EnergyConverter2 | EnergyConverter_2258 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[1].EnergyConverter2 | EnergyConverter_2259 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[2].EnergyConverter2 | EnergyConverter_2260 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer2_for[3].EnergyConverter2 | EnergyConverter_2261 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | column_for[5].row_for[9].layer3_for[0].EnergyConverter3 | EnergyConverter_2262 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_PARAMETER_RAM | AlgoParameterRAM_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (IPBUS_ALGO_PARAMETER_RAM) | AlgoParameterRAM_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_PARAMETER_RAM | AlgoParameterRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | AlgoParameterRAM_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | AlgoParameterRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | AlgoParameterRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | AlgoParameterRAM_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | AlgoParameterRAM_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized8 | 17222(4.97%) | 17222(4.97%) | 0(0.00%) | 0(0.00%) | 2058(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_FABRIC | ipbus_fabric_sel__parameterized3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | LOAD_GENERATOR | LoadGenerator | 58(0.02%) | 56(0.02%) | 0(0.00%) | 2(0.01%) | 130(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RATE_MONITOR | AlgoRateMonitor | 4885(1.41%) | 4884(1.41%) | 0(0.00%) | 1(0.01%) | 3234(0.47%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (RATE_MONITOR) | AlgoRateMonitor | 2(0.01%) | 1(0.01%) | 0(0.00%) | 1(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_ALGO_REGISTERS | ipbus_ctrlreg_v__parameterized7 | 149(0.04%) | 149(0.04%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | NORMALISATION_CNT | counter | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_EG | counter_1508 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[0].CNT_TAU | counter_1509 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_EG | counter_1510 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[1].CNT_TAU | counter_1511 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_EG | counter_1512 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[2].CNT_TAU | counter_1513 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_EG | counter_1514 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[3].CNT_TAU | counter_1515 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_EG | counter_1516 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[4].CNT_TAU | counter_1517 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_EG | counter_1518 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[5].CNT_TAU | counter_1519 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_EG | counter_1520 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[6].CNT_TAU | counter_1521 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_EG | counter_1522 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[0].phi_for[7].CNT_TAU | counter_1523 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_EG | counter_1524 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[0].CNT_TAU | counter_1525 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_EG | counter_1526 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[1].CNT_TAU | counter_1527 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_EG | counter_1528 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[2].CNT_TAU | counter_1529 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_EG | counter_1530 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[3].CNT_TAU | counter_1531 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_EG | counter_1532 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[4].CNT_TAU | counter_1533 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_EG | counter_1534 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[5].CNT_TAU | counter_1535 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_EG | counter_1536 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[6].CNT_TAU | counter_1537 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_EG | counter_1538 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[1].phi_for[7].CNT_TAU | counter_1539 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_EG | counter_1540 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[0].CNT_TAU | counter_1541 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_EG | counter_1542 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[1].CNT_TAU | counter_1543 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_EG | counter_1544 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[2].CNT_TAU | counter_1545 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_EG | counter_1546 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[3].CNT_TAU | counter_1547 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_EG | counter_1548 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[4].CNT_TAU | counter_1549 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_EG | counter_1550 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[5].CNT_TAU | counter_1551 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_EG | counter_1552 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[6].CNT_TAU | counter_1553 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_EG | counter_1554 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[2].phi_for[7].CNT_TAU | counter_1555 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_EG | counter_1556 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[0].CNT_TAU | counter_1557 | 113(0.03%) | 113(0.03%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_EG | counter_1558 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[1].CNT_TAU | counter_1559 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_EG | counter_1560 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[2].CNT_TAU | counter_1561 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_EG | counter_1562 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[3].CNT_TAU | counter_1563 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_EG | counter_1564 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[4].CNT_TAU | counter_1565 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_EG | counter_1566 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[5].CNT_TAU | counter_1567 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_EG | counter_1568 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[6].CNT_TAU | counter_1569 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_EG | counter_1570 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[3].phi_for[7].CNT_TAU | counter_1571 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_EG | counter_1572 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[0].CNT_TAU | counter_1573 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 53(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_EG | counter_1574 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[1].CNT_TAU | counter_1575 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_EG | counter_1576 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[2].CNT_TAU | counter_1577 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_EG | counter_1578 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[3].CNT_TAU | counter_1579 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_EG | counter_1580 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[4].CNT_TAU | counter_1581 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_EG | counter_1582 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[5].CNT_TAU | counter_1583 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_EG | counter_1584 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[6].CNT_TAU | counter_1585 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_EG | counter_1586 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[4].phi_for[7].CNT_TAU | counter_1587 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_EG | counter_1588 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[0].CNT_TAU | counter_1589 | 50(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_EG | counter_1590 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[1].CNT_TAU | counter_1591 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_EG | counter_1592 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[2].CNT_TAU | counter_1593 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_EG | counter_1594 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[3].CNT_TAU | counter_1595 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_EG | counter_1596 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[4].CNT_TAU | counter_1597 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_EG | counter_1598 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[5].CNT_TAU | counter_1599 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_EG | counter_1600 | 40(0.01%) | 40(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[6].CNT_TAU | counter_1601 | 42(0.01%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_EG | counter_1602 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | eta_for[5].phi_for[7].CNT_TAU | counter_1603 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOP_ALGO_MODULE | TopAlgoModule | 81784(23.61%) | 80549(23.25%) | 0(0.00%) | 1235(0.71%) | 103432(14.93%) | 0(0.00%) | 0(0.00%) | 96(3.33%) | | (TOP_ALGO_MODULE) | TopAlgoModule | 11562(3.34%) | 11562(3.34%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[0].AGLO_CORE_EG | AlgoCore_eg__xdcDup__1 | 5418(1.56%) | 5342(1.54%) | 0(0.00%) | 76(0.04%) | 7428(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[0].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__1 | 1699(0.49%) | 1699(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5647 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_5648 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5649 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD49 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD50 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD55 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD56 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__2 | 1331(0.38%) | 1331(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__2 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5740 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5741 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5742 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5743 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5744 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5745 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5746 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5747 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5748 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5749 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5750 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5751 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5752 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5753 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5754 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5755 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5756 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5757 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5758 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5759 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5760 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5761 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5762 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5763 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5764 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5765 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5766 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5767 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5768 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5769 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5770 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5771 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5772 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5773 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5774 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5775 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5776 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5777 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5778 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5779 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5780 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5781 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5782 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_5783 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_5784 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_5785 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_5786 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_5787 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_5788 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_5789 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_5790 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_5791 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_5792 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5793 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_5794 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_5795 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5796 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5797 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5798 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5799 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5800 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5801 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_5802 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_5803 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_5804 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_5805 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_5806 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_5807 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_5808 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_5809 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_5810 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_5811 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_5812 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_5813 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_5814 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_5815 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_5816 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_5817 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_5818 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_5819 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_5820 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_5821 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_5822 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_5823 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_5824 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_5825 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_5826 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_5827 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_5828 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_5829 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_5830 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_5831 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_5832 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_5833 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_5834 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_5835 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_5836 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_5837 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_5838 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_5839 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_5840 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_5841 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_5842 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_5843 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_5844 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_5845 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_5846 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_5847 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_5848 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_5849 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_5850 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_5851 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_5852 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_5853 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_5854 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_5855 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_5856 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_5857 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_5858 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_5859 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_5860 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_5861 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_5862 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_5863 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_5864 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_5865 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_5866 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_5650 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_5650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5724 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5731 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5732 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5733 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5734 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5735 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5736 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5737 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5738 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5739 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_5651 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_5651 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5714 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5715 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5716 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5717 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5718 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5719 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5720 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5652 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5652 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5704 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5705 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5706 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5653 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5694 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5695 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5696 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5697 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5698 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5699 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5700 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5654 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5680 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5681 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5682 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5683 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5684 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5685 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5655 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5655 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5667 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5668 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5669 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5670 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5671 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5672 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5673 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_5656 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_5657 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5658 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__1 | 3361(0.97%) | 3282(0.95%) | 0(0.00%) | 79(0.05%) | 3967(0.57%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__1 | 504(0.15%) | 504(0.15%) | 0(0.00%) | 0(0.00%) | 86(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__2 | 2695(0.78%) | 2645(0.76%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_5435 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5635 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5636 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5638 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5639 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5640 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5641 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5642 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5643 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5644 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5645 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_5436 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_5437 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_5438 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_5439 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_5440 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_5441 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_5442 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_5443 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_5444 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_5445 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5446 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5616 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5617 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5619 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5620 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5621 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5622 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5623 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5624 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5625 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5626 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5627 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5628 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5629 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5630 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5631 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5632 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5633 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5634 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_5447 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5588 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5589 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5590 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5591 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5592 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5593 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5594 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5595 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5596 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5597 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5598 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5599 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5600 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5601 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5602 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5603 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5604 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5605 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5606 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5607 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5608 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5609 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5610 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5611 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5612 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5613 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5614 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5615 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_5448 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5582 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5583 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5585 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5586 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_5449 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5570 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5571 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5573 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5574 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5575 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5576 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5577 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5578 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5579 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5580 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_5450 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5558 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5559 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5561 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5562 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5563 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5564 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5565 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5566 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5567 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5568 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_5451 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5546 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5547 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5549 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5550 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5551 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5552 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5553 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5554 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5555 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5556 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_5452 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5534 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5535 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5537 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5538 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5539 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5540 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5541 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5542 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5543 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5544 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_5453 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5522 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5523 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5525 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5526 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5527 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5528 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5529 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5530 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5531 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5532 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_5454 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5510 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5511 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5513 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5514 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5515 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5516 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5517 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5518 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5519 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5520 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_5455 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5499 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5500 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5502 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5503 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5504 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5505 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5506 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5507 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5508 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5509 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_5456 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5487 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5488 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5490 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5491 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5492 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5493 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5494 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5495 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5496 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5497 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_5457 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5484 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5485 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5486 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_5458 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5481 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5482 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5483 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_5459 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5478 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5479 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5480 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_5460 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5475 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5476 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5477 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_5461 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5474 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_5462 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5473 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_5463 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5472 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_5464 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5469 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5470 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5471 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_5465 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5466 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5467 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5468 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_5413 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_5414 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_5415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_5416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_5417 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 220(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_5419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_5421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_5422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5423 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_5424 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_5425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_5426 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_5427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_5428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_5429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_5430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_5431 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_5432 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_5433 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_5434 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_5418 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[1].AGLO_CORE_EG | AlgoCore_eg__xdcDup__2 | 5418(1.56%) | 5342(1.54%) | 0(0.00%) | 76(0.04%) | 7417(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[1].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__2 | 1699(0.49%) | 1699(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_5193 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_5194 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_5195 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD65 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD66 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD67 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD68 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__3 | 1331(0.38%) | 1331(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__3 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5286 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5287 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5288 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5289 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5290 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5291 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5292 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5293 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5294 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5295 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5296 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5297 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5298 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5299 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5300 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5301 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5302 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5303 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5304 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5305 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5306 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5307 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5308 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5309 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5310 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5311 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5312 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5313 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5314 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5315 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5316 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_5317 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_5318 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_5319 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_5320 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_5321 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_5322 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_5323 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_5324 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_5325 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_5326 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_5327 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_5328 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_5329 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_5330 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_5331 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_5332 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_5333 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_5334 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_5335 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_5336 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_5337 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_5338 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_5339 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_5340 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_5341 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_5342 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_5343 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_5344 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_5345 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_5346 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_5347 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_5348 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_5349 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_5350 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_5351 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_5352 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_5353 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_5354 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_5355 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_5356 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_5357 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_5358 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_5359 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_5360 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_5361 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_5362 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_5363 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_5364 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_5365 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_5366 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_5367 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_5368 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_5369 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_5370 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_5371 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_5372 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_5373 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_5374 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_5375 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_5376 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_5377 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_5378 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_5379 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_5380 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_5381 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_5382 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_5383 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_5384 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_5385 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_5386 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_5387 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_5388 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_5389 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_5390 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_5391 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_5392 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_5393 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_5394 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_5395 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_5396 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_5397 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_5398 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_5399 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_5400 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_5401 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_5402 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_5403 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_5404 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_5405 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_5406 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_5407 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_5408 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_5409 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_5410 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_5411 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_5412 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_5196 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_5196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5270 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5277 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5278 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5279 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5280 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_5281 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_5282 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5283 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5284 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5285 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_5197 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_5197 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5260 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5261 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5262 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5263 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5264 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5265 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5266 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_5198 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_5198 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5250 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5251 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5252 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_5199 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_5199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5240 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5241 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5242 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5243 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5244 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5245 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5246 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_5200 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_5200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5226 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5227 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5228 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5229 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5230 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5231 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_5201 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 271(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_5201 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5213 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5214 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5215 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5216 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5217 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5218 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_5219 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_5202 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_5203 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_5204 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__2 | 3361(0.97%) | 3282(0.95%) | 0(0.00%) | 79(0.05%) | 3862(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__2 | 504(0.15%) | 504(0.15%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__3 | 2695(0.78%) | 2645(0.76%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4981 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5181 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5182 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5184 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5185 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5186 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5187 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5188 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5189 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5190 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5191 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4982 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4983 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4984 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4985 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4986 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4987 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4988 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4989 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4990 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4991 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4992 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5162 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5163 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5165 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5166 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5167 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5168 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5169 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5170 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5171 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5172 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5173 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5174 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5175 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5176 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5177 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5178 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5179 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5180 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4993 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5134 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5135 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5136 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5137 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5138 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5139 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_5140 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5141 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5142 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5143 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5144 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5145 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5146 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_5147 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_5148 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_5149 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_5150 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_5151 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_5152 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_5153 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_5154 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_5155 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_5156 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_5157 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_5158 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_5159 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_5160 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_5161 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4994 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5128 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5129 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5131 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5132 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4995 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5116 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5117 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5119 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5120 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5121 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5122 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5123 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5124 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5125 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5126 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4996 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5104 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5105 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5107 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5108 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5109 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5110 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5111 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5112 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5113 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5114 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4997 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5092 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5093 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5095 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5096 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5097 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5098 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5099 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5100 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5101 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5102 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4998 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5080 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5081 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5083 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5084 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5085 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5086 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5087 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5088 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5089 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5090 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4999 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5068 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5069 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5071 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5072 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5073 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5074 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5075 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5076 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5077 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5078 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_5000 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5056 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5057 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5059 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5060 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5061 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5062 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5063 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5064 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5065 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5066 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_5001 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5045 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5046 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5048 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5049 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5050 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5051 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5052 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5053 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5054 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5055 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_5002 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5033 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5034 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_5036 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_5037 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_5038 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_5039 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_5040 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_5041 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_5042 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_5043 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_5003 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5030 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5031 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5032 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_5004 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5027 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5028 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5029 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_5005 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5024 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5025 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5026 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_5006 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5021 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5022 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5023 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_5007 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5020 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_5008 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5019 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_5009 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5018 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_5010 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5015 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5016 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5017 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_5011 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_5012 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_5013 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_5014 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4959 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4960 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4961 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4963 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4969 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4970 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4972 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4977 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4978 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4979 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4980 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4964 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[2].AGLO_CORE_EG | AlgoCore_eg__xdcDup__3 | 5417(1.56%) | 5341(1.54%) | 0(0.00%) | 76(0.04%) | 7413(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[2].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__3 | 1699(0.49%) | 1699(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4739 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_4740 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4741 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD82 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD83 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__4 | 1330(0.38%) | 1330(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__4 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4832 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4833 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4834 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4835 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4836 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4837 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4838 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4839 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4840 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4841 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4842 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4843 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4844 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4845 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4846 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4847 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4848 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4849 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4850 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4851 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4852 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4853 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4854 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4855 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4856 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4857 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4858 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4859 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4860 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4861 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4862 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4863 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4864 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4865 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4866 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4867 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4868 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4869 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4870 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4871 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4872 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4873 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4874 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_4875 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_4876 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_4877 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_4878 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_4879 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_4880 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_4881 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_4882 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_4883 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_4884 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4885 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_4886 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_4887 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_4888 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_4889 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_4890 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_4891 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_4892 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_4893 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_4894 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_4895 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_4896 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_4897 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_4898 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_4899 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_4900 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_4901 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_4902 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_4903 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_4904 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_4905 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_4906 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_4907 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_4908 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4909 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4910 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4911 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4912 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4913 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4914 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4915 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4916 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4917 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4918 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4919 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4920 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4921 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4922 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4923 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4924 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4925 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4926 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4927 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4928 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4929 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4930 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4931 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4932 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4933 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4934 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4935 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4936 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4937 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4938 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4939 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4940 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4941 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4942 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4943 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4944 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4945 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4946 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4947 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4948 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4949 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4950 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4951 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4952 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4953 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4954 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4955 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4956 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4957 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4958 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_4742 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_4742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4816 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4823 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4824 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4825 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4826 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4827 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4828 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4829 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4830 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4831 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_4743 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_4743 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4806 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4807 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4808 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4809 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4810 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4811 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4812 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4744 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4744 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4796 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4797 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4798 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4745 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4786 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4787 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4788 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4789 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4790 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4791 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4792 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4746 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4772 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4773 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4774 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4775 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4776 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4777 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4747 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4747 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4759 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4760 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4761 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4762 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4763 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4764 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4765 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_4748 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_4749 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4750 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__3 | 3360(0.97%) | 3282(0.95%) | 0(0.00%) | 78(0.04%) | 3934(0.57%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__3 | 504(0.15%) | 504(0.15%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__4 | 2694(0.78%) | 2645(0.76%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4527 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4727 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4728 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4730 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4731 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4732 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4733 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4734 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4735 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4736 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4737 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4528 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4529 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4530 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4531 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4532 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4533 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4534 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4535 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4536 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4537 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4538 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4708 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4709 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4711 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4712 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4713 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4714 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4715 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4716 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4717 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4718 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4719 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4720 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4721 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4722 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4723 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4724 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4725 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4726 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4539 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4680 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4681 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4682 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4683 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4684 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4685 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4686 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4687 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4688 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4689 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4690 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4691 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4692 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4693 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4694 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4695 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4696 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4697 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4698 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4699 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4700 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4701 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4702 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4703 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4704 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4705 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4706 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4707 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4540 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4674 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4675 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4677 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4678 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4541 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4662 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4663 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4665 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4666 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4667 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4668 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4669 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4670 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4671 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4672 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4542 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4650 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4651 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4653 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4654 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4655 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4656 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4657 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4658 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4659 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4660 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4543 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4638 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4639 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4641 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4642 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4643 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4644 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4645 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4646 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4647 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4648 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4544 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4626 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4627 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4629 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4630 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4631 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4632 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4633 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4634 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4635 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4636 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4545 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4614 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4615 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4617 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4618 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4619 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4620 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4621 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4622 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4623 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4624 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_4546 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4602 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4603 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4605 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4606 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4607 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4608 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4609 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4610 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4611 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4612 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_4547 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4591 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4592 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4594 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4595 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4596 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4597 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4598 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4599 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4600 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4601 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_4548 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4579 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4580 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4582 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4583 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4584 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4585 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4586 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4587 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4588 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4589 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_4549 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4576 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4577 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4578 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_4550 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4573 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4574 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4575 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_4551 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4570 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4571 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4572 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_4552 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4567 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4568 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4569 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_4553 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4566 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_4554 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4565 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_4555 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4564 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_4556 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4561 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4562 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4563 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_4557 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4558 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4559 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4560 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4505 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4506 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4507 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4509 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 201(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4515 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4516 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4518 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4523 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4524 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4525 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4526 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4510 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[3].AGLO_CORE_EG | AlgoCore_eg__xdcDup__4 | 5418(1.56%) | 5342(1.54%) | 0(0.00%) | 76(0.04%) | 7414(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[3].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__4 | 1700(0.49%) | 1700(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_4285 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_4286 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_4287 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD84 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD85 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD86 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD87 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD88 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD89 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD90 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD91 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD92 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD93 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD94 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD95 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__5 | 1330(0.38%) | 1330(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__5 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4378 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4379 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4380 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4381 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4382 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4383 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4384 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4385 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4386 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4387 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4388 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4389 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4390 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4391 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4392 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4393 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4394 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4395 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4396 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4397 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4398 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4399 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4400 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4401 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4402 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4403 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4404 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4405 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4406 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4407 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4408 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_4409 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_4410 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_4411 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_4412 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_4413 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_4414 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_4415 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_4416 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_4417 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_4418 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_4419 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_4420 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_4421 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_4422 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_4423 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_4424 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_4425 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_4426 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_4427 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_4428 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_4429 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_4430 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_4431 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_4432 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_4433 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_4434 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_4435 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_4436 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_4437 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_4438 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_4439 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_4440 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_4441 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_4442 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_4443 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_4444 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_4445 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_4446 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_4447 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_4448 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_4449 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_4450 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_4451 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_4452 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_4453 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_4454 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4455 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4456 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4457 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4458 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4459 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4460 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4461 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4462 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4463 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4464 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4465 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4466 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4467 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4468 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4469 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4470 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4471 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4472 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4473 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4474 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4475 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4476 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4477 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4478 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4479 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4480 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4481 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4482 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4483 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4484 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4485 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4486 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4487 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4488 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4489 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4490 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4491 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4492 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4493 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4494 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4495 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4496 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4497 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4498 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4499 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4500 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4501 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4502 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4503 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4504 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_4288 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_4288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4362 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4369 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4370 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4371 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4372 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_4373 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_4374 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4375 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4376 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4377 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_4289 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_4289 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4352 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4353 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4354 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4355 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4356 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4357 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4358 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_4290 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_4290 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4342 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4343 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4344 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_4291 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_4291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4332 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4333 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4334 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4335 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4336 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4337 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4338 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_4292 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_4292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4318 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4319 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4320 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4321 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4322 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4323 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_4293 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 272(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_4293 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4305 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4306 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4307 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4308 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4309 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4310 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_4311 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_4294 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_4295 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_4296 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__4 | 3360(0.97%) | 3281(0.95%) | 0(0.00%) | 79(0.05%) | 3950(0.57%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__4 | 503(0.15%) | 503(0.15%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__5 | 2695(0.78%) | 2645(0.76%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_4073 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4273 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4274 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4276 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4277 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4278 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4279 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4280 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4281 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4282 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4283 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_4074 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_4075 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_4076 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_4077 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_4078 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_4079 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_4080 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_4081 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_4082 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_4083 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4084 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4254 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4255 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4257 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4258 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4259 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4260 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4261 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4262 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4263 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4264 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4265 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4266 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4267 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4268 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4269 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4270 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4271 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4272 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_4085 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4226 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4227 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4228 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4229 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4230 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4231 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_4232 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4233 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4234 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4235 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4236 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4237 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4238 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_4239 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_4240 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_4241 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_4242 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_4243 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_4244 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_4245 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_4246 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_4247 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_4248 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_4249 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_4250 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_4251 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_4252 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_4253 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_4086 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4220 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4221 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4223 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4224 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_4087 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4208 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4209 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4211 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4212 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4213 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4214 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4215 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4216 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4217 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4218 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_4088 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4196 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4197 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4199 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4200 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4201 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4202 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4203 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4204 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4205 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4206 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_4089 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4184 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4185 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4187 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4188 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4189 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4190 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4191 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4192 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4193 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4194 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_4090 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4172 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4173 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4175 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4176 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4177 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4178 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4179 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4180 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4181 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4182 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_4091 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4160 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4161 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4163 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4164 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4165 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4166 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4167 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4168 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4169 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4170 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_4092 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4148 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4149 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4151 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4152 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4153 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4154 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4155 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4156 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4157 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4158 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_4093 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4137 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4138 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4140 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4141 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4142 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4143 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4144 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4145 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4146 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4147 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_4094 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4125 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4126 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_4128 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_4129 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_4130 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_4131 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_4132 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_4133 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_4134 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_4135 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_4136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_4095 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4122 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4123 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4124 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_4096 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4119 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4120 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4121 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_4097 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4116 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4117 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4118 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_4098 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4113 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4114 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4115 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_4099 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4112 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_4100 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4111 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_4101 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4110 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_4102 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4107 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4108 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4109 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_4103 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_4104 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_4105 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_4106 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_4051 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_4052 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_4053 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_4055 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 217(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_4060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4061 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_4062 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_4064 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 28(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_4065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_4066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_4067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_4068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_4069 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_4070 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_4071 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_4072 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_4056 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[4].AGLO_CORE_EG | AlgoCore_eg__xdcDup__5 | 5416(1.56%) | 5341(1.54%) | 0(0.00%) | 75(0.04%) | 7405(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[4].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__5 | 1699(0.49%) | 1699(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3831 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_3832 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3833 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD96 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD97 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD98 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD99 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__6 | 1330(0.38%) | 1330(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__6 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3924 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3925 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3926 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3927 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3928 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3929 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3930 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3931 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3932 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3933 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3934 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3935 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3936 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3937 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3938 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3939 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3940 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3941 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3942 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3943 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3944 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3945 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3946 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3947 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3948 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3949 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3950 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3951 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3952 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3953 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3954 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3955 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3956 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3957 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3958 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3959 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3960 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3961 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3962 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3963 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3964 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3965 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3966 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3967 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3968 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3969 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3970 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3971 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3972 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3973 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3974 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3975 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3976 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3977 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3978 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3979 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3980 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3981 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3982 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3983 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3984 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3985 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3986 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3987 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3988 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3989 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3990 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3991 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3992 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3993 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3994 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3995 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3996 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3997 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3998 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3999 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_4000 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_4001 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_4002 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_4003 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_4004 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_4005 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_4006 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_4007 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_4008 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_4009 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_4010 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_4011 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_4012 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_4013 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_4014 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_4015 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_4016 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_4017 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_4018 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_4019 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_4020 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_4021 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_4022 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_4023 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_4024 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_4025 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_4026 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_4027 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_4028 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_4029 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_4030 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_4031 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_4032 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_4033 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_4034 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_4035 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_4036 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_4037 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_4038 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_4039 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_4040 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_4041 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_4042 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_4043 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_4044 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_4045 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_4046 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_4047 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_4048 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_4049 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_4050 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_3834 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_3834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3908 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3915 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3916 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3917 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3918 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3919 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3920 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3921 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3922 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3923 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_3835 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_3835 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3898 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3899 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3900 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3901 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3902 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3903 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3904 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3836 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3836 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3888 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3889 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3890 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3837 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3878 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3879 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3880 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3881 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3882 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3883 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3884 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3838 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3864 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3865 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3866 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3867 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3868 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3869 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3839 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3839 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3851 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3852 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3853 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3854 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3855 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3856 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3857 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_3840 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_3841 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3842 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__5 | 3361(0.97%) | 3282(0.95%) | 0(0.00%) | 79(0.05%) | 3928(0.57%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__5 | 504(0.15%) | 504(0.15%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__6 | 2695(0.78%) | 2645(0.76%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_3619 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3819 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3820 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3822 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3823 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3824 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3825 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3826 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3827 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3828 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3829 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_3620 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_3621 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_3622 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_3623 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_3624 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_3625 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_3626 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_3627 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_3628 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_3629 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3630 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3800 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3801 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3803 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3804 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3805 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3806 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3807 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3808 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3809 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3810 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3811 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3812 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3813 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3814 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3815 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3816 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3817 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3818 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3631 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3772 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3773 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3774 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3775 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3776 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3777 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3778 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3779 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3780 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3781 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3782 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3783 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3784 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3785 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3786 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3787 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3788 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3789 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3790 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3791 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3792 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3793 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3794 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3795 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3796 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3797 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3798 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3799 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_3632 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3766 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3767 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3769 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3770 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_3633 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3754 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3755 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3757 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3758 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3759 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3760 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3761 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3762 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3763 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3764 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_3634 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3742 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3743 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3745 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3746 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3747 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3748 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3749 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3750 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3751 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3752 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_3635 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3730 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3731 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3733 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3734 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3735 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3736 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3737 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3738 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3739 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3740 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_3636 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3718 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3719 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3721 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3722 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3723 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3724 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3725 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3726 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3727 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3728 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_3637 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3706 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3707 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3709 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3710 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3711 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3712 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3713 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3714 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3715 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3716 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_3638 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3694 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3695 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3697 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3698 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3699 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3700 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3701 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3702 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3703 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3704 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_3639 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3683 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3684 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3686 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3687 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3688 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3689 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3690 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3691 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3692 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3693 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_3640 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3671 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3672 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3674 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3675 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3676 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3677 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3678 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3679 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3680 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3681 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_3641 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3668 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3669 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3670 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_3642 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3665 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3666 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3667 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_3643 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3662 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3663 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3664 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_3644 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3659 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3660 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3661 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_3645 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3658 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_3646 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3657 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_3647 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3656 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_3648 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3653 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3654 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3655 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_3649 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3650 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3651 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3652 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_3597 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_3598 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_3599 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_3601 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 205(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_3606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3607 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_3608 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_3610 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_3612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_3613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_3615 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_3616 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3617 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3618 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3602 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[5].AGLO_CORE_EG | AlgoCore_eg__xdcDup__6 | 5418(1.56%) | 5342(1.54%) | 0(0.00%) | 76(0.04%) | 7410(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[5].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__6 | 1700(0.49%) | 1700(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_3377 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_3378 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_3379 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__7 | 1330(0.38%) | 1330(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__7 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3470 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3471 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3472 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3473 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3474 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3475 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3476 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3477 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3478 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3479 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3480 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3481 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3482 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3483 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3484 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3485 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3486 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3487 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3488 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3489 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3490 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3491 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3492 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3493 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3494 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3495 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3496 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3497 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3498 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3499 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3500 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3501 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3502 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3503 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3504 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3505 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3506 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3507 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3508 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3509 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3510 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3511 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3512 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3513 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3514 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3515 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3516 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3517 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3518 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3519 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3520 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3521 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3522 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3523 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3524 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3525 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3526 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3527 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3528 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3529 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3530 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3531 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3532 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3533 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3534 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3535 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3536 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3537 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3538 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3539 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3540 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3541 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3542 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3543 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3544 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3545 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3546 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_3547 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_3548 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_3549 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_3550 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_3551 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_3552 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_3553 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_3554 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_3555 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_3556 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_3557 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_3558 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_3559 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_3560 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_3561 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_3562 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_3563 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_3564 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_3565 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_3566 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_3567 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_3568 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_3569 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_3570 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_3571 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_3572 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_3573 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_3574 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_3575 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_3576 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_3577 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_3578 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_3579 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3580 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3581 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3582 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3583 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3584 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3585 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3586 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3587 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3588 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3589 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3590 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3591 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3592 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3593 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3594 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3595 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3596 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_3380 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3461 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3462 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3463 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3464 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3465 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3466 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3467 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3468 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3469 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_3381 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_3381 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3444 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3445 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3446 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3447 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3448 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3449 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3450 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_3382 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_3382 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3434 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3435 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3436 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_3383 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3424 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3425 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3426 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3427 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3428 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3429 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3430 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_3384 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3410 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3411 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3412 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3413 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3414 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3415 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_3385 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_3385 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3397 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3398 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3399 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3400 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3401 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3402 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3403 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_3386 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_3387 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_3388 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__6 | 3360(0.97%) | 3281(0.95%) | 0(0.00%) | 79(0.05%) | 3889(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__6 | 503(0.15%) | 503(0.15%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__7 | 2695(0.78%) | 2645(0.76%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_3165 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3365 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3366 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3368 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3369 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3370 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3371 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3372 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3373 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3374 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3375 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_3166 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_3167 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_3168 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_3169 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_3170 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_3171 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_3172 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_3173 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_3174 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_3175 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3176 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3346 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3347 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3349 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3350 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3351 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3352 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3353 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3354 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3355 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3356 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3357 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3358 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3359 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3360 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3361 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3362 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3363 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3364 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_3177 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3318 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3319 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3320 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3321 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3322 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3323 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3324 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3325 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3326 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3327 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3328 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3329 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3330 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3331 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3332 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3333 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3334 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3335 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3336 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3337 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3338 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3339 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3340 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3341 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3342 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3343 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3344 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3345 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_3178 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3312 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3313 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3315 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3316 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_3179 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3300 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3301 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3303 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3304 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3305 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3306 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3307 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3308 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3309 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3310 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_3180 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3288 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3289 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3291 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3292 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3293 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3294 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3295 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3296 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3297 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3298 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_3181 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3276 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3277 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3279 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3280 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3281 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3282 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3283 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3284 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3285 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3286 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_3182 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3264 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3265 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3267 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3268 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3269 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3270 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3271 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3272 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3273 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3274 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_3183 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3252 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3253 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3255 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3256 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3257 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3258 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3259 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3260 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3261 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3262 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_3184 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3240 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3241 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3243 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3244 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3245 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3246 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3247 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3248 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3249 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3250 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_3185 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3229 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3230 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3232 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3233 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3234 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3235 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3236 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3237 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3238 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3239 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_3186 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3217 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3218 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3220 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3221 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3222 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3223 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3224 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3225 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3226 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3227 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_3187 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3214 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3215 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3216 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_3188 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3211 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3212 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3213 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_3189 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3208 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3209 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3210 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_3190 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3205 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3206 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3207 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_3191 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3204 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_3192 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3203 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_3193 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3202 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_3194 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3199 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3200 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3201 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_3195 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3196 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3197 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3198 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_3143 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_3144 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_3145 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_3147 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 204(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3153 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_3154 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_3156 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_3157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_3158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_3159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_3161 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_3162 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_3163 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_3164 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_3148 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[6].AGLO_CORE_EG | AlgoCore_eg__xdcDup__7 | 5420(1.56%) | 5344(1.54%) | 0(0.00%) | 76(0.04%) | 7412(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[6].AGLO_CORE_EG) | AlgoCore_eg__xdcDup__7 | 1701(0.49%) | 1701(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1_2923 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1_2924 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1_2925 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult_HD120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult_HD128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__8 | 1331(0.38%) | 1331(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__8 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_3016 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_3017 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_3018 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_3019 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3020 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3021 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3022 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_3023 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_3024 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_3025 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_3026 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3027 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3028 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3029 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3030 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_3031 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3032 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3033 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3034 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3035 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3036 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3037 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_3038 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_3039 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_3040 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_3041 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_3042 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_3043 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3044 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3045 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3046 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_3047 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_3048 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_3049 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_3050 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_3051 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_3052 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_3053 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_3054 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_3055 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_3056 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_3057 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_3058 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_3059 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_3060 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_3061 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_3062 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_3063 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_3064 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_3065 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_3066 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_3067 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_3068 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_3069 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_3070 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_3071 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_3072 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_3073 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_3074 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_3075 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_3076 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_3077 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_3078 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_3079 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_3080 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_3081 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_3082 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_3083 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_3084 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_3085 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_3086 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_3087 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_3088 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_3089 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_3090 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_3091 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_3092 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_3093 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_3094 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_3095 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_3096 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_3097 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_3098 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_3099 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_3100 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_3101 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_3102 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_3103 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_3104 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_3105 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_3106 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_3107 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_3108 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_3109 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_3110 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_3111 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_3112 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_3113 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_3114 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_3115 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_3116 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_3117 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_3118 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_3119 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_3120 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_3121 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_3122 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_3123 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_3124 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_3125 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_3126 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_3127 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_3128 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_3129 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_3130 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_3131 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_3132 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_3133 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_3134 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_3135 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_3136 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_3137 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_3138 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_3139 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_3140 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_3141 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_3142 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1_2926 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1_2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_3000 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_3007 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_3008 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_3009 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_3010 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_3011 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_3012 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_3013 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_3014 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_3015 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1_2927 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1_2927 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2990 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2991 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2992 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2993 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2994 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2995 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2996 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1_2928 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1_2928 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2980 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2981 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2982 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1_2929 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1_2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2970 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2971 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2972 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2973 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2974 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2975 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2976 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2930 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2956 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2957 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2958 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2959 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2960 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2961 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1_2931 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1_2931 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2943 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2944 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2945 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2946 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2947 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2948 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2949 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1_2932 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1_2933 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1_2934 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt__xdcDup__7 | 3360(0.97%) | 3281(0.95%) | 0(0.00%) | 79(0.05%) | 3955(0.57%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt__xdcDup__7 | 503(0.15%) | 503(0.15%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__8 | 2695(0.78%) | 2645(0.76%) | 0(0.00%) | 50(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1_2711 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2911 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2912 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2914 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2915 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2916 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2917 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2918 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2919 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2920 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2921 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1_2712 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1_2713 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_2714 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_2715 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_2716 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_2717 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_2718 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_2719 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_2720 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_2721 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2722 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2892 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2893 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2895 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2896 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2897 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2898 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2899 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2900 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2901 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2902 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2903 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2904 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2905 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2906 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2907 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2908 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2909 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2910 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2723 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2864 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2865 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2866 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2867 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2868 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2869 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2870 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2871 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2872 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2873 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2874 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2875 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2876 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2877 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2878 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2879 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2880 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2881 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2882 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2883 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2884 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2885 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2886 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2887 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2888 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2889 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2890 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2891 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1_2724 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2858 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2859 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2861 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2862 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_2725 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2846 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2847 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2849 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2850 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2851 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2852 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2853 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2854 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2855 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2856 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_2726 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2834 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2835 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2837 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2838 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2839 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2840 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2841 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2842 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2843 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2844 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_2727 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2822 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2823 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2825 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2826 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2827 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2828 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2829 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2830 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2831 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2832 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_2728 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2810 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2811 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2813 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2814 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2815 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2816 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2817 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2818 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2819 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2820 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_2729 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2798 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2799 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2801 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2802 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2803 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2804 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2805 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2806 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2807 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2808 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_2730 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2786 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2787 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2789 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2790 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2791 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2792 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2793 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2794 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2795 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2796 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_2731 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2775 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2776 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2778 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2779 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2780 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2781 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2782 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2783 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2784 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2785 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_2732 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2763 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2764 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2766 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2767 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2768 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2769 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2770 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2771 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2772 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2773 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1_2733 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2760 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2761 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2762 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_2734 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2757 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2758 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2759 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_2735 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2754 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2755 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2756 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_2736 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2751 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2752 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2753 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1_2737 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2750 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_2738 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2749 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_2739 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2748 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_2740 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2745 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2746 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2747 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_2741 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2742 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2743 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2744 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1_2689 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1_2690 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1_2691 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1_2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1_2693 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 222(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2699 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_2700 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1_2701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_2702 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_2707 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_2708 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2709 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2710 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1_2694 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_GENERATION[7].AGLO_CORE_EG | AlgoCore_eg | 5418(1.56%) | 5342(1.54%) | 0(0.00%) | 76(0.04%) | 7413(1.07%) | 0(0.00%) | 0(0.00%) | 9(0.31%) | | (ALGO_GENERATION[7].AGLO_CORE_EG) | AlgoCore_eg | 1700(0.49%) | 1700(0.49%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Condition_threshold_delay | Delay__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DEAD_MATERIAL_DELAY | GeneralDelay__parameterized1__sblockDup__1 | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Energy_threshold_delay | Delay__parameterized0__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HADRON_MULTIPLIER | MultiMultiplier__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.FASTMULTIPLIER | FastMult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.FASTMULTIPLIER | FastMult_HD44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22_HD45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv_HD46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp_HD47 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.FASTMULTIPLIER | FastMult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | FastMult_mult_gen_v12_0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | FastMult_mult_gen_v12_0_22_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | FastMult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | INPUT_MULTIPLEXER | egInputMultiplexer__sblockDup__1 | 1330(0.38%) | 1330(0.38%) | 0(0.00%) | 0(0.00%) | 3802(0.55%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_ENERGY | MultiAdder__sblockDup__1 | 1687(0.49%) | 1687(0.49%) | 0(0.00%) | 0(0.00%) | 1976(0.29%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_ENERGY) | MultiAdder__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2562 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2563 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2564 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2565 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2566 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2567 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2568 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2569 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2570 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2571 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2572 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2573 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2574 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2575 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2576 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2577 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2578 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2579 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2580 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2581 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2582 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2583 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2584 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2585 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2586 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2587 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2588 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2589 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2590 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2591 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2592 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[0].ADD | Adder__sblockDup__1_2593 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[10].ADD | Adder__sblockDup__1_2594 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[11].ADD | Adder__sblockDup__1_2595 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[12].ADD | Adder__sblockDup__1_2596 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[13].ADD | Adder__sblockDup__1_2597 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[14].ADD | Adder__sblockDup__1_2598 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[15].ADD | Adder__sblockDup__1_2599 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[16].ADD | Adder__sblockDup__1_2600 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[17].ADD | Adder__sblockDup__1_2601 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[18].ADD | Adder__sblockDup__1_2602 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[19].ADD | Adder__sblockDup__1_2603 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[1].ADD | Adder__sblockDup__1_2604 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[20].ADD | Adder__sblockDup__1_2605 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[21].ADD | Adder__sblockDup__1_2606 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[22].ADD | Adder__sblockDup__1_2607 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[23].ADD | Adder__sblockDup__1_2608 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[24].ADD | Adder__sblockDup__1_2609 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[25].ADD | Adder__sblockDup__1_2610 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[26].ADD | Adder__sblockDup__1_2611 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[27].ADD | Adder__sblockDup__1_2612 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[28].ADD | Adder__sblockDup__1_2613 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[29].ADD | Adder__sblockDup__1_2614 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[2].ADD | Adder__sblockDup__1_2615 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[30].ADD | Adder__sblockDup__1_2616 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[31].ADD | Adder__sblockDup__1_2617 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[3].ADD | Adder__sblockDup__1_2618 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[4].ADD | Adder__sblockDup__1_2619 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[5].ADD | Adder__sblockDup__1_2620 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[6].ADD | Adder__sblockDup__1_2621 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[7].ADD | Adder__sblockDup__1_2622 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[8].ADD | Adder__sblockDup__1_2623 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[5].adder_gen[9].ADD | Adder__sblockDup__1_2624 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[0].ADD | Adder__sblockDup__1_2625 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[10].ADD | Adder__sblockDup__1_2626 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[11].ADD | Adder__sblockDup__1_2627 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[12].ADD | Adder__sblockDup__1_2628 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[13].ADD | Adder__sblockDup__1_2629 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[14].ADD | Adder__sblockDup__1_2630 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[15].ADD | Adder__sblockDup__1_2631 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[16].ADD | Adder__sblockDup__1_2632 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[17].ADD | Adder__sblockDup__1_2633 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[18].ADD | Adder__sblockDup__1_2634 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[19].ADD | Adder__sblockDup__1_2635 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[1].ADD | Adder__sblockDup__1_2636 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[20].ADD | Adder__sblockDup__1_2637 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[21].ADD | Adder__sblockDup__1_2638 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[22].ADD | Adder__sblockDup__1_2639 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[23].ADD | Adder__sblockDup__1_2640 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[24].ADD | Adder__sblockDup__1_2641 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[25].ADD | Adder__sblockDup__1_2642 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[26].ADD | Adder__sblockDup__1_2643 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[27].ADD | Adder__sblockDup__1_2644 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[28].ADD | Adder__sblockDup__1_2645 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[29].ADD | Adder__sblockDup__1_2646 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[2].ADD | Adder__sblockDup__1_2647 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[30].ADD | Adder__sblockDup__1_2648 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[31].ADD | Adder__sblockDup__1_2649 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[32].ADD | Adder__sblockDup__1_2650 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[33].ADD | Adder__sblockDup__1_2651 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[34].ADD | Adder__sblockDup__1_2652 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[35].ADD | Adder__sblockDup__1_2653 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[36].ADD | Adder__sblockDup__1_2654 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[37].ADD | Adder__sblockDup__1_2655 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[38].ADD | Adder__sblockDup__1_2656 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[39].ADD | Adder__sblockDup__1_2657 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[3].ADD | Adder__sblockDup__1_2658 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[40].ADD | Adder__sblockDup__1_2659 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[41].ADD | Adder__sblockDup__1_2660 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[42].ADD | Adder__sblockDup__1_2661 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[43].ADD | Adder__sblockDup__1_2662 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[44].ADD | Adder__sblockDup__1_2663 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[45].ADD | Adder__sblockDup__1_2664 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[46].ADD | Adder__sblockDup__1_2665 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[47].ADD | Adder__sblockDup__1_2666 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[48].ADD | Adder__sblockDup__1_2667 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[49].ADD | Adder__sblockDup__1_2668 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[4].ADD | Adder__sblockDup__1_2669 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[50].ADD | Adder__sblockDup__1_2670 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[51].ADD | Adder__sblockDup__1_2671 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[52].ADD | Adder__sblockDup__1_2672 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[53].ADD | Adder__sblockDup__1_2673 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[54].ADD | Adder__sblockDup__1_2674 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[55].ADD | Adder__sblockDup__1_2675 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[56].ADD | Adder__sblockDup__1_2676 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[57].ADD | Adder__sblockDup__1_2677 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[58].ADD | Adder__sblockDup__1_2678 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[59].ADD | Adder__sblockDup__1_2679 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[5].ADD | Adder__sblockDup__1_2680 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[60].ADD | Adder__sblockDup__1_2681 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[61].ADD | Adder__sblockDup__1_2682 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[62].ADD | Adder__sblockDup__1_2683 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[63].ADD | Adder__sblockDup__1_2684 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[6].ADD | Adder__sblockDup__1_2685 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[7].ADD | Adder__sblockDup__1_2686 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[8].ADD | Adder__sblockDup__1_2687 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[6].adder_gen[9].ADD | Adder__sblockDup__1_2688 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_CORE | MultiAdder__parameterized3__sblockDup__1 | 153(0.04%) | 144(0.04%) | 0(0.00%) | 9(0.01%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_CORE) | MultiAdder__parameterized3__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2546 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2553 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2554 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2555 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2556 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[14].ADD | Adder__sblockDup__1_2557 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[15].ADD | Adder__sblockDup__1_2558 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2559 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2560 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2561 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_HAD_ENV | MultiAdder__parameterized4__sblockDup__1 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 254(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_HAD_ENV) | MultiAdder__parameterized4__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2536 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2537 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2538 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2539 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2540 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2541 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2542 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_CORE | MultiAdder__parameterized1__sblockDup__1 | 57(0.02%) | 48(0.01%) | 0(0.00%) | 9(0.01%) | 118(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_CORE) | MultiAdder__parameterized1__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2526 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2527 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2528 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_RETA_ENV | MultiAdder__parameterized0__sblockDup__1 | 112(0.03%) | 112(0.03%) | 0(0.00%) | 0(0.00%) | 269(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_RETA_ENV) | MultiAdder__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2516 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2517 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2518 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2519 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2520 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2521 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2522 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_CORE | MultiAdder__parameterized0__sblockDup__1_2480 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 219(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_CORE) | MultiAdder__parameterized0__sblockDup__1_2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2502 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2503 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2504 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2505 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2506 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2507 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MULTI_ADDER_WS_ENV | MultiAdder__parameterized2__sblockDup__1 | 121(0.03%) | 112(0.03%) | 0(0.00%) | 9(0.01%) | 270(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (MULTI_ADDER_WS_ENV) | MultiAdder__parameterized2__sblockDup__1 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2489 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2490 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2491 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2492 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2493 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2494 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[7].ADD | Adder__sblockDup__1_2495 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | OVERFLOW_DELAY | GeneralDelay__parameterized3__sblockDup__1 | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RETA_MULTIPLIER | MultiMultiplier__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | SEED_DELAY | GeneralDelay__parameterized2__sblockDup__1 | 5(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SEED_FINDER | SeedFinder__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | WS_MULTIPLIER | MultiMultiplier__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult_HD218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT | AlgoCore_tau_bdt | 3359(0.97%) | 3281(0.95%) | 0(0.00%) | 78(0.04%) | 3861(0.56%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | (ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT) | AlgoCore_tau_bdt | 503(0.15%) | 503(0.15%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ADDER_TREE | AdderTree__sblockDup__1 | 2694(0.78%) | 2645(0.76%) | 0(0.00%) | 49(0.03%) | 3297(0.48%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CORE | MultiAdderWithCarry__parameterized1__sblockDup__1 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2468 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2469 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2471 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2472 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2473 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2474 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2475 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2476 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2477 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2478 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l0_d0000_l0_d0000_d | DelayWithCarry__parameterized1__sblockDup__1 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1164_l1_d1164_d | DelayWithCarry__sblockDup__1 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1315_l1_d1315_d | DelayWithCarry__sblockDup__1_2276 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1493_l1_d1493_d | DelayWithCarry__sblockDup__1_2277 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l1_d1690_l1_d1690_d | DelayWithCarry__sblockDup__1_2278 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0125_l2_d0125_d | DelayWithCarry__parameterized0__sblockDup__1_2279 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0375_l2_d0375_d | DelayWithCarry__parameterized0__sblockDup__1_2280 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0625_l2_d0625_d | DelayWithCarry__parameterized0__sblockDup__1_2281 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d0990_l2_d0990_d | DelayWithCarry__sblockDup__1_2282 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_l2_d1051_l2_d1051_d | DelayWithCarry__sblockDup__1_2283 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | EM_ET | MultiAdderWithCarry__parameterized2__sblockDup__1 | 289(0.08%) | 280(0.08%) | 0(0.00%) | 9(0.01%) | 301(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2449 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2450 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2452 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2453 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2454 | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2455 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2456 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2457 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2458 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2459 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2460 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2461 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2462 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2463 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2464 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2465 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2466 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2467 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ET | MultiAdderWithCarry__parameterized2__sblockDup__1_2284 | 463(0.13%) | 463(0.13%) | 0(0.00%) | 0(0.00%) | 472(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2421 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2422 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2423 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2424 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2425 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2426 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[3].ADD | Adder__sblockDup__1_2427 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2428 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2429 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2430 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2431 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2432 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2433 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[6].ADD | Adder__sblockDup__1_2434 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[0].ADD | Adder__sblockDup__1_2435 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[10].ADD | Adder__sblockDup__1_2436 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[11].ADD | Adder__sblockDup__1_2437 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[12].ADD | Adder__sblockDup__1_2438 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[13].ADD | Adder__sblockDup__1_2439 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[1].ADD | Adder__sblockDup__1_2440 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[2].ADD | Adder__sblockDup__1_2441 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[3].ADD | Adder__sblockDup__1_2442 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[4].ADD | Adder__sblockDup__1_2443 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[5].ADD | Adder__sblockDup__1_2444 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[6].ADD | Adder__sblockDup__1_2445 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[7].ADD | Adder__sblockDup__1_2446 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[8].ADD | Adder__sblockDup__1_2447 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[4].adder_gen[9].ADD | Adder__sblockDup__1_2448 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | HAD_ET | MultiAdderWithCarry__parameterized3__sblockDup__1 | 66(0.02%) | 66(0.02%) | 0(0.00%) | 0(0.00%) | 100(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2415 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2416 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2418 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2419 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T0 | MultiAdderWithCarry__parameterized1__sblockDup__1_2285 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2403 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2404 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2406 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2407 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2408 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2409 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2410 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2411 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2412 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2413 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T1 | MultiAdderWithCarry__parameterized1__sblockDup__1_2286 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2391 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2392 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2394 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2395 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2396 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2397 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2398 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2399 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2400 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2401 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T2 | MultiAdderWithCarry__parameterized1__sblockDup__1_2287 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2379 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2380 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2382 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2383 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2384 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2385 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2386 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2387 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2388 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2389 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T3 | MultiAdderWithCarry__parameterized1__sblockDup__1_2288 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2367 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2368 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2370 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2371 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2372 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2373 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2374 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2375 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2376 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2377 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T5 | MultiAdderWithCarry__parameterized1__sblockDup__1_2289 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2355 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2356 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2358 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2359 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2360 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2361 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2362 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2363 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2364 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2365 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T6 | MultiAdderWithCarry__parameterized1__sblockDup__1_2290 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2343 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2344 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2346 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2347 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2348 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2349 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2350 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2351 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2352 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2353 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T7 | MultiAdderWithCarry__parameterized1__sblockDup__1_2291 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 187(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2332 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2333 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2335 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2336 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2337 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2338 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2339 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2340 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2341 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2342 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | T8 | MultiAdderWithCarry__parameterized1__sblockDup__1_2292 | 165(0.05%) | 165(0.05%) | 0(0.00%) | 0(0.00%) | 203(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2320 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2321 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[0].ADD | Adder__sblockDup__1_2323 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[1].ADD | Adder__sblockDup__1_2324 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[2].adder_gen[2].ADD | Adder__sblockDup__1_2325 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[0].ADD | Adder__sblockDup__1_2326 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[1].ADD | Adder__sblockDup__1_2327 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[2].ADD | Adder__sblockDup__1_2328 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[3].ADD | Adder__sblockDup__1_2329 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[4].ADD | Adder__sblockDup__1_2330 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[3].adder_gen[5].ADD | Adder__sblockDup__1_2331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1164 | MultiAdderWithCarry__sblockDup__1 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2317 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2318 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2319 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1315 | MultiAdderWithCarry__sblockDup__1_2293 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2314 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2315 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2316 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1493 | MultiAdderWithCarry__sblockDup__1_2294 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2311 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2312 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2313 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1_d1690 | MultiAdderWithCarry__sblockDup__1_2295 | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2308 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2309 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2310 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0125 | MultiAdderWithCarry__parameterized0__sblockDup__1 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2307 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0375 | MultiAdderWithCarry__parameterized0__sblockDup__1_2296 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2306 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0625 | MultiAdderWithCarry__parameterized0__sblockDup__1_2297 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2305 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d0990 | MultiAdderWithCarry__sblockDup__1_2298 | 51(0.01%) | 51(0.01%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1_2302 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2303 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2304 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l2_d1051 | MultiAdderWithCarry__sblockDup__1_2299 | 53(0.02%) | 53(0.02%) | 0(0.00%) | 0(0.00%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].adder_gen[0].ADD | Adder__sblockDup__1 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[0].ADD | Adder__sblockDup__1_2300 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].adder_gen[1].ADD | Adder__sblockDup__1_2301 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | BDT | BDTModel__sblockDup__1 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 332(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_BDT | TauConditionsBDT__sblockDup__1 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_ENERGY_AND_SEED | TauConditionsEnergyAndSeed__sblockDup__1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | CONDITIONS_FRAC | TauConditionsFrac__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DELAY_TREE | DelayTree__sblockDup__1 | 29(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.02%) | 200(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTScore_C_IN_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergyOverflow_C_IN_BDTTOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_BDTTOBEnergy_C_IN_BDTTOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 64(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_EnergyThr_C_IN_EnergyThr_d | DelayWithCarry__parameterized2__sblockDup__1_2264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSumOverflow_C_IN_FracCoreSumOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2265 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracCoreSum_C_IN_FracCoreSum_d | DelayWithCarry__parameterized3__sblockDup__1_2266 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_FracEnvSumOverflow_C_IN_FracEnvSumOverflow_d | DelayWithCarry__parameterized0__sblockDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_Frac_ET_Thr_C_IN_Frac_ET_Thr_d | DelayWithCarry__parameterized0__sblockDup__1_2267 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergyOverflow_C_IN_TOBEnergyOverflow_d | DelayWithCarry__parameterized2__sblockDup__1_2268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_C_IN_TOBEnergy_C_IN_TOBEnergy_d | DelayWithCarry__parameterized2__sblockDup__1_2269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTCondition_Final_BDTCondition_d | DelayWithCarry__parameterized2__sblockDup__1_2270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_BDTScore_Final_BDTScore_d | DelayWithCarry__parameterized2__sblockDup__1_2271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_FracCondition_Final_FracCondition_d | DelayWithCarry__parameterized0__sblockDup__1_2272 | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_IsMax_Final_IsMax_d | DelayWithCarry__parameterized3__sblockDup__1_2273 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergyOverflow_Final_TOBEnergyOverflow_d | DelayWithCarry__parameterized3__sblockDup__1_2274 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DelayWC_Final_TOBEnergy_Final_TOBEnergy_d | DelayWithCarry__parameterized3__sblockDup__1_2275 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Frac_MULTIPLIER | MultiMultiplier | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.10%) | | MULT_FOR[0].SPEED.MULTIPLIER | Mult_HD390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[1].SPEED.MULTIPLIER | Mult_HD394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22_HD395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv_HD396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp_HD397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | MULT_FOR[2].SPEED.MULTIPLIER | Mult | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | U0 | Mult_mult_gen_v12_0_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | i_mult | Mult_mult_gen_v12_0_22_viv | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | gDSP.gDSP_only.iDSP | Mult_dsp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.03%) | | TAU_SEED_FINDER | TauSeedFinder__sblockDup__1 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | DATA_SHIFT_REGISTER | AlgoShiftRegister | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 12735(1.84%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_eg | SerialSorter | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 481(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_eg) | SerialSorter | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 321(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1503 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1504 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1505 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1506 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1507 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[0].SerialSorter_tau | SerialSorter_1414 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[0].SerialSorter_tau) | SerialSorter_1414 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1498 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1499 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1500 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1501 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1502 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_eg | SerialSorter_1415 | 302(0.09%) | 302(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_eg) | SerialSorter_1415 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1493 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1494 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1495 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1496 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1497 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[1].SerialSorter_tau | SerialSorter_1416 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[1].SerialSorter_tau) | SerialSorter_1416 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1488 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1489 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1490 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1491 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1492 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_eg | SerialSorter_1417 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_eg) | SerialSorter_1417 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1483 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1484 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1485 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1486 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1487 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[2].SerialSorter_tau | SerialSorter_1418 | 299(0.09%) | 299(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[2].SerialSorter_tau) | SerialSorter_1418 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1478 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1479 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1480 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1481 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1482 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_eg | SerialSorter_1419 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_eg) | SerialSorter_1419 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1473 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1474 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1475 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1476 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1477 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[3].SerialSorter_tau | SerialSorter_1420 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[3].SerialSorter_tau) | SerialSorter_1420 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1468 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1469 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1470 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1471 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1472 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_eg | SerialSorter_1421 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_eg) | SerialSorter_1421 | 125(0.04%) | 125(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1463 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1464 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1465 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1466 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1467 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[4].SerialSorter_tau | SerialSorter_1422 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[4].SerialSorter_tau) | SerialSorter_1422 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1458 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1459 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1460 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1461 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1462 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_eg | SerialSorter_1423 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_eg) | SerialSorter_1423 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1453 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1454 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1455 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1456 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1457 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[5].SerialSorter_tau | SerialSorter_1424 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[5].SerialSorter_tau) | SerialSorter_1424 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1448 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1449 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1450 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1451 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1452 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_eg | SerialSorter_1425 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_eg) | SerialSorter_1425 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1443 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1444 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1445 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1446 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1447 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[6].SerialSorter_tau | SerialSorter_1426 | 297(0.09%) | 297(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[6].SerialSorter_tau) | SerialSorter_1426 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1438 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1439 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1440 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1441 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1442 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_eg | SerialSorter_1427 | 300(0.09%) | 300(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_eg) | SerialSorter_1427 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell_1433 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1434 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1435 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1436 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1437 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | out_tob_for[7].SerialSorter_tau | SerialSorter_1428 | 298(0.09%) | 298(0.09%) | 0(0.00%) | 0(0.00%) | 480(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (out_tob_for[7].SerialSorter_tau) | SerialSorter_1428 | 127(0.04%) | 127(0.04%) | 0(0.00%) | 0(0.00%) | 320(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[0].SORT_CELL | SortingCell | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[1].SORT_CELL | SortingCell_1429 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[2].SORT_CELL | SortingCell_1430 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[3].SORT_CELL | SortingCell_1431 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SortingCells[4].SORT_CELL | SortingCell_1432 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | data_alignment_block | data_alignment | 21334(6.16%) | 8836(2.55%) | 0(0.00%) | 12498(7.17%) | 37512(5.41%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (data_alignment_block) | data_alignment | 469(0.14%) | 469(0.14%) | 0(0.00%) | 0(0.00%) | 848(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[0].bc_align_b | quad_bc_alignment | 117(0.03%) | 117(0.03%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[0].bc_align_b) | quad_bc_alignment | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1410 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1411 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1412 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1413 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[11].bc_align_b | quad_bc_alignment_602 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[11].bc_align_b) | quad_bc_alignment_602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1403 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1404 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1405 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1406 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[12].bc_align_b | quad_bc_alignment_603 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[12].bc_align_b) | quad_bc_alignment_603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1395 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1396 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1397 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1398 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[13].bc_align_b | quad_bc_alignment_604 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[13].bc_align_b) | quad_bc_alignment_604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1387 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1388 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1389 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1390 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[14].bc_align_b | quad_bc_alignment_605 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[14].bc_align_b) | quad_bc_alignment_605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1379 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1380 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1381 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1382 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[15].bc_align_b | quad_bc_alignment_606 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[15].bc_align_b) | quad_bc_alignment_606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1371 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1372 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1373 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1374 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[1].bc_align_b | quad_bc_alignment_607 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[1].bc_align_b) | quad_bc_alignment_607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1363 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1364 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1365 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1366 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[2].bc_align_b | quad_bc_alignment_608 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[2].bc_align_b) | quad_bc_alignment_608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1355 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1356 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1357 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1358 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[3].bc_align_b | quad_bc_alignment_609 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[3].bc_align_b) | quad_bc_alignment_609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1347 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1348 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1349 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1350 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[4].bc_align_b | quad_bc_alignment_610 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[4].bc_align_b) | quad_bc_alignment_610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1339 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1340 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1341 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1342 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[5].bc_align_b | quad_bc_alignment_611 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[5].bc_align_b) | quad_bc_alignment_611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1331 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1332 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1333 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1334 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[6].bc_align_b | quad_bc_alignment_612 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[6].bc_align_b) | quad_bc_alignment_612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1323 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1324 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1325 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1326 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[7].bc_align_b | quad_bc_alignment_613 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[7].bc_align_b) | quad_bc_alignment_613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1315 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1316 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1317 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1318 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[8].bc_align_b | quad_bc_alignment_614 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[8].bc_align_b) | quad_bc_alignment_614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1307 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1308 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1309 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1310 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_after_mux[9].bc_align_b | quad_bc_alignment_615 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_after_mux[9].bc_align_b) | quad_bc_alignment_615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1299 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1300 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1301 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1302 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[0].bc_align_a | quad_bc_alignment_616 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 111(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[0].bc_align_a) | quad_bc_alignment_616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1291 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1292 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1293 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1294 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[11].bc_align_a | quad_bc_alignment_618 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[11].bc_align_a) | quad_bc_alignment_618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1280 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1281 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1282 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1283 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[12].bc_align_a | quad_bc_alignment_619 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[12].bc_align_a) | quad_bc_alignment_619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1272 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1273 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1274 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1275 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[13].bc_align_a | quad_bc_alignment_620 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[13].bc_align_a) | quad_bc_alignment_620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1264 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1265 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1266 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1267 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[14].bc_align_a | quad_bc_alignment_621 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[14].bc_align_a) | quad_bc_alignment_621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1256 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1257 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1258 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1259 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[15].bc_align_a | quad_bc_alignment_622 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[15].bc_align_a) | quad_bc_alignment_622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1248 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1249 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1250 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1251 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[1].bc_align_a | quad_bc_alignment_623 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[1].bc_align_a) | quad_bc_alignment_623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1240 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1241 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1242 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1243 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[2].bc_align_a | quad_bc_alignment_624 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[2].bc_align_a) | quad_bc_alignment_624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1232 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1233 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1234 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1235 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[3].bc_align_a | quad_bc_alignment_625 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[3].bc_align_a) | quad_bc_alignment_625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1224 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1225 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1226 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1227 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[4].bc_align_a | quad_bc_alignment_626 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[4].bc_align_a) | quad_bc_alignment_626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1216 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1217 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1218 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1219 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[5].bc_align_a | quad_bc_alignment_627 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[5].bc_align_a) | quad_bc_alignment_627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1208 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1209 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1210 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1211 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[6].bc_align_a | quad_bc_alignment_628 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[6].bc_align_a) | quad_bc_alignment_628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1200 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1201 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1202 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1203 | 29(0.01%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[7].bc_align_a | quad_bc_alignment_629 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[7].bc_align_a) | quad_bc_alignment_629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1192 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1193 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1194 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1195 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[8].bc_align_a | quad_bc_alignment_630 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[8].bc_align_a) | quad_bc_alignment_630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm_1184 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1185 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1186 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1187 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bc_alignment_before_mux[9].bc_align_a | quad_bc_alignment_631 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (bc_alignment_before_mux[9].bc_align_a) | quad_bc_alignment_631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch0_pseudo | pseudo_orbit_gen_1173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch1_pseudo | pseudo_orbit_gen_1174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch2_pseudo | pseudo_orbit_gen_1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ch3_pseudo | pseudo_orbit_gen_1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_0 | orbit_sm | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_1 | orbit_sm_1177 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_2 | orbit_sm_1178 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm_orbit_3 | orbit_sm_1179 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo | pseudo_orbit_gen | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | orbit_ref_pseudo_b | pseudo_orbit_gen_632 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u0 | top_synch | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u0) | top_synch | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1168 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1169 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1170 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1171 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1171 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1172 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[0].u1 | crc_checker | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[0].u1) | crc_checker | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1166 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u0 | top_synch_633 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u0) | top_synch_633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1160 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1161 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1162 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1163 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1164 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1164 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1165 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[10].u1 | crc_checker_634 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[10].u1) | crc_checker_634 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1159 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u0 | top_synch_635 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u0) | top_synch_635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1155 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1156 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1157 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1157 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1158 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[11].u1 | crc_checker_636 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[11].u1) | crc_checker_636 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1152 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u0 | top_synch_637 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u0) | top_synch_637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1147 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1148 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1149 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1150 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1150 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1151 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[12].u1 | crc_checker_638 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[12].u1) | crc_checker_638 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1145 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u0 | top_synch_639 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u0) | top_synch_639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1140 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1141 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1142 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1143 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1143 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1144 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[13].u1 | crc_checker_640 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[13].u1) | crc_checker_640 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1138 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u0 | top_synch_641 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u0) | top_synch_641 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1132 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1133 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1134 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1135 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1136 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1136 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1137 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[14].u1 | crc_checker_642 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[14].u1) | crc_checker_642 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1131 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u0 | top_synch_643 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u0) | top_synch_643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1127 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1128 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1129 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1129 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1130 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[15].u1 | crc_checker_644 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[15].u1) | crc_checker_644 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1124 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u0 | top_synch_645 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u0) | top_synch_645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1118 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1119 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1120 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1121 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1122 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1122 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1123 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[16].u1 | crc_checker_646 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[16].u1) | crc_checker_646 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1117 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u0 | top_synch_647 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u0) | top_synch_647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1112 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1113 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1114 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1115 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1115 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1116 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[17].u1 | crc_checker_648 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[17].u1) | crc_checker_648 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1110 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u0 | top_synch_649 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u0) | top_synch_649 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1104 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1105 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1106 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1107 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1108 | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1108 | 8(0.01%) | 7(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1109 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[18].u1 | crc_checker_650 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[18].u1) | crc_checker_650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1103 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u0 | top_synch_651 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u0) | top_synch_651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1098 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1099 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1100 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1101 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1101 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1102 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[19].u1 | crc_checker_652 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[19].u1) | crc_checker_652 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1096 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u0 | top_synch_653 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u0) | top_synch_653 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1092 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1093 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1094 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1094 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1095 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[1].u1 | crc_checker_654 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[1].u1) | crc_checker_654 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1089 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u0 | top_synch_655 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u0) | top_synch_655 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1083 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1084 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1085 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1086 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1087 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1087 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1088 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[20].u1 | crc_checker_656 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[20].u1) | crc_checker_656 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1082 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u0 | top_synch_657 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u0) | top_synch_657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1077 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1078 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1079 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1080 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1080 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1081 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[21].u1 | crc_checker_658 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[21].u1) | crc_checker_658 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1075 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u0 | top_synch_659 | 267(0.08%) | 18(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u0) | top_synch_659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1071 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1072 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1073 | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1073 | 8(0.01%) | 7(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1074 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[22].u1 | crc_checker_660 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[22].u1) | crc_checker_660 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1068 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u0 | top_synch_661 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u0) | top_synch_661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1063 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1064 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1065 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1066 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1066 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1067 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[23].u1 | crc_checker_662 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[23].u1) | crc_checker_662 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1061 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u0 | top_synch_663 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u0) | top_synch_663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1056 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1057 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1058 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1059 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1059 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1060 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[24].u1 | crc_checker_664 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[24].u1) | crc_checker_664 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1054 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u0 | top_synch_665 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u0) | top_synch_665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1049 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1050 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1051 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1052 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1052 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1053 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[25].u1 | crc_checker_666 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[25].u1) | crc_checker_666 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1047 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u0 | top_synch_667 | 267(0.08%) | 18(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u0) | top_synch_667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1042 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1043 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1044 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1045 | 28(0.01%) | 7(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1045 | 8(0.01%) | 7(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1046 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[26].u1 | crc_checker_668 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[26].u1) | crc_checker_668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1040 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u0 | top_synch_669 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u0) | top_synch_669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1035 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1036 | 231(0.07%) | 3(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1037 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1038 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1038 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1039 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[27].u1 | crc_checker_670 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[27].u1) | crc_checker_670 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1033 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u0 | top_synch_671 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u0) | top_synch_671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1028 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1029 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1030 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1031 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1031 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1032 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[28].u1 | crc_checker_672 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[28].u1) | crc_checker_672 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1026 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u0 | top_synch_673 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u0) | top_synch_673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1021 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1022 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1023 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1024 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1024 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1025 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[29].u1 | crc_checker_674 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[29].u1) | crc_checker_674 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1019 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u0 | top_synch_675 | 525(0.15%) | 276(0.08%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u0) | top_synch_675 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1013 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1014 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1015 | 484(0.14%) | 256(0.07%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1016 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1017 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1017 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1018 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[2].u1 | crc_checker_676 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[2].u1) | crc_checker_676 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1012 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u0 | top_synch_677 | 366(0.11%) | 117(0.03%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u0) | top_synch_677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_1006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1007 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1008 | 331(0.10%) | 103(0.03%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1009 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1010 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1010 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1011 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[30].u1 | crc_checker_678 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[30].u1) | crc_checker_678 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_1005 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u0 | top_synch_679 | 577(0.17%) | 328(0.09%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u0) | top_synch_679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_1000 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_1001 | 536(0.15%) | 308(0.09%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_1002 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_1003 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_1003 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_1004 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[31].u1 | crc_checker_680 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[31].u1) | crc_checker_680 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_998 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u0 | top_synch_681 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u0) | top_synch_681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_993 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_994 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_995 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_996 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_996 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_997 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[32].u1 | crc_checker_682 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[32].u1) | crc_checker_682 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_991 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u0 | top_synch_683 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u0) | top_synch_683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_986 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_987 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_988 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_989 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_989 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_990 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[33].u1 | crc_checker_684 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[33].u1) | crc_checker_684 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_984 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u0 | top_synch_685 | 366(0.11%) | 117(0.03%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u0) | top_synch_685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_979 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_980 | 331(0.10%) | 103(0.03%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_981 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_982 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_982 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_983 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[34].u1 | crc_checker_686 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[34].u1) | crc_checker_686 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_977 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u0 | top_synch_687 | 371(0.11%) | 122(0.04%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u0) | top_synch_687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_972 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_973 | 331(0.10%) | 103(0.03%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_974 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_975 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_975 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_976 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[35].u1 | crc_checker_688 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[35].u1) | crc_checker_688 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_970 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u0 | top_synch_689 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u0) | top_synch_689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_966 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_967 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_968 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_968 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_969 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[36].u1 | crc_checker_690 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[36].u1) | crc_checker_690 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_963 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u0 | top_synch_691 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u0) | top_synch_691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_958 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_959 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_960 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_961 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_961 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_962 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[37].u1 | crc_checker_692 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[37].u1) | crc_checker_692 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_956 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u0 | top_synch_693 | 571(0.16%) | 322(0.09%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u0) | top_synch_693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_951 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_952 | 536(0.15%) | 308(0.09%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_953 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_954 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_954 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_955 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[38].u1 | crc_checker_694 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[38].u1) | crc_checker_694 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_949 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u0 | top_synch_695 | 576(0.17%) | 327(0.09%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u0) | top_synch_695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_944 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_945 | 536(0.15%) | 308(0.09%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_946 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_947 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_947 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_948 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[39].u1 | crc_checker_696 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[39].u1) | crc_checker_696 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_942 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u0 | top_synch_697 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u0) | top_synch_697 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_937 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_938 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_939 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_940 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_940 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_941 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[3].u1 | crc_checker_698 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[3].u1) | crc_checker_698 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_935 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[44].u0 | top_synch_703 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[44].u0) | top_synch_703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_926 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_927 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_928 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_929 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_929 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_930 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[44].u1 | crc_checker_704 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[44].u1) | crc_checker_704 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_924 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[45].u0 | top_synch_705 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[45].u0) | top_synch_705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_920 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_921 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_922 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_922 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_923 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[45].u1 | crc_checker_706 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[45].u1) | crc_checker_706 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_917 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[46].u0 | top_synch_707 | 265(0.08%) | 16(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[46].u0) | top_synch_707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_913 | 230(0.07%) | 2(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_914 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_915 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_915 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_916 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[46].u1 | crc_checker_708 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[46].u1) | crc_checker_708 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_910 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[47].u0 | top_synch_709 | 42(0.01%) | 15(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[47].u0) | top_synch_709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_906 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_907 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_908 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_908 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_909 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[47].u1 | crc_checker_710 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[47].u1) | crc_checker_710 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_903 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u0 | top_synch_711 | 42(0.01%) | 15(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u0) | top_synch_711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_899 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_900 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_901 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_901 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_902 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[48].u1 | crc_checker_712 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[48].u1) | crc_checker_712 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_896 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u0 | top_synch_713 | 42(0.01%) | 15(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u0) | top_synch_713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_891 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_892 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_893 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_894 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_894 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_895 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[49].u1 | crc_checker_714 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[49].u1) | crc_checker_714 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_889 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u0 | top_synch_715 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u0) | top_synch_715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_885 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_886 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_887 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_887 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_888 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[4].u1 | crc_checker_716 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[4].u1) | crc_checker_716 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_882 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u0 | top_synch_717 | 37(0.01%) | 10(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u0) | top_synch_717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_878 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_879 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_880 | 14(0.01%) | 2(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_880 | 6(0.01%) | 2(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_881 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[50].u1 | crc_checker_718 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[50].u1) | crc_checker_718 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_875 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u0 | top_synch_719 | 42(0.01%) | 15(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u0) | top_synch_719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_870 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_871 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_872 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_873 | 19(0.01%) | 7(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_873 | 11(0.01%) | 7(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_874 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[51].u1 | crc_checker_720 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[51].u1) | crc_checker_720 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_868 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u0 | top_synch_721 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u0) | top_synch_721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_863 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_864 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_865 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_866 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_866 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_867 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[52].u1 | crc_checker_722 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[52].u1) | crc_checker_722 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_861 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u0 | top_synch_723 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u0) | top_synch_723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_857 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_858 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_859 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_859 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_860 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[53].u1 | crc_checker_724 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[53].u1) | crc_checker_724 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_854 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u0 | top_synch_725 | 39(0.01%) | 12(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u0) | top_synch_725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_849 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_850 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_851 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_852 | 15(0.01%) | 3(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_852 | 7(0.01%) | 3(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_853 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[54].u1 | crc_checker_726 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[54].u1) | crc_checker_726 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_847 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u0 | top_synch_727 | 272(0.08%) | 23(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u0) | top_synch_727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_842 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_843 | 230(0.07%) | 2(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_844 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_845 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_845 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_846 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[55].u1 | crc_checker_728 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[55].u1) | crc_checker_728 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_840 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u0 | top_synch_729 | 44(0.01%) | 17(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u0) | top_synch_729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_835 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_836 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_837 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_838 | 20(0.01%) | 8(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_838 | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_839 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[56].u1 | crc_checker_730 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[56].u1) | crc_checker_730 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_833 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u0 | top_synch_731 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u0) | top_synch_731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_829 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_830 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_831 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_831 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_832 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[57].u1 | crc_checker_732 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[57].u1) | crc_checker_732 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_826 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u0 | top_synch_733 | 39(0.01%) | 12(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u0) | top_synch_733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_822 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_823 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_824 | 15(0.01%) | 3(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_824 | 7(0.01%) | 3(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_825 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[58].u1 | crc_checker_734 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[58].u1) | crc_checker_734 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_819 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u0 | top_synch_735 | 275(0.08%) | 26(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u0) | top_synch_735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_815 | 233(0.07%) | 5(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_816 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_817 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_817 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_818 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[59].u1 | crc_checker_736 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[59].u1) | crc_checker_736 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_812 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u0 | top_synch_737 | 268(0.08%) | 19(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u0) | top_synch_737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_807 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_808 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_809 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_810 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_810 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_811 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[5].u1 | crc_checker_738 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[5].u1) | crc_checker_738 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_805 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u0 | top_synch_739 | 270(0.08%) | 21(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u0) | top_synch_739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_801 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_802 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_803 | 33(0.01%) | 12(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_803 | 13(0.01%) | 12(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_804 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[60].u1 | crc_checker_740 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[60].u1) | crc_checker_740 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_798 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u0 | top_synch_741 | 44(0.01%) | 17(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u0) | top_synch_741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_794 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_795 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_796 | 20(0.01%) | 8(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_796 | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_797 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[61].u1 | crc_checker_742 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[61].u1) | crc_checker_742 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_791 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u0 | top_synch_743 | 39(0.01%) | 12(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u0) | top_synch_743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_786 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_787 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_788 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_789 | 15(0.01%) | 3(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_789 | 7(0.01%) | 3(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_790 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[62].u1 | crc_checker_744 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[62].u1) | crc_checker_744 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_784 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u0 | top_synch_745 | 47(0.01%) | 20(0.01%) | 0(0.00%) | 27(0.02%) | 99(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u0) | top_synch_745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_778 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_779 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_780 | 15(0.01%) | 0(0.00%) | 0(0.00%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_781 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_782 | 20(0.01%) | 8(0.01%) | 0(0.00%) | 12(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_782 | 12(0.01%) | 8(0.01%) | 0(0.00%) | 4(0.01%) | 74(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_783 | 8(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[63].u1 | crc_checker_746 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[63].u1) | crc_checker_746 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_777 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u0 | top_synch_747 | 304(0.09%) | 55(0.02%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u0) | top_synch_747 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_771 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_772 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_773 | 266(0.08%) | 38(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_774 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_775 | 27(0.01%) | 6(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_775 | 7(0.01%) | 6(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_776 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[6].u1 | crc_checker_748 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[6].u1) | crc_checker_748 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_770 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u0 | top_synch_749 | 271(0.08%) | 22(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u0) | top_synch_749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_765 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_766 | 230(0.07%) | 2(0.01%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_767 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_768 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_768 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_769 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[7].u1 | crc_checker_750 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[7].u1) | crc_checker_750 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_763 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u0 | top_synch_751 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u0) | top_synch_751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type_757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable_758 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226_759 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm_760 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1_761 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1_761 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35_762 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[8].u1 | crc_checker_752 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[8].u1) | crc_checker_752 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_756 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u0 | top_synch_753 | 269(0.08%) | 20(0.01%) | 0(0.00%) | 249(0.14%) | 601(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u0) | top_synch_753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | dtype | d_type | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | latch | latch_enable | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | shift_register | SRLC32E_226 | 228(0.07%) | 0(0.00%) | 0(0.00%) | 228(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | state_machine | tac_sm | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_1 | synch_stage_1 | 32(0.01%) | 11(0.01%) | 0(0.00%) | 21(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_1) | synch_stage_1 | 12(0.01%) | 11(0.01%) | 0(0.00%) | 1(0.01%) | 576(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | SRL_16E_35 | SRL16E_35 | 20(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch_gen[9].u1 | crc_checker_754 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (synch_gen[9].u1) | crc_checker_754 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | RX | osum_crc9d32_755 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bcn_cntr | local_bcn_counter | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_A1 | io_delay | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_selectio_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_A2 | io_delay_HD6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_selectio_wiz_HD7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_B1 | io_delay_HD8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_selectio_wiz_HD9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_B2 | io_delay_HD10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_selectio_wiz_HD11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_BC_A | io_delay2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay2_selectio_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_BC_B | io_delay2_HD18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay2_selectio_wiz_HD19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_BC_C | io_delay2_HD20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay2_selectio_wiz_HD21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_C1 | io_delay_HD12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_selectio_wiz_HD13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.IO_DELAY_C2 | io_delay_HD14 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | io_delay_selectio_wiz_HD15 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.Merging_Module | IPBusTopMergingModule | 3433(0.99%) | 3353(0.97%) | 0(0.00%) | 80(0.05%) | 10408(1.50%) | 5(0.42%) | 0(0.00%) | 0(0.00%) | | (GLOBAL_MERGE.Merging_Module) | IPBusTopMergingModule | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 79(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPBUS_MERGING_REGISTERS | ipbus_ctrlreg_v__parameterized10 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOBMerging | TopSortingModule__parameterized0 | 678(0.20%) | 678(0.20%) | 0(0.00%) | 0(0.00%) | 1536(0.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (TOBMerging) | TopSortingModule__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 163(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER | ParallelSorter | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 457(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER) | ParallelSorter | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_600 | 107(0.03%) | 107(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_601 | 91(0.03%) | 91(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifFirst.sorter_gen0[0].PAR_SORTER | ParallelSorter__parameterized1 | 228(0.07%) | 228(0.07%) | 0(0.00%) | 0(0.00%) | 458(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifFirst.sorter_gen0[0].PAR_SORTER) | ParallelSorter__parameterized1 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo_598 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_599 | 96(0.03%) | 96(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | stage_gen[1].ifFirst.sorter_gen0[1].PAR_SORTER | ParallelSorter__parameterized1_596 | 229(0.07%) | 229(0.07%) | 0(0.00%) | 0(0.00%) | 458(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (stage_gen[1].ifFirst.sorter_gen0[1].PAR_SORTER) | ParallelSorter__parameterized1_596 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 62(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_1 | FastFifo | 110(0.03%) | 110(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | FastFifo_2 | FastFifo_597 | 116(0.03%) | 116(0.03%) | 0(0.00%) | 0(0.00%) | 198(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | TOB_SYNCH_OFFSET | TOB_synch | 2292(0.66%) | 2292(0.66%) | 0(0.00%) | 0(0.00%) | 8432(1.22%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inputRAM_1 | ipbus_sorting_outputRAM_wrapper__xdcDup__1 | 60(0.02%) | 44(0.01%) | 0(0.00%) | 16(0.01%) | 50(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_1) | ipbus_sorting_outputRAM_wrapper__xdcDup__1 | 60(0.02%) | 44(0.01%) | 0(0.00%) | 16(0.01%) | 50(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inputRAM_2 | ipbus_sorting_outputRAM_wrapper__xdcDup__2 | 75(0.02%) | 59(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_2) | ipbus_sorting_outputRAM_wrapper__xdcDup__2 | 75(0.02%) | 59(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_9_HD486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_9_synth_HD487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inputRAM_3 | ipbus_sorting_outputRAM_wrapper__xdcDup__3 | 68(0.02%) | 52(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_3) | ipbus_sorting_outputRAM_wrapper__xdcDup__3 | 68(0.02%) | 52(0.02%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_9_HD493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_9_synth_HD494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inputRAM_4 | ipbus_sorting_outputRAM_wrapper__xdcDup__4 | 56(0.02%) | 40(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (inputRAM_4) | ipbus_sorting_outputRAM_wrapper__xdcDup__4 | 56(0.02%) | 40(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM_HD499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_9_HD500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_9_synth_HD501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top_HD502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr_HD503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width_HD504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper_HD505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | outputRAM | ipbus_sorting_outputRAM_wrapper | 40(0.01%) | 24(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (outputRAM) | ipbus_sorting_outputRAM_wrapper | 40(0.01%) | 24(0.01%) | 0(0.00%) | 16(0.01%) | 46(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ALGO_OUTPUT_RAM | SortingOutputRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | SortingOutputRAM_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | SortingOutputRAM_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | SortingOutputRAM_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | SortingOutputRAM_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | SortingOutputRAM_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | SortingOutputRAM_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GLOBAL_MERGE.tx_phase_adjust | efex_topo_tx | 185(0.05%) | 181(0.05%) | 0(0.00%) | 4(0.01%) | 231(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (GLOBAL_MERGE.tx_phase_adjust) | efex_topo_tx | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 82(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Latome_crc | osum_crc9d32 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | efex_topo_sm | efex_topo_frame_sm | 177(0.05%) | 177(0.05%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_TX_RX | MGT_4_quad_gen | 9893(2.86%) | 9893(2.86%) | 0(0.00%) | 0(0.00%) | 17936(2.59%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[0].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__1 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__1 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__1 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__1 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_594 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD521 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD522 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD522 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD523 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD523 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD526 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD526 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD527 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD529 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD530 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD534 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD534 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD535 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD536 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD537 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD538 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD539 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD540 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD541 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD543 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD544 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD545 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD546 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD547 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD547 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD548 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD550 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD554 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD554 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD556 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD557 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD557 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD558 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD560 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD561 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD565 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD565 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD566 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD568 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD572 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD572 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD574 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD575 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD575 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD576 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD578 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD579 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD583 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD583 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD584 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD586 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD590 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD590 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD592 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD593 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD593 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD594 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD596 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD597 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD601 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD601 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD602 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD604 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD608 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD610 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD611 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD612 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[10].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__11 | 615(0.18%) | 615(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__11 | 615(0.18%) | 615(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__11 | 615(0.18%) | 615(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_591 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD705 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD706 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD706 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD707 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD710 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD710 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD711 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD713 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD718 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD718 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD719 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD720 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD721 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD722 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD724 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD725 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD727 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD728 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD729 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD730 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD731 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD731 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD732 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD738 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD738 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD740 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD741 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD741 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD742 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD744 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD749 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD749 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD750 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD756 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD756 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD758 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD759 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD759 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD760 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD762 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD763 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD767 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD767 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD768 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD770 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD774 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD774 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD776 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD777 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD777 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD778 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD780 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD781 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD785 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD785 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD786 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD788 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD792 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD794 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD795 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD796 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[14].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__12 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__12 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__12 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__12 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_588 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD797 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD798 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD798 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD799 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD799 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD802 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD802 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD803 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD805 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD810 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD810 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD811 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD812 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD813 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD814 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD815 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD816 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD817 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD819 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD820 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD822 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD823 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD823 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD824 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD830 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD830 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD832 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD833 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD833 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD834 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD836 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD837 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD841 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD841 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD842 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD844 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD848 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD848 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD850 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD851 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD851 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD852 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD854 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD855 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD859 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD859 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD860 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD862 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD866 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD866 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD868 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD869 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD869 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD870 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD872 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD873 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD877 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD877 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD878 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD880 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD884 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD886 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD887 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD888 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[15].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__13 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__13 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__13 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__13 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_585 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD889 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD890 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD890 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD891 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD891 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD894 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD894 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD895 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD897 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD902 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD902 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD903 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD904 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD905 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD906 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD907 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD908 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD909 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD910 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD911 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD913 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD914 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD915 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD915 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD916 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD918 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD922 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD922 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD924 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD925 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD925 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD926 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD928 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD929 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD933 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD933 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD934 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD936 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD940 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD940 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD942 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD943 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD943 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD944 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD946 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD947 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD951 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD951 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD952 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD954 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD958 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD958 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD960 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD961 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD961 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD962 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD964 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD969 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD969 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD970 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD972 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD976 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD977 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD978 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD979 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD980 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[17].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__14 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__14 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__14 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__14 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_582 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD981 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD982 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD982 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD983 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD983 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD986 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD986 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD987 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD989 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD990 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD994 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD994 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD995 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD996 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD997 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD999 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1000 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1001 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1002 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1003 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1005 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1006 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1007 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1007 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1008 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1010 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1014 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1014 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1016 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1017 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1017 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1018 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1020 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1021 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1025 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1025 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1026 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1028 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1032 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1032 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1034 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1035 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1035 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1036 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1038 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1039 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1043 | 62(0.02%) | 62(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1043 | 56(0.02%) | 56(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1044 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1046 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1050 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1050 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1052 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1053 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1053 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1054 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1056 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1057 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1061 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1061 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1062 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1064 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1068 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1069 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1070 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1071 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1072 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[18].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__15 | 618(0.18%) | 618(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__15 | 618(0.18%) | 618(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__15 | 618(0.18%) | 618(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__15 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_579 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1073 | 603(0.17%) | 603(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1074 | 603(0.17%) | 603(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1074 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1075 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1075 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1078 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1078 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1079 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1081 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1082 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1086 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1086 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1088 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1089 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1090 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1091 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1092 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1093 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1094 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1095 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1096 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1097 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1098 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1099 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1099 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1100 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1102 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1106 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1106 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1108 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1109 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1109 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1110 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1112 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1113 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1117 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1117 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1118 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1120 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1124 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1124 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1126 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1127 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1127 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1128 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1130 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1135 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1135 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1136 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1138 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1142 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1142 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1144 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1145 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1145 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1146 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1148 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1149 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1153 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1153 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1154 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1156 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1160 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1161 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1162 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1164 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[19].mgt_1quad_Rx_Tx | mgt_selection_wrapper | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_576 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[1].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__2 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__2 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__2 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__2 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_573 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1165 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1166 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1166 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1167 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1167 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1170 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1170 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1171 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1173 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1174 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1178 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1178 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1179 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1180 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1181 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1182 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1184 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1185 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1186 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1187 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1188 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1189 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1190 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1191 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1191 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1192 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1194 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1198 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1198 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1200 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1201 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1201 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1202 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1204 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1205 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1209 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1209 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1210 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1212 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1216 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1216 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1218 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1219 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1219 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1220 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1222 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1223 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1227 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1227 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1228 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1230 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1234 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1234 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1236 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1237 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1237 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1238 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1240 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1241 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1245 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1245 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1246 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1252 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1253 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1254 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1255 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1256 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[2].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__3 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__3 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__3 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__3 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_570 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1257 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1258 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1258 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1259 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1259 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1262 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1262 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1263 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1265 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1266 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1270 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1270 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1271 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1272 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1273 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1274 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1276 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1277 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1278 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1279 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1280 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1281 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1282 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1283 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1283 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1284 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1286 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1290 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1290 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1292 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1293 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1293 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1294 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1296 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1301 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1301 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1302 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1304 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1308 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1308 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1310 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1311 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1311 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1312 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1314 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1315 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1319 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1319 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1320 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1322 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1326 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1326 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1328 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1329 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1329 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1330 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1332 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1333 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1337 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1337 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1338 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1340 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1344 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1346 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1347 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1348 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[3].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__4 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__4 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__4 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__4 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_567 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1349 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1350 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1350 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1351 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1351 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1354 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1354 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1355 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1357 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1362 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1362 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1363 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1364 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1365 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1366 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1368 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1369 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1371 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1373 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1374 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1375 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1375 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1376 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1378 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1382 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1382 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1384 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1385 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1385 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1386 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1388 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1389 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1393 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1393 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1394 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1396 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1400 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1400 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1402 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1403 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1403 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1404 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1406 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1407 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1411 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1411 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1412 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1414 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1418 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1418 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1420 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1421 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1421 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1422 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1424 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1425 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1429 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1429 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1430 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1432 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1436 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1437 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1438 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1439 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1440 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[4].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__5 | 618(0.18%) | 618(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__5 | 618(0.18%) | 618(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__5 | 618(0.18%) | 618(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__5 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_564 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1441 | 603(0.17%) | 603(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1442 | 603(0.17%) | 603(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1442 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1443 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1443 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1446 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1446 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1447 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1449 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1450 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1454 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1454 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1455 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1456 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1457 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1458 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1459 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1460 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1461 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1462 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1463 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1464 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1465 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1466 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1467 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1467 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1468 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1470 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1474 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1474 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1476 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1477 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1477 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1478 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1480 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1481 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1485 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1485 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1486 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1488 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1492 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1492 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1494 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1495 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1495 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1496 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1498 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1503 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1503 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1504 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1506 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1510 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1510 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1512 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1513 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1513 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1514 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1516 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1517 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1521 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1521 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1522 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1524 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1528 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1529 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1530 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1531 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1532 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[5].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__6 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__6 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__6 | 619(0.18%) | 619(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__6 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_561 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1533 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1534 | 604(0.17%) | 604(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1534 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1535 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1535 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1538 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1538 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1539 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1541 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1542 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1546 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1546 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1547 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1548 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1549 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1550 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1551 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1552 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1553 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1554 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1555 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1557 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1558 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1559 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1559 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1560 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1562 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1566 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1566 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1568 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1569 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1569 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1570 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1572 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1573 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1577 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1577 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1578 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1580 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1584 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1584 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1586 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1587 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1587 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1588 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1590 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1591 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1595 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1595 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1596 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1598 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1602 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1602 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1604 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1605 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1605 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1606 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1608 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1609 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1613 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1613 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1614 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1616 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1620 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1621 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1622 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1623 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1624 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[6].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__7 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__7 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__7 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__7 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_558 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1625 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1626 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1626 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1627 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1627 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1630 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1630 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1631 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1633 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1638 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1638 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1639 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1640 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1641 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1643 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1644 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1645 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1646 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1647 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1648 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1649 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1651 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1651 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1652 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1654 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1658 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1658 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1660 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1661 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1661 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1662 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1664 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1665 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1669 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1669 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1670 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1672 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1676 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1676 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1678 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1679 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1679 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1680 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1682 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1683 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1687 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1687 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1688 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1690 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1694 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1694 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1696 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1697 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1697 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1698 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1700 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1705 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1705 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1706 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1708 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1712 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1713 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1714 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1715 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1716 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[7].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__8 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__8 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__8 | 617(0.18%) | 617(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__8 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_555 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1717 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1718 | 602(0.17%) | 602(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1718 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1719 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1719 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1722 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1722 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1723 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1725 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1726 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1730 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1730 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1731 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1732 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1733 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1734 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1735 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1736 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1737 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1738 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1739 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1740 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1741 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1742 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1743 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1743 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1744 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1746 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1750 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1750 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1752 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1753 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1753 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1754 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1756 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1757 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1761 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1761 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1762 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1764 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1768 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1768 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1770 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1771 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1771 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1772 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1774 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1775 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1779 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1779 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1780 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1782 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1786 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1786 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1788 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1789 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1789 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1790 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1792 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1793 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1797 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1797 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1798 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1800 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1804 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1805 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1806 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1807 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1808 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[8].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__9 | 616(0.18%) | 616(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__9 | 616(0.18%) | 616(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__9 | 616(0.18%) | 616(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__9 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common_551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset_552 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE_553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD1809 | 601(0.17%) | 601(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD1810 | 601(0.17%) | 601(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD1810 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1811 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD1811 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD1812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD1813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1814 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD1814 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD1815 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD1816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD1817 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD1818 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD1819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD1820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD1821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1822 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD1822 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD1823 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD1824 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD1825 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD1826 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD1827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD1828 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD1829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD1830 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD1831 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD1832 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD1833 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD1834 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1835 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD1835 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD1836 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD1837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD1838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD1839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD1840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD1841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1842 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD1842 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD1843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD1844 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1845 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD1845 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD1846 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD1847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD1848 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD1849 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD1850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD1851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD1852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1853 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD1853 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD1854 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD1855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD1856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD1857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD1858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD1859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1860 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD1860 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD1861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD1862 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1863 | 68(0.02%) | 68(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD1863 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD1864 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD1865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD1866 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD1867 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD1868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD1869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD1870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1871 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD1871 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD1872 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD1873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD1874 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD1875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD1876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD1877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1878 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD1878 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD1879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD1880 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1881 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD1881 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD1882 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD1883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD1884 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD1885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD1886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD1887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD1888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1889 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD1889 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD1890 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD1891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD1892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD1893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD1894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD1895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD1896 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD1897 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD1898 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD1899 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD1900 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GEN[9].mgt_1quad_Rx_Tx | mgt_selection_wrapper__xdcDup__10 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_ENABLED.mgt | min_latency_1quad_11g2_RxTX_wrapper__xdcDup__10 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_support_i | min_latency_1_quad_rx_tx_support__xdcDup__10 | 620(0.18%) | 620(0.18%) | 0(0.00%) | 0(0.00%) | 1121(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (min_latency_1_quad_rx_tx_support_i) | min_latency_1_quad_rx_tx_support__xdcDup__10 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common0_i | min_latency_1_quad_rx_tx_common | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | common_reset_i | min_latency_1_quad_rx_tx_common_reset | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt_usrclk_source | min_latency_1_quad_rx_tx_GT_USRCLK_SOURCE | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_init_i | min_latency_1_quad_rx_tx_HD613 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0 | min_latency_1_quad_rx_tx_init_HD614 | 605(0.17%) | 605(0.17%) | 0(0.00%) | 0(0.00%) | 1109(0.16%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U0) | min_latency_1_quad_rx_tx_init_HD614 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_HD615 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_80_HD616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_81_HD617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD618 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_HD618 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_73_HD619 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_74_HD620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_75_HD621 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_76_HD622 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_77_HD623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_78_HD624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_79_HD625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_tx_manual_phase_i | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD626 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 127(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_tx_manual_phase_i) | min_latency_1_quad_rx_tx_TX_MANUAL_PHASE_ALIGN_HD626 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_62_HD627 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_63_HD628 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[0].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_HD629 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_64_HD630 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_65_HD631 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[1].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_66_HD632 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_67_HD633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_68_HD634 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[2].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_69_HD635 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXDLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_70_HD636 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_71_HD637 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cdc[3].sync_TXPHINITDONE | min_latency_1_quad_rx_tx_sync_pulse_72_HD638 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD639 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt0_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_HD639 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_56_HD640 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_57_HD641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_58_HD642 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_59_HD643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_60_HD644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_61_HD645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD646 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_0_HD646 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_54_HD647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_55_HD648 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD649 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_1_HD649 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_47_HD650 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_48_HD651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_49_HD652 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_50_HD653 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_51_HD654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_52_HD655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_53_HD656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD657 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt1_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_2_HD657 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_41_HD658 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_42_HD659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_43_HD660 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_44_HD661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_45_HD662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_46_HD663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD664 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_3_HD664 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_39_HD665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_40_HD666 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD667 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_4_HD667 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_32_HD668 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_33_HD669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_34_HD670 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_35_HD671 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_36_HD672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_37_HD673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_38_HD674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD675 | 63(0.02%) | 63(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt2_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_5_HD675 | 57(0.02%) | 57(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_26_HD676 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_27_HD677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_28_HD678 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_29_HD679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_30_HD680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_31_HD681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rx_auto_phase_align_i | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD682 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rx_auto_phase_align_i) | min_latency_1_quad_rx_tx_AUTO_PHASE_ALIGN_6_HD682 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_DLYSRESETDONE | min_latency_1_quad_rx_tx_sync_block_24_HD683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_PHALIGNDONE | min_latency_1_quad_rx_tx_sync_block_25_HD684 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_rxresetfsm_i | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD685 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 113(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_rxresetfsm_i) | min_latency_1_quad_rx_tx_RX_STARTUP_FSM_7_HD685 | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_17_HD686 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_RXRESETDONE | min_latency_1_quad_rx_tx_sync_block_18_HD687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_data_valid | min_latency_1_quad_rx_tx_sync_block_19_HD688 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_20_HD689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_21_HD690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_rx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_22_HD691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_23_HD692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_txresetfsm_i | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD693 | 65(0.02%) | 65(0.02%) | 0(0.00%) | 0(0.00%) | 112(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gt3_txresetfsm_i) | min_latency_1_quad_rx_tx_TX_STARTUP_FSM_8_HD693 | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 76(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_QPLLLOCK | min_latency_1_quad_rx_tx_sync_block_HD694 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_TXRESETDONE | min_latency_1_quad_rx_tx_sync_block_12_HD695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_mmcm_lock_reclocked | min_latency_1_quad_rx_tx_sync_block_13_HD696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_run_phase_alignment_int | min_latency_1_quad_rx_tx_sync_block_14_HD697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_time_out_wait_bypass | min_latency_1_quad_rx_tx_sync_block_15_HD698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sync_tx_fsm_reset_done_int | min_latency_1_quad_rx_tx_sync_block_16_HD699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_multi_gt_HD700 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt0_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_HD701 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt1_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_9_HD702 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt2_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_10_HD703 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gt3_min_latency_1_quad_rx_tx_i | min_latency_1_quad_rx_tx_GT_11_HD704 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_IF.MGT_ipb | mgt_slaves | 25408(7.33%) | 25408(7.33%) | 0(0.00%) | 0(0.00%) | 8561(1.24%) | 512(43.39%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[0].quad | mgt_quad_slaves__xdcDup__1 | 1875(0.54%) | 1875(0.54%) | 0(0.00%) | 0(0.00%) | 554(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[0].quad) | mgt_quad_slaves__xdcDup__1 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__1 | 565(0.16%) | 565(0.16%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_546 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_547 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_548 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_549 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__1 | 483(0.14%) | 483(0.14%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__1 | 475(0.14%) | 475(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_550 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__2 | 574(0.17%) | 574(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_541 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_542 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_543 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_544 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__2 | 492(0.14%) | 492(0.14%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__2 | 484(0.14%) | 484(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_545 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__3 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_536 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_537 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_538 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_539 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__3 | 136(0.04%) | 136(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__3 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_540 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__4 | 442(0.13%) | 442(0.13%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_531 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_532 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_533 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_534 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__4 | 359(0.10%) | 359(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__4 | 351(0.10%) | 351(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_535 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_524 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_526 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 60(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_529 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_530 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[10].quad | mgt_quad_slaves__xdcDup__11 | 354(0.10%) | 354(0.10%) | 0(0.00%) | 0(0.00%) | 395(0.06%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[10].quad) | mgt_quad_slaves__xdcDup__11 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__41 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_520 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_521 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_522 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__41 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__41 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_523 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__42 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_516 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_517 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_518 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__42 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__42 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_519 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__43 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 65(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_512 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_513 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_514 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__43 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__43 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_515 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__44 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 66(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_508 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_509 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_510 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__44 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_511 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_503 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_505 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_506 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_507 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[14].quad | mgt_quad_slaves__xdcDup__12 | 1334(0.39%) | 1334(0.39%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[14].quad) | mgt_quad_slaves__xdcDup__12 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__57 | 429(0.12%) | 429(0.12%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__57 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_496 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_497 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_498 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_499 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__57 | 346(0.10%) | 346(0.10%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__57 | 338(0.10%) | 338(0.10%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_500 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__58 | 511(0.15%) | 511(0.15%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__58 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_491 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_492 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_493 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_494 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__58 | 429(0.12%) | 429(0.12%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__58 | 421(0.12%) | 421(0.12%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_495 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__59 | 216(0.06%) | 216(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__59 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_486 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_487 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_488 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_489 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__59 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__59 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_490 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__60 | 103(0.03%) | 103(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__60 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_481 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_482 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_483 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_484 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__60 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__60 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_485 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_474 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_476 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_478 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_479 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_480 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[15].quad | mgt_quad_slaves__xdcDup__13 | 482(0.14%) | 482(0.14%) | 0(0.00%) | 0(0.00%) | 526(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[15].quad) | mgt_quad_slaves__xdcDup__13 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__61 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__61 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_469 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_470 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_471 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_472 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__61 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__61 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_473 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__62 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__62 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_464 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_465 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_466 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_467 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__62 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__62 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_468 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__63 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__63 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_459 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_460 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_461 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_462 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__63 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__63 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_463 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__64 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__64 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_454 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_455 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_456 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_457 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__64 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__64 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_458 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_449 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_451 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_452 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_453 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[17].quad | mgt_quad_slaves__xdcDup__14 | 1319(0.38%) | 1319(0.38%) | 0(0.00%) | 0(0.00%) | 542(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[17].quad) | mgt_quad_slaves__xdcDup__14 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__69 | 387(0.11%) | 387(0.11%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__69 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_442 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_443 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_444 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_445 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__69 | 301(0.09%) | 301(0.09%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__69 | 293(0.08%) | 293(0.08%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_446 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__70 | 530(0.15%) | 530(0.15%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__70 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_437 | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_438 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_439 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_440 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__70 | 444(0.13%) | 444(0.13%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__70 | 436(0.13%) | 436(0.13%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2817 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2818 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_441 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__71 | 108(0.03%) | 108(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__71 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_432 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_433 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_434 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_435 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__71 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__71 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2819 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2821 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2822 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2823 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2825 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2827 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2829 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2837 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_436 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__72 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__72 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_427 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_428 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_429 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_430 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__72 | 134(0.04%) | 134(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__72 | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2845 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2847 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2849 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2850 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2851 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2853 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_431 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_420 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_422 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_424 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_425 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_426 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[18].quad | mgt_quad_slaves__xdcDup__15 | 1378(0.40%) | 1378(0.40%) | 0(0.00%) | 0(0.00%) | 538(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[18].quad) | mgt_quad_slaves__xdcDup__15 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__73 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__73 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_415 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_416 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_417 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_418 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__73 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__73 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2873 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2874 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2875 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2877 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2878 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2881 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_419 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__74 | 880(0.25%) | 880(0.25%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__74 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_410 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_411 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_412 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_413 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__74 | 798(0.23%) | 798(0.23%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__74 | 789(0.23%) | 789(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2883 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2885 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2893 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2901 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2902 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_414 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__75 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__75 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_405 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_406 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_407 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_408 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__75 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__75 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2907 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2909 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2911 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2913 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2921 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_409 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__76 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__76 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_400 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_401 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_402 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_403 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__76 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__76 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2929 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2930 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2931 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2933 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2941 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_404 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_395 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 44(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_397 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_398 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_399 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[19].quad | mgt_quad_slaves | 1272(0.37%) | 1272(0.37%) | 0(0.00%) | 0(0.00%) | 530(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[19].quad) | mgt_quad_slaves | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__77 | 889(0.26%) | 889(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__77 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_388 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_389 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_390 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_391 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__77 | 807(0.23%) | 807(0.23%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__77 | 799(0.23%) | 799(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD1979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD1980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD1981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD1982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD1983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD1984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD1985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD1986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD1987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD1988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD1989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD1990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD1991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD1992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD1993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD1994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD1995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD1996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD1997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD1998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD1999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_392 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__78 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__78 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_383 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_384 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_385 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_386 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__78 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__78 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_387 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__79 | 102(0.03%) | 102(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__79 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_378 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_379 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_380 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_381 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__79 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__79 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_382 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information | 104(0.03%) | 104(0.03%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_373 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_374 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_375 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_376 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_377 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_366 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_368 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_370 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_371 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_372 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[1].quad | mgt_quad_slaves__xdcDup__2 | 1506(0.43%) | 1506(0.43%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[1].quad) | mgt_quad_slaves__xdcDup__2 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__5 | 511(0.15%) | 511(0.15%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_361 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_362 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_363 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_364 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__5 | 429(0.12%) | 429(0.12%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__5 | 421(0.12%) | 421(0.12%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2949 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2957 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2958 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2961 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2962 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2963 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2965 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_365 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__6 | 479(0.14%) | 479(0.14%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_356 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_357 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_358 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_359 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__6 | 397(0.11%) | 397(0.11%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__6 | 389(0.11%) | 389(0.11%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2967 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2969 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_360 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__7 | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__7 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_351 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_352 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_353 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_354 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__7 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__7 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2987 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2989 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2990 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2991 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2993 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2995 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2997 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3005 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_355 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__8 | 222(0.06%) | 222(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__8 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_346 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_347 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_348 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_349 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__8 | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__8 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3013 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3021 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_350 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_339 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_341 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_343 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_344 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_345 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[2].quad | mgt_quad_slaves__xdcDup__3 | 1794(0.52%) | 1794(0.52%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[2].quad) | mgt_quad_slaves__xdcDup__3 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__9 | 683(0.20%) | 683(0.20%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_334 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_335 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_336 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_337 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__9 | 601(0.17%) | 601(0.17%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__9 | 593(0.17%) | 593(0.17%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3101 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3102 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_338 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__10 | 575(0.17%) | 575(0.17%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__10 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_329 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_330 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_331 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_332 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__10 | 493(0.14%) | 493(0.14%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__10 | 485(0.14%) | 485(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3033 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3041 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3042 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3043 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3045 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3047 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3049 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_333 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__11 | 218(0.06%) | 218(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__11 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_324 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_325 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_326 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_327 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__11 | 136(0.04%) | 136(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__11 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3051 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3053 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3061 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3069 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3070 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_328 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__12 | 243(0.07%) | 243(0.07%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__12 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_319 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_320 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_321 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_322 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__12 | 160(0.05%) | 160(0.05%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__12 | 152(0.04%) | 152(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3071 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3073 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3074 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3075 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3077 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3081 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3089 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_323 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_312 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_314 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_316 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_317 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[3].quad | mgt_quad_slaves__xdcDup__4 | 2410(0.70%) | 2410(0.70%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[3].quad) | mgt_quad_slaves__xdcDup__4 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__13 | 958(0.28%) | 958(0.28%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__13 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_307 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_308 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_309 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_310 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__13 | 876(0.25%) | 876(0.25%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__13 | 868(0.25%) | 868(0.25%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3125 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3130 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3131 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3132 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3133 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_311 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__14 | 906(0.26%) | 906(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__14 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_302 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_303 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_304 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_305 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__14 | 824(0.24%) | 824(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__14 | 816(0.24%) | 816(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3147 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3148 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3149 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3150 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3154 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_306 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__15 | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__15 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_297 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_298 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_299 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_300 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__15 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__15 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3155 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3157 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3158 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3160 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3161 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3163 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3164 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3165 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3173 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_301 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__16 | 251(0.07%) | 251(0.07%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__16 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_292 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_293 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_294 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_295 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__16 | 167(0.05%) | 167(0.05%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__16 | 159(0.05%) | 159(0.05%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3181 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3182 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3187 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3188 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3189 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3191 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3192 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3193 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_296 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_285 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_287 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_289 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_290 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_291 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[4].quad | mgt_quad_slaves__xdcDup__5 | 2340(0.68%) | 2340(0.68%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[4].quad) | mgt_quad_slaves__xdcDup__5 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__17 | 913(0.26%) | 913(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__17 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_280 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_281 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_282 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_283 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__17 | 831(0.24%) | 831(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__17 | 823(0.24%) | 823(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3201 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3202 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3203 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3204 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3209 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3210 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3211 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3213 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_284 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__18 | 909(0.26%) | 909(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__18 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_275 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_276 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_277 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_278 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__18 | 827(0.24%) | 827(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__18 | 819(0.24%) | 819(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3220 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3221 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3229 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3230 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3231 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3233 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3235 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3237 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3238 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_279 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__19 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__19 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_270 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_271 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_272 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_273 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__19 | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__19 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3241 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3242 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3243 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3244 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3245 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3247 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3248 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3249 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_274 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__20 | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__20 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_265 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_266 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_267 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_268 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__20 | 136(0.04%) | 136(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__20 | 128(0.04%) | 128(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3260 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3262 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3267 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3269 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3270 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3271 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3272 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3273 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3275 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3276 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3277 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_269 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_258 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_260 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_261 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_262 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_263 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_264 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[5].quad | mgt_quad_slaves__xdcDup__6 | 2329(0.67%) | 2329(0.67%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[5].quad) | mgt_quad_slaves__xdcDup__6 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__21 | 907(0.26%) | 907(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_253 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_254 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_255 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_256 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__21 | 825(0.24%) | 825(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__21 | 817(0.24%) | 817(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3285 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3287 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3288 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3289 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3290 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3291 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3293 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3300 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3301 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_257 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__22 | 909(0.26%) | 909(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_248 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_249 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_250 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_251 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__22 | 827(0.24%) | 827(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__22 | 818(0.24%) | 818(0.24%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3313 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3314 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3315 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3316 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3317 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3318 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3321 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3322 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_252 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__23 | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__23 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_243 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_244 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_245 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_246 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__23 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__23 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3323 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3325 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3327 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3328 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3329 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3331 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3332 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3333 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3341 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3342 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_247 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__24 | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__24 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_238 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_239 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_240 | 20(0.01%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_241 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__24 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__24 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3347 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3349 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3350 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3351 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3353 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3354 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3355 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3356 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3357 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3360 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3361 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_242 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_231 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_232 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_233 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_234 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_235 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_236 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_237 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[6].quad | mgt_quad_slaves__xdcDup__7 | 2324(0.67%) | 2324(0.67%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[6].quad) | mgt_quad_slaves__xdcDup__7 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__25 | 903(0.26%) | 903(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_226 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_227 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_228 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_229 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__25 | 821(0.24%) | 821(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__25 | 813(0.23%) | 813(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3369 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3370 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3371 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3372 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3373 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3381 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3382 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_230 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__26 | 903(0.26%) | 903(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_221 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_222 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_223 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_224 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__26 | 821(0.24%) | 821(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__26 | 813(0.23%) | 813(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3387 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3388 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3389 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3397 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3398 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3399 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3400 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3401 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3402 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3403 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3405 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3406 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_225 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__27 | 222(0.06%) | 222(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_216 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_217 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_218 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_219 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__27 | 140(0.04%) | 140(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__27 | 132(0.04%) | 132(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3407 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3409 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3410 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3411 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3412 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3413 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3415 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3416 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3417 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3425 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3426 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3427 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_220 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__28 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__28 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_211 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_212 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_213 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_214 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__28 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__28 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3428 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3429 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3430 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3431 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3433 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_215 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_204 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_205 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_206 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_207 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_208 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_209 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_210 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[7].quad | mgt_quad_slaves__xdcDup__8 | 2323(0.67%) | 2323(0.67%) | 0(0.00%) | 0(0.00%) | 550(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[7].quad) | mgt_quad_slaves__xdcDup__8 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__29 | 901(0.26%) | 901(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__29 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_199 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_200 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_201 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_202 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__29 | 819(0.24%) | 819(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__29 | 811(0.23%) | 811(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_203 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__30 | 904(0.26%) | 904(0.26%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__30 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_194 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_195 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_196 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_197 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__30 | 822(0.24%) | 822(0.24%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__30 | 814(0.23%) | 814(0.23%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_198 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__31 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__31 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_189 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_190 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_191 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_192 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__31 | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__31 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_193 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__32 | 222(0.06%) | 222(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__32 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_184 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_185 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_186 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_187 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__32 | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__32 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_188 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_177 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_179 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_181 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_182 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_183 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[8].quad | mgt_quad_slaves__xdcDup__9 | 1138(0.33%) | 1138(0.33%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[8].quad) | mgt_quad_slaves__xdcDup__9 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__33 | 304(0.09%) | 304(0.09%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_172 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_173 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_174 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_175 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__33 | 222(0.06%) | 222(0.06%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__33 | 214(0.06%) | 214(0.06%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_176 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__34 | 321(0.09%) | 321(0.09%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__34 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_167 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_168 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_169 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_170 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__34 | 239(0.07%) | 239(0.07%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__34 | 231(0.07%) | 231(0.07%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_171 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__35 | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__35 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_162 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_163 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_164 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_165 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__35 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__35 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_166 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__36 | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__36 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_157 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_158 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_159 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_160 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__36 | 137(0.04%) | 137(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__36 | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD3596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD3597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD3598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD3599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD3600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD3601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD3602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD3603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD3604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD3605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD3606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD3607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD3608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD3609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD3610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD3611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD3612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD3613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD3614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD3615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD3616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_161 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_150 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_151 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_152 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_153 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch_154 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_155 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_156 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | QUAD_FOR[9].quad | mgt_quad_slaves__xdcDup__10 | 1239(0.36%) | 1239(0.36%) | 0(0.00%) | 0(0.00%) | 546(0.08%) | 32(2.71%) | 0(0.00%) | 0(0.00%) | | (QUAD_FOR[9].quad) | mgt_quad_slaves__xdcDup__10 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT0 | gt_information__xdcDup__37 | 322(0.09%) | 322(0.09%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT0) | gt_information__xdcDup__37 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_145 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_146 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_147 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_148 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__37 | 240(0.07%) | 240(0.07%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__37 | 232(0.07%) | 232(0.07%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_149 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT1 | gt_information__xdcDup__38 | 400(0.12%) | 400(0.12%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT1) | gt_information__xdcDup__38 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_140 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_141 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_142 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_143 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__38 | 318(0.09%) | 318(0.09%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__38 | 310(0.09%) | 310(0.09%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_144 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT2 | gt_information__xdcDup__39 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT2) | gt_information__xdcDup__39 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0_135 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_136 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_137 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_138 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__39 | 139(0.04%) | 139(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__39 | 131(0.04%) | 131(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram_HD2504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9_HD2505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth_HD2506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top_HD2507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr_HD2508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width_HD2509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper_HD2510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0_HD2511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0_HD2512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1_HD2513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1_HD2514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2_HD2515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2_HD2516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3_HD2517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3_HD2518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4_HD2519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4_HD2520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5_HD2521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5_HD2522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6_HD2523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6_HD2524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram_139 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_GT3 | gt_information__xdcDup__40 | 221(0.06%) | 221(0.06%) | 0(0.00%) | 0(0.00%) | 98(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (MGT_GT3) | gt_information__xdcDup__40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_0 | counter__parameterized0 | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_1 | counter__parameterized0_132 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_2 | counter__parameterized0_133 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cntr_3 | counter__parameterized0_134 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | playback_ram | mgt_playback_ram_wrapper__xdcDup__40 | 138(0.04%) | 138(0.04%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | (playback_ram) | mgt_playback_ram_wrapper__xdcDup__40 | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | PLAYBACK_RAM | mgt_playback_ram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | U0 | mgt_playback_ram_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | mgt_playback_ram_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | mgt_playback_ram_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | valid.cstr | mgt_playback_ram_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | mgt_playback_ram_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized4 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized5 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | mgt_playback_ram_blk_mem_gen_prim_width__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | mgt_playback_ram_blk_mem_gen_prim_wrapper__parameterized6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | sm_playback | ctrl_playback_ram | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Control | ipbus_ctrlreg_v__parameterized2_126 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_PHASE | ipbus_ctrlreg_v__parameterized2_127 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Pulse | ipbus_ctrlreg_v__parameterized2_128 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | MGT_QUAD_Synch | ipbus_ctrlreg_v__parameterized2_129 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | error_counter_reset_pulse | led_stretch | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_rx_pulse | led_stretch_130 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | softreset_tx_pulse | led_stretch_131 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | READOUT_IF.Readout_block | Readout_logic_top | 15249(4.40%) | 15182(4.38%) | 0(0.00%) | 67(0.04%) | 51504(7.43%) | 172(14.58%) | 83(3.52%) | 0(0.00%) | | (READOUT_IF.Readout_block) | Readout_logic_top | 11(0.01%) | 10(0.01%) | 0(0.00%) | 1(0.01%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_ECR_debug_counter | cntr_generic | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_L1A_debug_counter | cntr_generic_7 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_RAW_busy | cntr_generic_8 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOB_LO_fifo_tidemark | tide_mark_block | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOB_busy | cntr_generic_9 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_TOBs_readout | TOBs_rdout | 6296(1.82%) | 6232(1.80%) | 0(0.00%) | 64(0.04%) | 15277(2.21%) | 112(9.49%) | 33(1.40%) | 0(0.00%) | | (U0_TOBs_readout) | TOBs_rdout | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 67(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_FIFO_BCN_L1A | FIFO_47b_512 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_11 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_11_synth | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 173(0.02%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_flag_fsm | busy_flag_fsm_99 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_TOB_SPY_mem | ipbus_dpram_100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3_101 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOB_sorting_gen.U1_TOBs_sorting | T_TOBs_sorting | 132(0.04%) | 123(0.04%) | 0(0.00%) | 9(0.01%) | 540(0.08%) | 6(0.51%) | 0(0.00%) | 0(0.00%) | | (U1_TOB_sorting_gen.U1_TOBs_sorting) | T_TOBs_sorting | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 217(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_eg | SIPO_TOPO_TOBs_unit | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 218(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_eg) | SIPO_TOPO_TOBs_unit | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 202(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOB_BCN_Delay | GeneralDelay | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO_124 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U3_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO_124 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b_125 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_T_TOB_DRP | DPR_209b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_209b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_209b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_209b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_209b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_209b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_209b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | DPR_209b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_209b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_209b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_209b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U5_T_TOBs_fifo | FIFO_209b_512 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_209b_512_fifo_generator_v13_2_11 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_209b_512_fifo_generator_v13_2_11_synth | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_209b_512_fifo_generator_top | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_209b_512_fifo_generator_ramfifo | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 71(0.01%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_209b_512_rd_logic | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_209b_512_dc_ss | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_209b_512_updn_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_209b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_209b_512_rd_status_flags_ss | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_209b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_209b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_209b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_209b_512_wr_logic | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_209b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_209b_512_wr_status_flags_ss | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_209b_512_wr_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_209b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_209b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_209b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_209b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_209b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_209b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_209b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_209b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_209b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_209b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_209b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_209b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_209b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_209b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_209b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U1_gen_sync_280 | gen_sync_280M_102 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOBs_eg_sorting | XTOBs_sorting__xdcDup__1 | 678(0.20%) | 653(0.19%) | 0(0.00%) | 25(0.01%) | 4712(0.68%) | 48(4.07%) | 16(0.68%) | 0(0.00%) | | (U2_XTOBs_eg_sorting) | XTOBs_sorting__xdcDup__1 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 1967(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit_114 | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 183(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_252b_512_HD3709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_252b_512_HD4067 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4068 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4069 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4070 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4071 | 86(0.02%) | 83(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4072 | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4072 | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4073 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4074 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4075 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_252b_512_rd_dc_as_HD4076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4077 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4077 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4078 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4079 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4081 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4082 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4085 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4085 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4088 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4089 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4090 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4091 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4092 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4093 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4097 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4098 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4099 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4100 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4100 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4101 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4102 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4102 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4103 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4105 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_252b_512_HD3722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_252b_512_HD4107 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4108 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4109 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4110 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4111 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4112 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4112 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4113 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4114 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4115 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4117 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4117 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4118 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4121 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4122 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4125 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4125 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4126 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4127 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4128 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4129 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4130 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4131 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4132 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4133 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4135 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4136 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4137 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4140 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4140 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4141 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4142 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4142 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4145 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4146 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_252b_512_HD3735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_252b_512_HD4147 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4148 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4149 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4150 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4151 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4152 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4152 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4153 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4154 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4155 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4157 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4157 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4158 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4159 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4161 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4162 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4165 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4165 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4167 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4168 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4169 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4170 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4171 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4172 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4173 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4174 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4175 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4176 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4177 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4178 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4179 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4180 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4180 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4181 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4182 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4182 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4183 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4185 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4186 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_117 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_252b_512_HD3748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_252b_512_HD4187 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4188 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4189 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4190 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4191 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4192 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4192 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4193 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4194 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4195 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4197 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4197 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4198 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4201 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4202 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4205 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4205 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4206 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4207 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4208 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4209 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4210 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4211 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4212 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4213 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4214 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4215 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4216 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4217 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4219 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4220 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4220 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4221 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4222 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4222 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_252b_512_HD3761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3763 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3764 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3765 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3766 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3767 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3769 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3770 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3771 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3773 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_252b_512_HD4227 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4228 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4229 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4230 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4231 | 96(0.03%) | 93(0.03%) | 0(0.00%) | 3(0.01%) | 181(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4232 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4232 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4233 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4234 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4235 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4237 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4237 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4238 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4239 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_252b_512_rd_handshaking_flags_HD4240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4241 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4242 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_252b_512_wr_pf_as_HD4243 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4245 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4245 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4248 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4249 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4250 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4251 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4252 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4253 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4257 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4258 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4259 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4260 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4260 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4261 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4262 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4262 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4263 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4265 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4266 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_252b_512_HD3774 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3775 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3776 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3777 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3779 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3780 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3781 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_252b_512_HD4267 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4268 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4269 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4270 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4271 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4272 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4272 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4273 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4274 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4275 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4277 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4277 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4278 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4281 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4282 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4285 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4285 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4286 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4287 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4288 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4289 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4290 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4291 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4292 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4293 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4294 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4295 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4297 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4298 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4299 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4300 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4300 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4301 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4302 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4302 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4303 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4304 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4305 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_252b_512_HD3787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3789 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3790 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3791 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3792 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3793 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3794 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3795 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3797 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3798 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3799 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_252b_512_HD4307 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4308 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4309 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4310 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4311 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4312 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4312 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4313 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4314 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4315 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4317 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4317 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4318 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4319 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4321 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4322 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4325 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4325 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4326 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4327 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4328 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4329 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4330 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4331 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4332 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4333 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4340 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4340 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4341 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4342 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4342 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4343 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4344 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4345 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4346 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 164(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_252b_512_HD3800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3801 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3802 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3803 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3804 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3805 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3807 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3808 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3809 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_252b_512_HD4347 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4348 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4349 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4350 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4351 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4352 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4352 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4353 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4354 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4355 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4357 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4357 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4358 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4359 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4361 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4362 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4365 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4365 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4367 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4368 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4369 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4370 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4371 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4372 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4373 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4374 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4375 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4377 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4378 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4379 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4380 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4380 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4381 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4382 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4382 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4383 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4384 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4385 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO_122 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO_122 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b_123 | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOBs_tau_sorting | XTOBs_sorting | 679(0.20%) | 650(0.19%) | 0(0.00%) | 29(0.02%) | 4939(0.71%) | 48(4.07%) | 16(0.68%) | 0(0.00%) | | (U3_XTOBs_tau_sorting) | XTOBs_sorting | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 1966(0.28%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U2_XTOBs_eg | SIPO_unit | 1(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 195(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U3_XTOB_DRP | DPR_252b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[0].U5_XTOBs_FIFO | FIFO_252b_512 | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11 | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo | 85(0.02%) | 82(0.02%) | 0(0.00%) | 3(0.01%) | 179(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs | 47(0.01%) | 47(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs | 23(0.01%) | 23(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 29(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_252b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U2_XTOBs_eg | SIPO_unit_107 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U3_XTOB_DRP | DPR_252b_512_HD3631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[1].U5_XTOBs_FIFO | FIFO_252b_512_HD3827 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD3828 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD3829 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3830 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3831 | 76(0.02%) | 73(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3832 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3832 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3833 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3834 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3835 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3837 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3837 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3838 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3841 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3842 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3845 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3845 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3846 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3847 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3848 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3849 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD3850 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD3851 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3852 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3853 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3855 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3857 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3860 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3860 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3861 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3862 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3862 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD3863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD3864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD3865 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD3866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U2_XTOBs_eg | SIPO_unit_108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U3_XTOB_DRP | DPR_252b_512_HD3644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[2].U5_XTOBs_FIFO | FIFO_252b_512_HD3867 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD3868 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD3869 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3870 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3871 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3872 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3872 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3873 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3874 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3875 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3877 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3877 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3878 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3879 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3881 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3882 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3885 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3885 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3887 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3888 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3889 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD3890 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD3891 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3892 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3893 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3900 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3900 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3901 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3902 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3902 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD3903 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD3904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD3905 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD3906 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U2_XTOBs_eg | SIPO_unit_109 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U3_XTOB_DRP | DPR_252b_512_HD3657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[3].U5_XTOBs_FIFO | FIFO_252b_512_HD3907 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD3908 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD3909 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3910 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3911 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3912 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3912 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3913 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3914 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3915 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3917 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3917 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3918 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3921 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3922 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3925 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3925 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3927 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3928 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3929 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD3930 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD3931 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3932 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3933 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3934 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3935 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3937 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3939 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3940 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3940 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3941 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3942 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3942 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD3943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD3944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD3945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD3946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U2_XTOBs_eg | SIPO_unit_110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U3_XTOB_DRP | DPR_252b_512_HD3670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[4].U5_XTOBs_FIFO | FIFO_252b_512_HD3947 | 97(0.03%) | 94(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD3948 | 97(0.03%) | 94(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD3949 | 97(0.03%) | 94(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3950 | 97(0.03%) | 94(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3951 | 97(0.03%) | 94(0.03%) | 0(0.00%) | 3(0.01%) | 180(0.03%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3952 | 45(0.01%) | 45(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3952 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3953 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3954 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3955 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3957 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3957 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3958 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3959 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD3961 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD3962 | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_252b_512_wr_pf_as_HD3963 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD3965 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD3965 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD3966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD3967 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD3968 | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD3969 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD3970 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD3971 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD3972 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD3973 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD3974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD3975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD3976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3977 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD3978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3980 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD3980 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3981 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD3982 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD3982 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD3983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD3984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD3985 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD3986 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U2_XTOBs_eg | SIPO_unit_111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U3_XTOB_DRP | DPR_252b_512_HD3683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[5].U5_XTOBs_FIFO | FIFO_252b_512_HD3987 | 78(0.02%) | 75(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD3988 | 78(0.02%) | 75(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD3989 | 78(0.02%) | 75(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD3990 | 78(0.02%) | 75(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD3991 | 78(0.02%) | 75(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD3992 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD3992 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD3993 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD3994 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD3995 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD3997 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD3997 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD3998 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD3999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4001 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4002 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4005 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4005 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4007 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4008 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4009 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4010 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4011 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4012 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4013 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4014 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4015 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4017 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4018 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4019 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4020 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4020 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4021 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4022 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4022 | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4023 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4025 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U2_XTOBs_eg | SIPO_unit_112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U3_XTOB_DRP | DPR_252b_512_HD3696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9_HD3697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth_HD3698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top_HD3699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr_HD3700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width_HD3701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper_HD3702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0_HD3703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD3704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1_HD3705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD3706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2_HD3707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD3708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[6].U5_XTOBs_FIFO | FIFO_252b_512_HD4027 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11_HD4028 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth_HD4029 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top_HD4030 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo_HD4031 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs_HD4032 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs_HD4032 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray_HD4033 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2_HD4034 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic_HD4035 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as_HD4037 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as_HD4037 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1_HD4038 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2_HD4039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr_HD4041 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic_HD4042 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as_HD4045 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as_HD4045 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_HD4046 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0_HD4047 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr_HD4048 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory_HD4049 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9_HD4050 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth_HD4051 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top_HD4052 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr_HD4053 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width_HD4054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper_HD4055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0_HD4056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0_HD4057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1_HD4058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1_HD4059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4060 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2_HD4060 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2_HD4061 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo_HD4062 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo_HD4062 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single_HD4063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2_HD4064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst_HD4065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2_HD4066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U2_XTOBs_eg | SIPO_unit_113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 194(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U3_XTOB_DRP | DPR_252b_512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | DPR_252b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | DPR_252b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_252b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | DPR_252b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | DPR_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | DPR_252b_512_blk_mem_gen_prim_width__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_XTOB_RAM[7].U5_XTOBs_FIFO | FIFO_252b_512 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_252b_512_fifo_generator_v13_2_11 | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_252b_512_fifo_generator_v13_2_11_synth | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_252b_512_fifo_generator_top | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_252b_512_fifo_generator_ramfifo | 75(0.02%) | 72(0.02%) | 0(0.00%) | 3(0.01%) | 170(0.02%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_252b_512_clk_x_pntrs | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_252b_512_clk_x_pntrs | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_252b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_252b_512_rd_logic | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_252b_512_rd_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_252b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_252b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_252b_512_wr_logic | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_252b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_252b_512_wr_status_flags_as | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_252b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_252b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_252b_512_wr_bin_cntr | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_252b_512_memory | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_252b_512_blk_mem_gen_v8_4_9 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_252b_512_blk_mem_gen_v8_4_9_synth | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_252b_512_blk_mem_gen_top | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_252b_512_blk_mem_gen_generic_cstr | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 3(0.25%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_252b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized0 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 7(0.01%) | 4(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | (ramloop[3].ram.r) | FIFO_252b_512_blk_mem_gen_prim_width__parameterized2 | 5(0.01%) | 2(0.01%) | 0(0.00%) | 3(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_252b_512_blk_mem_gen_prim_wrapper__parameterized2 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_252b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_252b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_252b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_252b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.gic_rst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gsckt_wrst.xpm_cdc_sync_rst_inst_wrst | FIFO_252b_512_xpm_cdc_sync_rst__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_TOBs_wr_FSM | fsm_TOB_wr_to_FIFO | 19(0.01%) | 19(0.01%) | 0(0.00%) | 0(0.00%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U1_TOBs_wr_FSM) | fsm_TOB_wr_to_FIFO | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_9b | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_BCN_Delay | GeneralDelay__parameterized0 | 4(0.01%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_rd_mux_fsm | fsm_TOBs_to_muxPISO | 4480(1.29%) | 4480(1.29%) | 0(0.00%) | 0(0.00%) | 4445(0.64%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U6_rd_mux_fsm) | fsm_TOBs_to_muxPISO | 4456(1.29%) | 4456(1.29%) | 0(0.00%) | 0(0.00%) | 4416(0.64%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_TOB_payld_length | cntr_generic__parameterized2_105 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_T_TOB_cntr | cntr_generic__parameterized0 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_eg_cntr | cntr_generic__parameterized1 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_XTOB_tau_cntr | cntr_generic__parameterized1_106 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO | FIFO_33b_8192 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_11 | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_11_synth | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo | 150(0.04%) | 150(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic | 59(0.02%) | 59(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_33b_8192_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as | 17(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_9 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_9_synth | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_TOB_Link_output_FIFO_FSM | FIFO_to_MGT_TOB_FSM | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 140(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_clk_closs_pulse | clk_closs_pulse_fsm_103 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_frame_counter | cntr_up_dn_generic_104 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_raw_duration_counter | cntr_generic_10 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_busy_tob_duration_counter | cntr_generic_11 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_real_time_40m_counter | cntr_generic_12 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_tob_bcn_tidemark | tide_mark_block_13 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U0_xtob_data_tidemark | tide_mark_block_14 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_bcn_l1a_valid_checker | bcn_l1a_valid_checker | 129(0.04%) | 129(0.04%) | 0(0.00%) | 0(0.00%) | 350(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U17_bcn_l1a_valid_checker) | bcn_l1a_valid_checker | 89(0.03%) | 89(0.03%) | 0(0.00%) | 0(0.00%) | 222(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_mismatch_cntr_block | cntr_generic__parameterized4 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bcn_parity_err_cntr_block | cntr_generic__parameterized4_96 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_mismatch_cntr_block | cntr_generic__parameterized4_97 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | l1id_parity_err_cntr_block | cntr_generic__parameterized4_98 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_LO_fifo_tidemark | tide_mark_block_15 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_bcn_tidemark | tide_mark_block_16 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_data_tidemark | tide_mark_block_17 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_readout | RAW_data_rdout | 8274(2.39%) | 8272(2.39%) | 0(0.00%) | 2(0.01%) | 34490(4.98%) | 60(5.08%) | 50(2.12%) | 0(0.00%) | | (U1_RAW_readout) | RAW_data_rdout | 74(0.02%) | 73(0.02%) | 0(0.00%) | 1(0.01%) | 15100(2.18%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U1_gen_sync_280 | gen_sync_280M | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U2_PISO_RAW | PISO_RAW_data | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U3_DPRAM_RAW_Data | DPR_36b_1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[0].U4_FIFO_RAW_Data | FIFO_36b_512 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[10].U2_PISO_RAW | PISO_RAW_data_48 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4434 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4435 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4437 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4438 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4439 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4440 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[10].U4_FIFO_RAW_Data | FIFO_36b_512_HD4810 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4811 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4812 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4813 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4814 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4815 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4819 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4819 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4820 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4821 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4822 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4823 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4824 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4825 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4825 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4826 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4827 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4828 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4829 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4830 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4831 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD4832 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4833 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4835 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4836 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[11].U2_PISO_RAW | PISO_RAW_data_49 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4441 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4443 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4444 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4445 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[11].U4_FIFO_RAW_Data | FIFO_36b_512_HD4838 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4839 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4840 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4841 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4842 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4843 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4847 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4847 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4848 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4849 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4850 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4851 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4852 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4853 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4853 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4854 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4855 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4856 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4857 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4858 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4859 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD4860 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4861 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4863 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4864 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[12].U2_PISO_RAW | PISO_RAW_data_50 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4453 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4454 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[12].U4_FIFO_RAW_Data | FIFO_36b_512_HD4866 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4867 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4868 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4869 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4870 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4871 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4875 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4875 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4876 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4877 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4878 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4879 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4880 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4881 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4881 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4882 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4883 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4884 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4885 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4886 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4887 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD4888 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4889 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4891 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4892 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[13].U2_PISO_RAW | PISO_RAW_data_51 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4455 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4456 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4457 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4458 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4459 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4461 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[13].U4_FIFO_RAW_Data | FIFO_36b_512_HD4894 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4895 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4896 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4897 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4898 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4899 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4903 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4903 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4904 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4905 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4906 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4907 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4908 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4909 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4909 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4910 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4911 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4912 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4913 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4914 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4915 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD4916 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4917 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4919 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4920 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[14].U2_PISO_RAW | PISO_RAW_data_52 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4462 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4463 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4465 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4466 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4467 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4468 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[14].U4_FIFO_RAW_Data | FIFO_36b_512_HD4922 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4923 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4924 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4925 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4926 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4927 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4931 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4931 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4932 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4933 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4934 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4935 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4936 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4937 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4937 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4938 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4939 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4940 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4941 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4942 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4943 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD4944 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4945 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4947 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4948 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[15].U2_PISO_RAW | PISO_RAW_data_53 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4469 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4471 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4472 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4473 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[15].U4_FIFO_RAW_Data | FIFO_36b_512_HD4950 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4951 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4952 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4953 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4954 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4955 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4959 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4959 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4960 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4961 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4962 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4963 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4964 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4965 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4965 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4966 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4967 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4968 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4969 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4970 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4971 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD4972 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD4973 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD4974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD4975 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD4976 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[16].U2_PISO_RAW | PISO_RAW_data_54 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4481 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4482 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[16].U4_FIFO_RAW_Data | FIFO_36b_512_HD4978 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD4979 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD4980 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD4981 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD4982 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD4983 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD4984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD4987 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD4987 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD4988 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD4989 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD4990 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD4991 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD4992 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD4993 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD4993 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD4994 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD4995 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD4996 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD4997 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD4998 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD4999 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5000 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5001 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5003 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5004 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[17].U2_PISO_RAW | PISO_RAW_data_55 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4483 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4484 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4485 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4486 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4487 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4489 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[17].U4_FIFO_RAW_Data | FIFO_36b_512_HD5006 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5007 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5008 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5009 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5010 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5011 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5015 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5015 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5016 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5017 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5018 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5019 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5020 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5021 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5021 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5022 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5023 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5024 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5025 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5026 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5027 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5028 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5029 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5031 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5032 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[18].U2_PISO_RAW | PISO_RAW_data_56 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4490 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4491 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4493 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4494 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4495 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4496 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[18].U4_FIFO_RAW_Data | FIFO_36b_512_HD5034 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5035 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5036 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5037 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5038 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5039 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5043 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5043 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5044 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5045 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5046 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5047 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5048 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5049 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5049 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5050 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5051 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5052 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5053 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5054 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5055 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5056 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5057 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5059 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5060 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[19].U2_PISO_RAW | PISO_RAW_data_57 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4497 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4499 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4500 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4501 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[19].U4_FIFO_RAW_Data | FIFO_36b_512_HD5062 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5063 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5064 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5065 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5066 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5067 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5071 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5071 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5072 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5073 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5074 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5075 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5076 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5077 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5077 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5078 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5079 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5080 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5081 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5082 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5083 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5084 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5085 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5087 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5088 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[1].U2_PISO_RAW | PISO_RAW_data_58 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4509 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4510 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[1].U4_FIFO_RAW_Data | FIFO_36b_512_HD5090 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5091 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5092 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5093 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5094 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5095 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5099 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5099 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5100 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5101 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5102 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5103 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5104 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5105 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5105 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5106 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5107 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5108 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5109 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5110 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5111 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5112 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5113 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5115 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5116 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[20].U2_PISO_RAW | PISO_RAW_data_59 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4511 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4512 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4513 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4514 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4515 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4517 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[20].U4_FIFO_RAW_Data | FIFO_36b_512_HD5118 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5119 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5120 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5121 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5122 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5123 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5125 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5126 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5127 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5127 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5128 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5129 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5130 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5131 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5132 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5133 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5133 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5134 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5135 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5136 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5137 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5138 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5139 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5140 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5141 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5142 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5143 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5144 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[21].U2_PISO_RAW | PISO_RAW_data_60 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4518 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4519 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4521 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4522 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4523 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4524 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[21].U4_FIFO_RAW_Data | FIFO_36b_512_HD5146 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5147 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5148 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5149 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5150 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5151 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5152 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5155 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5155 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5156 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5157 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5158 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5159 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5160 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5161 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5161 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5162 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5163 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5164 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5165 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5166 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5167 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5168 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5169 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5170 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5171 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5172 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[22].U2_PISO_RAW | PISO_RAW_data_61 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4525 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4527 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4528 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4529 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[22].U4_FIFO_RAW_Data | FIFO_36b_512_HD5174 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5175 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5176 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5177 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5178 | 81(0.02%) | 81(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5179 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5180 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.gdc.dc | FIFO_36b_512_dc_ss_HD5181 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gsym_dc.dc | FIFO_36b_512_updn_cntr_HD5182 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5183 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5183 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5184 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5185 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5186 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5187 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5188 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5189 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5189 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5190 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5191 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5192 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5193 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5194 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5195 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5196 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5197 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5198 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5199 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5200 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[23].U2_PISO_RAW | PISO_RAW_data_62 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4537 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4538 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[23].U4_FIFO_RAW_Data | FIFO_36b_512_HD5202 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5203 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5204 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5205 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5206 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5207 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5208 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5211 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5211 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5212 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5213 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5214 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5215 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5216 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5217 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5217 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5218 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5219 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5220 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5221 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5222 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5223 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5224 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5225 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5226 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5227 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5228 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[24].U2_PISO_RAW | PISO_RAW_data_63 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4539 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4540 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4541 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4542 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4543 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4545 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[24].U4_FIFO_RAW_Data | FIFO_36b_512_HD5230 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5231 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5232 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5233 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5234 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5235 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5236 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5239 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5239 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5240 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5241 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5242 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5243 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5244 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5245 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5245 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5246 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5247 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5248 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5249 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5250 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5251 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5252 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5253 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5254 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5255 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5256 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[25].U2_PISO_RAW | PISO_RAW_data_64 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4546 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4547 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4549 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4550 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4551 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4552 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[25].U4_FIFO_RAW_Data | FIFO_36b_512_HD5258 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5259 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5260 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5261 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5262 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5263 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5264 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5267 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5267 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5268 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5269 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5270 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5271 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5272 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5273 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5273 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5274 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5275 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5276 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5277 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5278 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5279 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5280 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5281 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5282 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5283 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5284 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[26].U2_PISO_RAW | PISO_RAW_data_65 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4553 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4555 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4556 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4557 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[26].U4_FIFO_RAW_Data | FIFO_36b_512_HD5286 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5287 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5288 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5289 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5290 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5291 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5292 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5295 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5295 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5296 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5297 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5298 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5299 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5300 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5301 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5301 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5302 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5303 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5304 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5305 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5306 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5307 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5308 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5309 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5310 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5311 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5312 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[27].U2_PISO_RAW | PISO_RAW_data_66 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4565 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4566 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[27].U4_FIFO_RAW_Data | FIFO_36b_512_HD5314 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5315 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5316 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5317 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5318 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5319 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5320 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5323 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5323 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5324 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5325 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5326 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5327 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5328 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5329 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5329 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5330 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5331 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5332 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5333 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5334 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5335 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5336 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5337 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5338 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5339 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5340 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[28].U2_PISO_RAW | PISO_RAW_data_67 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4567 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4568 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4569 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4570 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4571 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4573 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[28].U4_FIFO_RAW_Data | FIFO_36b_512_HD5342 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5343 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5344 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5345 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5346 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5347 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5348 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5351 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5351 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5352 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5353 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5354 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5355 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5356 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5357 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5357 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5358 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5359 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5360 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5361 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5362 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5363 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5364 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5365 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5366 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5367 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5368 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[29].U2_PISO_RAW | PISO_RAW_data_68 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4574 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4575 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4577 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4578 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4579 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4580 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[29].U4_FIFO_RAW_Data | FIFO_36b_512_HD5370 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5371 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5372 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5373 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5374 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5375 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5376 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5379 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5379 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5380 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5381 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5382 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5383 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5384 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5385 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5385 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5386 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5387 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5388 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5389 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5390 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5391 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5392 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5393 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5394 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5395 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5396 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[2].U2_PISO_RAW | PISO_RAW_data_69 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4581 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4583 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4584 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4585 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[2].U4_FIFO_RAW_Data | FIFO_36b_512_HD5398 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5399 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5400 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5401 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5402 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5403 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5404 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5407 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5407 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5408 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5409 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5410 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5411 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5412 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5413 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5413 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5414 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5415 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5416 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5417 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5418 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5419 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5420 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5421 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5422 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5423 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5424 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[30].U2_PISO_RAW | PISO_RAW_data_70 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4593 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4594 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[30].U4_FIFO_RAW_Data | FIFO_36b_512_HD5426 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5427 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5428 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5429 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5430 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5431 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5432 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5435 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5435 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5436 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5437 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5438 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5439 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5440 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5441 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5441 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5442 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5443 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5444 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5445 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5446 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5447 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5448 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5449 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5450 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5451 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5452 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[31].U2_PISO_RAW | PISO_RAW_data_71 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4595 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4596 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4597 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4598 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4599 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4601 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[31].U4_FIFO_RAW_Data | FIFO_36b_512_HD5454 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5455 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5456 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5457 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5458 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5459 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5460 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5463 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5463 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5464 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5465 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5466 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5467 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5468 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5469 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5469 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5470 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5471 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5472 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5473 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5474 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5475 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5476 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5477 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5478 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5479 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5480 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[32].U2_PISO_RAW | PISO_RAW_data_72 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4602 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4603 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4605 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4606 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4607 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4608 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[32].U4_FIFO_RAW_Data | FIFO_36b_512_HD5482 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5483 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5484 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5485 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5486 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5487 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5488 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5491 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5491 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5492 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5493 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5494 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5495 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5496 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5497 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5497 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5498 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5499 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5500 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5501 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5502 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5503 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5504 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5505 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5506 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5507 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5508 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[33].U2_PISO_RAW | PISO_RAW_data_73 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4609 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4611 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4612 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4613 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[33].U4_FIFO_RAW_Data | FIFO_36b_512_HD5510 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5511 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5512 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5513 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5514 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5515 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5516 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5519 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5519 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5520 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5521 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5522 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5523 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5524 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5525 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5525 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5526 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5527 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5528 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5529 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5530 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5531 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5532 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5533 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5534 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5535 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5536 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[34].U2_PISO_RAW | PISO_RAW_data_74 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4621 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4622 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[34].U4_FIFO_RAW_Data | FIFO_36b_512_HD5538 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5539 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5540 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5541 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5542 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5543 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5544 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5547 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5547 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5548 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5549 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5550 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5551 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5552 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5553 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5553 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5554 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5555 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5556 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5557 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5558 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5559 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5560 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5561 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5562 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5563 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5564 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[35].U2_PISO_RAW | PISO_RAW_data_75 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4623 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4624 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4625 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4626 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4627 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4629 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[35].U4_FIFO_RAW_Data | FIFO_36b_512_HD5566 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5567 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5568 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5569 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5570 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5571 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5572 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5575 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5575 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5576 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5577 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5578 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5579 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5580 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5581 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5581 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5582 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5583 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5584 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5585 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5586 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5587 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5588 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5589 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5590 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5591 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5592 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[36].U2_PISO_RAW | PISO_RAW_data_76 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4630 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4631 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4633 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4634 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4635 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4636 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[36].U4_FIFO_RAW_Data | FIFO_36b_512_HD5594 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5595 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5596 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5597 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5598 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5599 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5600 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5603 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5603 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5604 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5605 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5606 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5607 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5608 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5609 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5609 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5610 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5611 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5612 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5613 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5614 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5615 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5616 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5617 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5618 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5619 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5620 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[37].U2_PISO_RAW | PISO_RAW_data_77 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4637 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4639 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4640 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4641 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[37].U4_FIFO_RAW_Data | FIFO_36b_512_HD5622 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5623 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5624 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5625 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5626 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5627 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5628 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5631 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5631 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5632 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5633 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5634 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5635 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5636 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5637 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5637 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5638 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5639 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5640 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5641 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5642 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5643 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[38].U2_PISO_RAW | PISO_RAW_data_78 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4644 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4645 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4646 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4647 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4648 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4649 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4650 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[38].U4_FIFO_RAW_Data | FIFO_36b_512_HD5650 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5651 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5652 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5653 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5654 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5655 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5659 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5659 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5661 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5662 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5663 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5664 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5665 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5665 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5667 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5668 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5669 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[39].U2_PISO_RAW | PISO_RAW_data_79 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4651 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4652 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4653 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4654 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4655 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4656 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4657 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[39].U4_FIFO_RAW_Data | FIFO_36b_512_HD5678 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5679 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5680 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5681 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5682 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5683 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5687 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5687 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5689 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5690 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5691 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5692 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5693 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5693 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5695 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5696 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5697 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[3].U2_PISO_RAW | PISO_RAW_data_80 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4658 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4659 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4660 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4661 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4662 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4663 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4664 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[3].U4_FIFO_RAW_Data | FIFO_36b_512_HD5706 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5707 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5708 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5709 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5710 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5711 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5715 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5715 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5717 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5718 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5719 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5720 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5721 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5721 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5723 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5724 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5725 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[40].U2_PISO_RAW | PISO_RAW_data_81 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4665 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4666 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4667 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4668 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4669 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4670 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4671 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[40].U4_FIFO_RAW_Data | FIFO_36b_512_HD5734 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5735 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5736 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5737 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5738 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5739 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5743 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5743 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5745 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5746 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5747 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5748 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5749 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5749 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5751 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5752 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5753 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[41].U2_PISO_RAW | PISO_RAW_data_82 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4672 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4673 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4674 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4675 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4676 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4677 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4678 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[41].U4_FIFO_RAW_Data | FIFO_36b_512_HD5762 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5763 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5764 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5765 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5766 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5767 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5768 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5771 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5771 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5772 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5773 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5774 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5775 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5776 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5777 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5777 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5778 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5779 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5780 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5781 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5782 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5783 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5784 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5785 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5786 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5787 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5788 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[42].U2_PISO_RAW | PISO_RAW_data_83 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4679 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4680 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4681 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4682 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4683 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4684 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4685 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[42].U4_FIFO_RAW_Data | FIFO_36b_512_HD5790 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5791 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5792 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5793 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5794 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5795 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5796 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5799 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5799 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5800 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5801 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5802 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5803 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5804 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5805 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5805 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5806 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5807 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5808 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5809 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5810 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5811 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5812 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5813 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5814 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5815 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5816 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[43].U2_PISO_RAW | PISO_RAW_data_84 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4686 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4687 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4688 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4689 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4690 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4691 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4692 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[43].U4_FIFO_RAW_Data | FIFO_36b_512_HD5818 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5819 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5820 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5821 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5822 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5823 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5824 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5827 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5827 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5828 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5829 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5830 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5831 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5832 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5833 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5833 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5834 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5835 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5836 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5837 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5838 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5839 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5840 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5841 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5842 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5843 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5844 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[44].U2_PISO_RAW | PISO_RAW_data_85 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4693 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4694 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4695 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4696 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4697 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4698 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4699 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[44].U4_FIFO_RAW_Data | FIFO_36b_512_HD5846 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5847 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5848 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5849 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5850 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5851 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5852 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5855 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5855 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5856 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5857 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5858 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5859 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5860 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5861 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5861 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5862 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5863 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5864 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5865 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5866 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5867 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5868 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5869 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5870 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5871 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5872 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[45].U2_PISO_RAW | PISO_RAW_data_86 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4700 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4701 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4702 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4703 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4704 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4705 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4706 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[45].U4_FIFO_RAW_Data | FIFO_36b_512_HD5874 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5875 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5876 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5877 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5878 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5879 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5880 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5883 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5883 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5884 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5885 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5886 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5887 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5888 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5889 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5889 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5890 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5891 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5892 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5893 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5894 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5895 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5896 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5897 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5898 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5899 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5900 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[46].U2_PISO_RAW | PISO_RAW_data_87 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4707 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4708 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4709 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4710 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4711 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4712 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4713 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[46].U4_FIFO_RAW_Data | FIFO_36b_512_HD5902 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5903 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5904 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5905 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5906 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5907 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5908 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5911 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5911 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5912 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5913 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5914 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5915 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5916 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5917 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5917 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5918 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5919 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5920 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5921 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5922 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5923 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5924 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5925 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5926 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5927 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5928 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[47].U2_PISO_RAW | PISO_RAW_data_88 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4714 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4715 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4716 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4717 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4718 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4719 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4720 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[47].U4_FIFO_RAW_Data | FIFO_36b_512_HD5930 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5931 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5932 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5933 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5934 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5935 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5936 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5939 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5939 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5940 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5941 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5942 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5943 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5944 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5945 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5945 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5946 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5947 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5948 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5949 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5950 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5951 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5952 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5953 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5954 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5955 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5956 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[48].U2_PISO_RAW | PISO_RAW_data_89 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U3_DPRAM_RAW_Data | DPR_36b_1024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[48].U4_FIFO_RAW_Data | FIFO_36b_512 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[4].U2_PISO_RAW | PISO_RAW_data_90 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4721 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4722 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4723 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4724 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4725 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4726 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4727 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[4].U4_FIFO_RAW_Data | FIFO_36b_512_HD5958 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5959 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5960 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5961 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5962 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5963 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5964 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5967 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5967 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5968 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5969 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5970 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5971 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD5972 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD5973 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD5973 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD5974 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD5975 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD5976 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD5977 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD5978 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD5979 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD5980 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD5981 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD5982 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD5983 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD5984 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[5].U2_PISO_RAW | PISO_RAW_data_91 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4728 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4729 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4730 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4731 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4732 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4733 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4734 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[5].U4_FIFO_RAW_Data | FIFO_36b_512_HD5986 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD5987 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD5988 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD5989 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD5990 | 71(0.02%) | 71(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD5991 | 38(0.01%) | 38(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD5992 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD5995 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD5995 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD5996 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD5997 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD5998 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD5999 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6000 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6001 | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6001 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6002 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6003 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6004 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6005 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6006 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD6007 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD6008 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6009 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6010 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6011 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6012 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[6].U2_PISO_RAW | PISO_RAW_data_92 | 69(0.02%) | 69(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4735 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4736 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4737 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4738 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4739 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4740 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4741 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[6].U4_FIFO_RAW_Data | FIFO_36b_512_HD6014 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD6015 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD6016 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6017 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6018 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6019 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6020 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6023 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6023 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6024 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6025 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6026 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6027 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6028 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6029 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6029 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6030 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6031 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6032 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6033 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6034 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD6035 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD6036 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6037 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6038 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6039 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6040 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[7].U2_PISO_RAW | PISO_RAW_data_93 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4742 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4743 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4744 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4745 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4746 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4747 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4748 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[7].U4_FIFO_RAW_Data | FIFO_36b_512_HD6042 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD6043 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD6044 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6045 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6046 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6047 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6048 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6051 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6051 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6052 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6053 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6054 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6055 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6056 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6057 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6057 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6058 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6059 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6060 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6061 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6062 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD6063 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD6064 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6065 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6066 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6067 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6068 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[8].U2_PISO_RAW | PISO_RAW_data_94 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4749 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4750 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4751 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4752 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4753 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4754 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4755 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[8].U4_FIFO_RAW_Data | FIFO_36b_512_HD6070 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD6071 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD6072 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6073 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6074 | 73(0.02%) | 73(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6075 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6076 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6079 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6079 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6080 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6081 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6082 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6083 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6084 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6085 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6085 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6086 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6087 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6088 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6089 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6090 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD6091 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD6092 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6093 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6094 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6095 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6096 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | GEN_CHANNEL[9].U2_PISO_RAW | PISO_RAW_data_95 | 70(0.02%) | 70(0.02%) | 0(0.00%) | 0(0.00%) | 276(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U3_DPRAM_RAW_Data | DPR_36b_1024_HD4756 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | DPR_36b_1024_blk_mem_gen_v8_4_9_HD4757 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | DPR_36b_1024_blk_mem_gen_v8_4_9_synth_HD4758 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | DPR_36b_1024_blk_mem_gen_top_HD4759 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | DPR_36b_1024_blk_mem_gen_generic_cstr_HD4760 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | DPR_36b_1024_blk_mem_gen_prim_width_HD4761 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | DPR_36b_1024_blk_mem_gen_prim_wrapper_HD4762 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | GEN_CHANNEL[9].U4_FIFO_RAW_Data | FIFO_36b_512_HD6098 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_36b_512_fifo_generator_v13_2_11_HD6099 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_36b_512_fifo_generator_v13_2_11_synth_HD6100 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_36b_512_fifo_generator_top_HD6101 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_36b_512_fifo_generator_ramfifo_HD6102 | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 63(0.01%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_36b_512_rd_logic_HD6103 | 39(0.01%) | 39(0.01%) | 0(0.00%) | 0(0.00%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_36b_512_rd_handshaking_flags_HD6104 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grss.rsts | FIFO_36b_512_rd_status_flags_ss_HD6107 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (grss.rsts) | FIFO_36b_512_rd_status_flags_ss_HD6107 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_2_HD6108 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_36b_512_compare_3_HD6109 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_36b_512_rd_bin_cntr_HD6110 | 35(0.01%) | 35(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_36b_512_wr_logic_HD6111 | 34(0.01%) | 34(0.01%) | 0(0.00%) | 0(0.00%) | 42(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.gpf.wrpf | FIFO_36b_512_wr_pf_ss_HD6112 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwss.wsts | FIFO_36b_512_wr_status_flags_ss_HD6113 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwss.wsts) | FIFO_36b_512_wr_status_flags_ss_HD6113 | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_36b_512_compare_HD6114 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_36b_512_compare_0_HD6115 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gaf.c2 | FIFO_36b_512_compare_1_HD6116 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_36b_512_wr_bin_cntr_HD6117 | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_36b_512_memory_HD6118 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_36b_512_blk_mem_gen_v8_4_9_HD6119 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_36b_512_blk_mem_gen_v8_4_9_synth_HD6120 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_36b_512_blk_mem_gen_top_HD6121 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_36b_512_blk_mem_gen_generic_cstr_HD6122 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_36b_512_blk_mem_gen_prim_width_HD6123 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_36b_512_blk_mem_gen_prim_wrapper_HD6124 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | U10_RAW_frame_counter | cntr_up_dn_generic | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U10_clk_closs_pulse | clk_closs_pulse_fsm | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_RAW_SPY_mem | ipbus_dpram | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | U13_spy_mem_wr_addr | cntr_generic__parameterized3 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_busy_flag_fsm | busy_flag_fsm | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_FIFO_link_err | FIFO_54b_512 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_54b_512_fifo_generator_v13_2_11 | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_54b_512_fifo_generator_v13_2_11_synth | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_54b_512_fifo_generator_top | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbi.bi | FIFO_54b_512_fifo_generator_v13_2_11_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | g7ser_birst.rstbt | FIFO_54b_512_reset_builtin | 3(0.01%) | 2(0.01%) | 0(0.00%) | 1(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | v7_bi_fifo.fblk | FIFO_54b_512_builtin_top_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gextw[1].gnll_fifo.inst_extd | FIFO_54b_512_builtin_extdepth_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gonep.inst_prim | FIFO_54b_512_builtin_prim_v6 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U5_RAW_fsm | fsm_RAW_data_wr_to_DPR | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U5_RAW_fsm) | fsm_RAW_data_wr_to_DPR | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_rd_addr | cntr_ram_addr_10b | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_link_err | link_errors_ORed | 126(0.04%) | 126(0.04%) | 0(0.00%) | 0(0.00%) | 54(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5b_gen_full_flag | RAW_fifo_full_flag_gen | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_FIFO_BCN_L1A | FIFO_47b_512 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | U0 | FIFO_47b_512_fifo_generator_v13_2_11 | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_fifo_gen | FIFO_47b_512_fifo_generator_v13_2_11_synth | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gconvfifo.rf | FIFO_47b_512_fifo_generator_top | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | grf.rf | FIFO_47b_512_fifo_generator_ramfifo | 99(0.03%) | 99(0.03%) | 0(0.00%) | 0(0.00%) | 174(0.03%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_47b_512_clk_x_pntrs | 55(0.02%) | 55(0.02%) | 0(0.00%) | 0(0.00%) | 72(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_47b_512_clk_x_pntrs | 31(0.01%) | 31(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_47b_512_xpm_cdc_gray__2 | 12(0.01%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_47b_512_rd_logic | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_47b_512_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_47b_512_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_47b_512_compare_1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | grhf.rhf | FIFO_47b_512_rd_handshaking_flags | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_47b_512_rd_bin_cntr | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_47b_512_wr_logic | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_47b_512_wr_pf_as | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_47b_512_wr_status_flags_as | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_47b_512_compare | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_47b_512_compare_0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_47b_512_wr_bin_cntr | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 36(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_47b_512_memory | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_47b_512_blk_mem_gen_v8_4_9 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_47b_512_blk_mem_gen_v8_4_9_synth | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_47b_512_blk_mem_gen_top | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | valid.cstr | FIFO_47b_512_blk_mem_gen_generic_cstr | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_47b_512_blk_mem_gen_prim_width | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_47b_512_blk_mem_gen_prim_wrapper | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (rstblk) | FIFO_47b_512_reset_blk_ramfifo | 8(0.01%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | FIFO_47b_512_xpm_cdc_single | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | FIFO_47b_512_xpm_cdc_single__2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | FIFO_47b_512_xpm_cdc_async_rst__1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_rd_RAW_mux_fsm | fsm_RAW_to_muxPISO | 808(0.23%) | 808(0.23%) | 0(0.00%) | 0(0.00%) | 2086(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U7_rd_RAW_mux_fsm) | fsm_RAW_to_muxPISO | 782(0.23%) | 782(0.23%) | 0(0.00%) | 0(0.00%) | 2074(0.30%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_raw_payld_length | cntr_generic__parameterized2 | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_RAW_Link_output_FIFO | FIFO_33b_8192 | 148(0.04%) | 148(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | U0 | FIFO_33b_8192_fifo_generator_v13_2_11 | 148(0.04%) | 148(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_fifo_gen | FIFO_33b_8192_fifo_generator_v13_2_11_synth | 148(0.04%) | 148(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gconvfifo.rf | FIFO_33b_8192_fifo_generator_top | 148(0.04%) | 148(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | grf.rf | FIFO_33b_8192_fifo_generator_ramfifo | 148(0.04%) | 148(0.04%) | 0(0.00%) | 0(0.00%) | 226(0.03%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gntv_or_sync_fifo.gcx.clkx | FIFO_33b_8192_clk_x_pntrs | 61(0.02%) | 61(0.02%) | 0(0.00%) | 0(0.00%) | 104(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gntv_or_sync_fifo.gcx.clkx) | FIFO_33b_8192_clk_x_pntrs | 25(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rd_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wr_pntr_cdc_inst | FIFO_33b_8192_xpm_cdc_gray__2 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.rd | FIFO_33b_8192_rd_logic | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.grdc1.rdc | FIFO_33b_8192_rd_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gras.rsts | FIFO_33b_8192_rd_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gras.rsts) | FIFO_33b_8192_rd_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c0 | FIFO_33b_8192_compare_2 | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare_3 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rpntr | FIFO_33b_8192_rd_bin_cntr | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.gl0.wr | FIFO_33b_8192_wr_logic | 58(0.02%) | 58(0.02%) | 0(0.00%) | 0(0.00%) | 77(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gpf.wrpf | FIFO_33b_8192_wr_pf_as | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.gwdc0.wdc | FIFO_33b_8192_wr_dc_as | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gwas.wsts | FIFO_33b_8192_wr_status_flags_as | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (gwas.wsts) | FIFO_33b_8192_wr_status_flags_as | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c1 | FIFO_33b_8192_compare | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | c2 | FIFO_33b_8192_compare_1 | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | wpntr | FIFO_33b_8192_wr_bin_cntr | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 52(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gntv_or_sync_fifo.mem | FIFO_33b_8192_memory | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gbm.gbmg.gbmga.ngecc.bmg | FIFO_33b_8192_blk_mem_gen_v8_4_9 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | inst_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_v8_4_9_synth | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | gnbram.gnativebmg.native_blk_mem_gen | FIFO_33b_8192_blk_mem_gen_top | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | valid.cstr | FIFO_33b_8192_blk_mem_gen_generic_cstr | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 7(0.59%) | 1(0.04%) | 0(0.00%) | | bindec_a.bindec_inst_a | FIFO_33b_8192_bindec | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bindec_b.bindec_inst_b | FIFO_33b_8192_bindec_0 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | has_mux_b.B | FIFO_33b_8192_blk_mem_gen_mux__parameterized0 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ramloop[0].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.04%) | 0(0.00%) | | ramloop[1].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized0 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[2].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[3].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized2 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[4].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized3 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[5].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized4 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[6].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized5 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | ramloop[7].ram.r | FIFO_33b_8192_blk_mem_gen_prim_width__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | prim_noinit.ram | FIFO_33b_8192_blk_mem_gen_prim_wrapper__parameterized6 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | rstblk | FIFO_33b_8192_reset_blk_ramfifo | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_RAW_Link_output_FIFO_FSM | FIFO_to_MGT_RAW_FSM | 49(0.01%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 141(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_rdout_ipb_slave | readout_ipb_slave | 516(0.15%) | 516(0.15%) | 0(0.00%) | 0(0.00%) | 961(0.14%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U4_rdout_ipb_slave) | readout_ipb_slave | 7(0.01%) | 7(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_Test_Cntl_Reg | ipbus_ctrlreg_v__parameterized2_18 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_pulsed_register | ipbus_ctrlreg_v__parameterized2_19 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_top_level_counters | ipbus_ctrlreg_v__parameterized4 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_ttc_parity_L1A_BCN | ipbus_ctrlreg_v__parameterized5 | 64(0.02%) | 64(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_slave | slave_TOB_readout | 235(0.07%) | 235(0.07%) | 0(0.00%) | 0(0.00%) | 544(0.08%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U11_LINK_OUTPUT_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_31 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U12_LINK_OUTPUT_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_32 | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U17_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_33 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U18_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_34 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_TOB_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_35 | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_EG_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_36 | 41(0.01%) | 41(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_XTOB_TAU_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_37 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_TOB_SLICES_TO_RD | ipbus_ctrlreg_v__parameterized2_38 | 3(0.01%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U4_trigger_slice | ipbus_ctrlreg_v__parameterized2_39 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_TOB_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_40 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_TOB_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_41 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_42 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_TOB_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_43 | 14(0.01%) | 14(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_EG_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_44 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_XTOB_TAU_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_45 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_EG_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_46 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9_XTOB_TAU_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_47 | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_RAW_slave | slave_RAW_readout | 144(0.04%) | 144(0.04%) | 0(0.00%) | 0(0.00%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U15_RAW_WR_ADDR_OFFSET_REG | ipbus_ctrlreg_v__parameterized2_20 | 10(0.01%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U1_RAW_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_21 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U2_RAW_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_22 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_23 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U3_RAW_BUSY_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_24 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U5_BCN_FIFO_pFULL_THRESH_assert | ipbus_ctrlreg_v__parameterized2_25 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U6_BCN_FIFO_pFULL_THRESH_negate | ipbus_ctrlreg_v__parameterized2_26 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U7_Link_output_FIFO_pFULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_27 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U8_Link_output_FIFO_pFULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_28 | 26(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9A_RAW_FIFO_FULL_THRESH_ASSERT | ipbus_ctrlreg_v__parameterized2_29 | 33(0.01%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U9B_RAW_FIFO_FULL_THRESH_NEGATE | ipbus_ctrlreg_v__parameterized2_30 | 37(0.01%) | 37(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | proc_FPGAs | 8282(2.39%) | 8263(2.39%) | 0(0.00%) | 19(0.01%) | 2801(0.40%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | U_0 | UDP_node_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 33(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | interconnect | 13(0.01%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 20(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (U_1) | interconnect | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_0 | parity_gen | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_1 | parity_checker | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 10(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | U_2 | ipbus_ctrl | 8269(2.39%) | 8250(2.38%) | 0(0.00%) | 19(0.01%) | 2748(0.40%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (U_2) | ipbus_ctrl | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | trans | transactor | 6763(1.95%) | 6763(1.95%) | 0(0.00%) | 0(0.00%) | 509(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (trans) | transactor | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | iface | transactor_if | 220(0.06%) | 220(0.06%) | 0(0.00%) | 0(0.00%) | 135(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | sm | transactor_sm | 6555(1.89%) | 6555(1.89%) | 0(0.00%) | 0(0.00%) | 374(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | udp_if | UDP_if | 1505(0.43%) | 1486(0.43%) | 0(0.00%) | 19(0.01%) | 2239(0.32%) | 17(1.44%) | 0(0.00%) | 0(0.00%) | | (udp_if) | UDP_if | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 13(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | IPADDR | udp_ipaddr_ipam | 194(0.06%) | 193(0.06%) | 0(0.00%) | 1(0.01%) | 224(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_crossing_if | udp_clock_crossing_if | 18(0.01%) | 18(0.01%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram | udp_DualPortRAM | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | internal_ram_selector | udp_buffer_selector | 9(0.01%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 9(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | internal_ram_shim | udp_rxram_shim | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ipbus_rx_ram | udp_DualPortRAM_rx | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | ipbus_tx_ram | udp_DualPortRAM_tx | 22(0.01%) | 22(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 8(0.68%) | 0(0.00%) | 0(0.00%) | | payload | udp_build_payload | 180(0.05%) | 180(0.05%) | 0(0.00%) | 0(0.00%) | 196(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | resend | udp_build_resend | 21(0.01%) | 19(0.01%) | 0(0.00%) | 2(0.01%) | 61(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_byte_sum | udp_byte_sum | 27(0.01%) | 27(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_packet_parser | udp_packet_parser | 107(0.03%) | 91(0.03%) | 0(0.00%) | 16(0.01%) | 352(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_mux | udp_rxram_mux | 15(0.01%) | 15(0.01%) | 0(0.00%) | 0(0.00%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_ram_selector | udp_buffer_selector__parameterized0 | 60(0.02%) | 60(0.02%) | 0(0.00%) | 0(0.00%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_reset_block | udp_do_rx_reset | 5(0.01%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_transactor | udp_rxtransactor_if | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status | udp_build_status | 143(0.04%) | 143(0.04%) | 0(0.00%) | 0(0.00%) | 171(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | status_buffer | udp_status_buffer | 231(0.07%) | 231(0.07%) | 0(0.00%) | 0(0.00%) | 434(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_byte_sum | udp_byte_sum_5 | 24(0.01%) | 24(0.01%) | 0(0.00%) | 0(0.00%) | 49(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_main | udp_tx_mux | 219(0.06%) | 219(0.06%) | 0(0.00%) | 0(0.00%) | 209(0.03%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_ram_selector | udp_buffer_selector__parameterized0_6 | 101(0.03%) | 101(0.03%) | 0(0.00%) | 0(0.00%) | 59(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_transactor | udp_txtransactor_if | 130(0.04%) | 130(0.04%) | 0(0.00%) | 0(0.00%) | 264(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | cclk_o | startup | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clock_resources | clk_resources | 22(0.01%) | 21(0.01%) | 0(0.00%) | 1(0.01%) | 26(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clock_resources) | clk_resources | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | Inputclk40M | ClockWizard | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | ClockWizard_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clk40_gen | clk_wiz_1 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | inst | clk_wiz_1_clk_wiz | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clocks | clocks_7s_extphy | 20(0.01%) | 19(0.01%) | 0(0.00%) | 1(0.01%) | 25(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (clocks) | clocks_7s_extphy | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 8(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | clkdiv | ipbus_clock_div | 4(0.01%) | 3(0.01%) | 0(0.00%) | 1(0.01%) | 17(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | configure | self_configure | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | config | reconfig | 30(0.01%) | 30(0.01%) | 0(0.00%) | 0(0.00%) | 55(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | slaves | slaves | 560(0.16%) | 560(0.16%) | 0(0.00%) | 0(0.00%) | 1337(0.19%) | 3(0.25%) | 0(0.00%) | 0(0.00%) | | RAM | ipbus_ram | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | bcmuxvalue_sync | ipbus_ctrlreg_v__parameterized2 | 16(0.01%) | 16(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | module_control | ipbus_ctrlreg_v__parameterized1 | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 473(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | reconfig | ipbus_ctrlreg_v__parameterized2_0 | 32(0.01%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_flash | ipbus_spi32 | 274(0.08%) | 274(0.08%) | 0(0.00%) | 0(0.00%) | 304(0.04%) | 2(0.17%) | 0(0.00%) | 0(0.00%) | | (spi_flash) | ipbus_spi32 | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | arbitration | ipbus_watchdog | 132(0.04%) | 132(0.04%) | 0(0.00%) | 0(0.00%) | 108(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | gen_clock | clock_pulse | 1(0.01%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_control | ipbus_ctrlreg_v__parameterized3 | 43(0.01%) | 43(0.01%) | 0(0.00%) | 0(0.00%) | 128(0.02%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | spi_dpram_in | ipbus_dpram_flash__parameterized0 | 21(0.01%) | 21(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_dpram_out | ipbus_dpram_flash | 2(0.01%) | 2(0.01%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 1(0.08%) | 0(0.00%) | 0(0.00%) | | spi_engine | spi32_8_control | 72(0.02%) | 72(0.02%) | 0(0.00%) | 0(0.00%) | 56(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | synch | command_sync | 4(0.01%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 5(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bc_delay | ipbus_ctrlreg_v__parameterized1_1 | 48(0.01%) | 48(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_bus_delay | ipbus_ctrlreg_v__parameterized1_2 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tob_synch | ipbus_ctrlreg_v__parameterized2_3 | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ttc_orbit_length | ipbus_ctrlreg_v__parameterized2_4 | 11(0.01%) | 11(0.01%) | 0(0.00%) | 0(0.00%) | 32(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | xadc | ipbus_xadc_drp | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 367(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (xadc) | ipbus_xadc_drp | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 1(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | adc_inst | xadc_eFEX | 146(0.04%) | 146(0.04%) | 0(0.00%) | 0(0.00%) | 366(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-------------------------------------------------------------------------------------------+------------------------------------------------------------------+----------------+----------------+----------+--------------+----------------+-------------+-----------+------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining