*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Wed Apr 2 17:38:39 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1767.637 ; gain = 142.836 ; free physical = 22123 ; free virtual = 43519 Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.dcp' for cell 'GLOBAL_MERGE.IO_DELAY_A1' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.dcp' for cell 'GLOBAL_MERGE.IO_DELAY_BC_A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM.dcp' for cell 'GLOBAL_MERGE.Merging_Module/inputRAM_1/ALGO_OUTPUT_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/SortingOutputRAM/SortingOutputRAM.dcp' for cell 'GLOBAL_MERGE.Merging_Module/outputRAM/ALGO_OUTPUT_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_209b_512/DPR_209b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U4_T_TOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3219.863 ; gain = 11.000 ; free physical = 20674 ; free virtual = 42069 INFO: [Netlist 29-17] Analyzing 29991 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] get_clocks: Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 5037.430 ; gain = 1118.477 ; free physical = 19030 ; free virtual = 40426 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_A/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_B/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_BC_C/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A1/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_A2/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B1/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_B2/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C1/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc] for cell 'GLOBAL_MERGE.IO_DELAY_C2/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[2].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[4].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:54] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga2.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga2.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga2.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga2.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga2.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga2.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga2.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1714] 112 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 5906.484 ; gain = 0.000 ; free physical = 18158 ; free virtual = 39555 INFO: [Project 1-111] Unisim Transformation Summary: A total of 66 instances were transformed. OBUFDS => OBUFDS: 66 instances 41 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:57 ; elapsed = 00:02:07 . Memory (MB): peak = 5906.484 ; gain = 4122.004 ; free physical = 18158 ; free virtual = 39555 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 5914.488 ; gain = 0.000 ; free physical = 18172 ; free virtual = 39568 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1aef3a775 Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 6076.488 ; gain = 162.000 ; free physical = 17974 ; free virtual = 39371 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1aef3a775 Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.5 . Memory (MB): peak = 6440.254 ; gain = 0.000 ; free physical = 17637 ; free virtual = 39034 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1aef3a775 Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.66 . Memory (MB): peak = 6440.254 ; gain = 0.000 ; free physical = 17637 ; free virtual = 39034 Phase 1 Initialization | Checksum: 1aef3a775 Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.71 . Memory (MB): peak = 6440.254 ; gain = 0.000 ; free physical = 17637 ; free virtual = 39034 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1aef3a775 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6440.254 ; gain = 0.000 ; free physical = 17620 ; free virtual = 39017 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1aef3a775 Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 6568.254 ; gain = 128.000 ; free physical = 17541 ; free virtual = 38938 Phase 2 Timer Update And Timing Data Collection | Checksum: 1aef3a775 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 6568.254 ; gain = 128.000 ; free physical = 17541 ; free virtual = 38938 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 28 inverters resulting in an inversion of 130 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 2ae9c20b3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 6568.254 ; gain = 128.000 ; free physical = 17543 ; free virtual = 38939 Retarget | Checksum: 2ae9c20b3 INFO: [Opt 31-389] Phase Retarget created 165 cells and removed 572 cells INFO: [Opt 31-1021] In phase Retarget, 226 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 22c3fb1ed Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 6568.254 ; gain = 128.000 ; free physical = 17542 ; free virtual = 38939 Constant propagation | Checksum: 22c3fb1ed INFO: [Opt 31-389] Phase Constant propagation created 57 cells and removed 253 cells INFO: [Opt 31-1021] In phase Constant propagation, 158 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 6568.254 ; gain = 0.000 ; free physical = 17540 ; free virtual = 38937 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6568.254 ; gain = 0.000 ; free physical = 17539 ; free virtual = 38936 Phase 5 Sweep | Checksum: 228a6801b Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 6568.254 ; gain = 128.000 ; free physical = 17541 ; free virtual = 38938 Sweep | Checksum: 228a6801b INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3480 cells INFO: [Opt 31-1021] In phase Sweep, 910 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 1e0edd4e1 Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17540 ; free virtual = 38937 BUFG optimization | Checksum: 1e0edd4e1 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1e0edd4e1 Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17540 ; free virtual = 38937 Shift Register Optimization | Checksum: 1e0edd4e1 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 274c9e0f9 Time (s): cpu = 00:00:35 ; elapsed = 00:00:32 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17540 ; free virtual = 38937 Post Processing Netlist | Checksum: 274c9e0f9 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 302 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2a0d36703 Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17543 ; free virtual = 38940 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.59 . Memory (MB): peak = 6600.270 ; gain = 0.000 ; free physical = 17543 ; free virtual = 38940 Phase 9.2 Verifying Netlist Connectivity | Checksum: 2a0d36703 Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17543 ; free virtual = 38940 Phase 9 Finalization | Checksum: 2a0d36703 Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17543 ; free virtual = 38940 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 165 | 572 | 226 | | Constant propagation | 57 | 253 | 158 | | Sweep | 0 | 3480 | 910 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 302 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 2a0d36703 Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 6600.270 ; gain = 160.016 ; free physical = 17543 ; free virtual = 38940 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 799 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 97 newly gated: 189 Total Ports: 1598 Ending PowerOpt Patch Enables Task | Checksum: 23f2cd082 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14374 ; free virtual = 35772 Ending Power Optimization Task | Checksum: 23f2cd082 Time (s): cpu = 00:02:26 ; elapsed = 00:01:51 . Memory (MB): peak = 9821.445 ; gain = 3221.176 ; free physical = 14374 ; free virtual = 35772 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1e8bb7127 Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14339 ; free virtual = 35737 Ending Final Cleanup Task | Checksum: 1e8bb7127 Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14339 ; free virtual = 35737 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14339 ; free virtual = 35737 Ending Netlist Obfuscation Task | Checksum: 1e8bb7127 Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14339 ; free virtual = 35737 INFO: [Common 17-83] Releasing license: Implementation 79 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:17 ; elapsed = 00:03:41 . Memory (MB): peak = 9821.445 ; gain = 3914.961 ; free physical = 14339 ; free virtual = 35737 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14327 ; free virtual = 35725 generate_parallel_reports: Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14327 ; free virtual = 35725 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.46 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13954 ; free virtual = 35718 Wrote PlaceDB: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13951 ; free virtual = 35716 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13951 ; free virtual = 35716 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.54 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13952 ; free virtual = 35718 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13952 ; free virtual = 35718 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13948 ; free virtual = 35716 Write Physdb Complete: Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.66 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 13948 ; free virtual = 35716 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:51 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14164 ; free virtual = 35644 Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14225 ; free virtual = 35704 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1bb18e81c Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14225 ; free virtual = 35704 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14225 ; free virtual = 35704 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Place 30-1907] GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl_REPLICATED_0 replication was created for GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl IDELAYCTRL INFO: [Place 30-1907] GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl_REPLICATED_0_1 replication was created for GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl IDELAYCTRL INFO: [Place 30-1907] GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl_REPLICATED_0_2 replication was created for GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl IDELAYCTRL INFO: [Place 30-1907] GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl_REPLICATED_0_3 replication was created for GLOBAL_MERGE.IO_DELAY_C2/inst/delayctrl IDELAYCTRL Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 116f3b779 Time (s): cpu = 00:04:04 ; elapsed = 00:04:04 . Memory (MB): peak = 9821.445 ; gain = 0.000 ; free physical = 14318 ; free virtual = 35731 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 174cb941c Time (s): cpu = 00:05:16 ; elapsed = 00:05:17 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14265 ; free virtual = 35679 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 174cb941c Time (s): cpu = 00:05:17 ; elapsed = 00:05:18 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14265 ; free virtual = 35679 Phase 1 Placer Initialization | Checksum: 174cb941c Time (s): cpu = 00:05:18 ; elapsed = 00:05:19 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14265 ; free virtual = 35679 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 22c66b80c Time (s): cpu = 00:05:44 ; elapsed = 00:05:45 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14263 ; free virtual = 35677 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 23cd2cab8 Time (s): cpu = 00:06:05 ; elapsed = 00:06:06 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14262 ; free virtual = 35676 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1ba837d6c Time (s): cpu = 00:06:06 ; elapsed = 00:06:07 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14262 ; free virtual = 35676 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1e3708d6c Time (s): cpu = 00:09:36 ; elapsed = 00:09:38 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14257 ; free virtual = 35673 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1ab61277d Time (s): cpu = 00:10:03 ; elapsed = 00:10:05 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14267 ; free virtual = 35683 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 199 LUTNM shape to break, 10951 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 88, two critical 111, total 199, new lutff created 12 INFO: [Physopt 32-1138] End 1 Pass. Optimized 5239 nets or LUTs. Breaked 199 LUTs, combined 5040 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-1408] Pass 1. Identified 22 candidate nets for high-fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_hdr_BCN_in_i. Replicated 21 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg_n_1_[10]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/IN_Load. Replicated 72 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 70 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start. Replicated 28 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/SR[0]. Replicated 18 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-232] Optimized 21 nets. Created 323 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 21 nets or cells. Created 323 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14275 ; free virtual = 35691 INFO: [Physopt 32-76] Pass 1. Identified 89 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[0]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[8]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[9]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[9]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/enb. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[6]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[14]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[14]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[13]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[0]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[5]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[15]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[7]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[12]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[5]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[7]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[11]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[8]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[13]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1065[14]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[4]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[10]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[6]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1065[7]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[6]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[5]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[10]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1033[3]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[6]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[3]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[0]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[3]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1065[8]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[9]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[12]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[8]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1107[0]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1107[8]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[12]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1107[9]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[7]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[10]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1065[9]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[7]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[5]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1107[6]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1107[4]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[6]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1032[11]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1107[12]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1041[3]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1054[9]. Replicated 7 times. INFO: [Physopt 32-232] Optimized 73 nets. Created 514 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 73 nets or cells. Created 514 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.72 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14273 ; free virtual = 35689 INFO: [Physopt 32-46] Identified 19 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[3] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[1] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[5] was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-457] Pass 1. Identified 15 candidate cells for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 15 nets or cells. Created 360 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14272 ; free virtual = 35688 INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1402] Pass 1: Identified 138 candidate cells for Shift Register optimization. INFO: [Physopt 32-775] End 1 Pass. Optimized 68 nets or cells. Created 102 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14272 ; free virtual = 35688 INFO: [Physopt 32-527] Pass 1: Identified 4 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 28 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 124 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.43 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14271 ; free virtual = 35688 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14271 ; free virtual = 35688 INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14271 ; free virtual = 35688 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 199 | 5040 | 5239 | 0 | 1 | 00:00:06 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 323 | 0 | 21 | 0 | 1 | 00:00:10 | | Fanout | 514 | 0 | 73 | 0 | 1 | 00:00:10 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 360 | 0 | 15 | 0 | 1 | 00:00:01 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 102 | 0 | 68 | 0 | 1 | 00:00:01 | | BRAM Register | 124 | 0 | 4 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 1622 | 5040 | 5420 | 0 | 12 | 00:00:29 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 247210a86 Time (s): cpu = 00:11:02 ; elapsed = 00:11:04 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14266 ; free virtual = 35683 Phase 2.5 Global Place Phase2 | Checksum: 231f69980 Time (s): cpu = 00:11:13 ; elapsed = 00:11:16 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14264 ; free virtual = 35681 Phase 2 Global Placement | Checksum: 231f69980 Time (s): cpu = 00:11:13 ; elapsed = 00:11:16 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14264 ; free virtual = 35681 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d63a96b9 Time (s): cpu = 00:11:40 ; elapsed = 00:11:43 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14263 ; free virtual = 35680 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 297be9bf8 Time (s): cpu = 00:12:41 ; elapsed = 00:12:44 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14261 ; free virtual = 35680 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 29dd61b2f Time (s): cpu = 00:12:45 ; elapsed = 00:12:48 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14261 ; free virtual = 35679 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 250719cc6 Time (s): cpu = 00:12:46 ; elapsed = 00:12:49 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14261 ; free virtual = 35679 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 2422803b5 Time (s): cpu = 00:13:52 ; elapsed = 00:13:55 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14262 ; free virtual = 35681 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 215407125 Time (s): cpu = 00:15:17 ; elapsed = 00:15:20 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14256 ; free virtual = 35676 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 2058a0d4e Time (s): cpu = 00:15:30 ; elapsed = 00:15:33 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14255 ; free virtual = 35674 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 21bf89c3f Time (s): cpu = 00:15:33 ; elapsed = 00:15:36 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14255 ; free virtual = 35675 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 20aea1cd7 Time (s): cpu = 00:17:11 ; elapsed = 00:17:15 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14914 ; free virtual = 36334 Phase 3 Detail Placement | Checksum: 20aea1cd7 Time (s): cpu = 00:17:14 ; elapsed = 00:17:17 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14913 ; free virtual = 36333 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 200595a53 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.938 | TNS=-225.734 | Phase 1 Physical Synthesis Initialization | Checksum: 1dfa8ab83 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14820 ; free virtual = 36241 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 2bd1dc605 Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14817 ; free virtual = 36238 Phase 4.1.1.1 BUFG Insertion | Checksum: 200595a53 Time (s): cpu = 00:19:14 ; elapsed = 00:19:18 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14818 ; free virtual = 36239 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.291. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2488fcecf Time (s): cpu = 00:20:45 ; elapsed = 00:20:50 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14823 ; free virtual = 36244 Time (s): cpu = 00:20:45 ; elapsed = 00:20:50 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14823 ; free virtual = 36244 Phase 4.1 Post Commit Optimization | Checksum: 2488fcecf Time (s): cpu = 00:20:47 ; elapsed = 00:20:53 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14821 ; free virtual = 36242 Post Placement Optimization Initialization | Checksum: 1d047e4b7 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.422 | TNS=-129.060 | Phase 1 Physical Synthesis Initialization | Checksum: 1cab8fb1d Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14563 ; free virtual = 35987 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 2a1fc00cf Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14560 ; free virtual = 35984 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.189. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1eaaf3b51 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-32.721 | Phase 1 Physical Synthesis Initialization | Checksum: 21d29b8a4 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14560 ; free virtual = 35985 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 269f299e2 Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14565 ; free virtual = 35990 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.189. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1faf94978 Time (s): cpu = 00:29:58 ; elapsed = 00:30:07 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14571 ; free virtual = 35997 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 16x16| 8x8| |___________|___________________|___________________| | South| 16x16| 4x4| |___________|___________________|___________________| | East| 1x1| 2x2| |___________|___________________|___________________| | West| 16x16| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1faf94978 Time (s): cpu = 00:30:01 ; elapsed = 00:30:10 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14568 ; free virtual = 35994 Phase 4.3 Placer Reporting | Checksum: 1faf94978 Time (s): cpu = 00:30:03 ; elapsed = 00:30:12 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14567 ; free virtual = 35994 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14567 ; free virtual = 35994 Time (s): cpu = 00:30:04 ; elapsed = 00:30:13 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14567 ; free virtual = 35994 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 16b1db645 Time (s): cpu = 00:30:06 ; elapsed = 00:30:15 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14567 ; free virtual = 35993 Ending Placer Task | Checksum: c9e1f568 Time (s): cpu = 00:30:08 ; elapsed = 00:30:17 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14571 ; free virtual = 35998 261 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:30:33 ; elapsed = 00:30:42 . Memory (MB): peak = 9829.445 ; gain = 8.000 ; free physical = 14571 ; free virtual = 35998 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.71 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14552 ; free virtual = 35979 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:01 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14533 ; free virtual = 35962 generate_parallel_reports: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14532 ; free virtual = 35962 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.77 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14166 ; free virtual = 35981 Wrote PlaceDB: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13846 ; free virtual = 35983 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13846 ; free virtual = 35983 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.56 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13846 ; free virtual = 35984 Wrote Netlist Cache: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.34 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13814 ; free virtual = 35983 Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13814 ; free virtual = 35985 Write Physdb Complete: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13814 ; free virtual = 35985 report_design_analysis: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13799 ; free virtual = 35971 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:18 ; elapsed = 00:01:22 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14433 ; free virtual = 35979 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Starting Initial Update Timing Task Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14445 ; free virtual = 35991 INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 70.91s | WALL: 70.99s Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14444 ; free virtual = 35990 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.634 | Phase 1 Physical Synthesis Initialization | Checksum: 1e1812e3c Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14451 ; free virtual = 35997 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.634 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 1e1812e3c Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14450 ; free virtual = 35996 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.634 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[11]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[11] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[11]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.671 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[1]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[1] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.708 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[20]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[20] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[20]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.745 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[21] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.189 | TNS=-15.782 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[27]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk200_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_7__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_105. Rewiring did not optimize the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 13 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_105. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.148 | TNS=-13.969 | INFO: [Physopt 32-608] Optimized 1 net. Swapped 18 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry__0_i_4__14_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.142 | TNS=-13.735 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry__0_i_4__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_112. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[9]_i_2__5 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_112. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.135 | TNS=-13.462 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_112. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[9]_i_2__5 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_112. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.107 | TNS=-12.370 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_103. Rewiring did not optimize the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 6 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_103. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.096 | TNS=-11.241 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[5]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[5] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.096 | TNS=-11.145 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[7]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[7] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.090 | TNS=-11.050 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ramloop[3].ram.ram_doutb[8]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/din[12]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_reg[12] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/din[12]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.090 | TNS=-10.946 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/D[10]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__4_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_120. Rewiring did not optimize the net. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_120. Replicated 1 times. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_120. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.087 | TNS=-10.259 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/RAW_data_FIFO_flags_i[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U1_RAW_readout/FIFO_RAW_Data_empty_tmp_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U1_RAW_readout/FIFO_RAW_Data_empty_tmp_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/FIFO_RAW_Data_empty_tmp_i_2_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.085 | TNS=-10.172 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[4]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[4] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.085 | TNS=-10.149 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[5]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[5] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-10.126 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[10]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[10] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[10]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-10.106 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[18]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[18] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-10.086 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[21] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-10.083 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER/FastFifo_2/mem_reg_n_1_[2][24]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER/FastFifo_2/mem_reg[2][24] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[2].ifFirst.sorter_gen0[0].PAR_SORTER/FastFifo_2/mem_reg_n_1_[2][24]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-10.002 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[59].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt3_min_latency_1_quad_rx_tx_i/gt3_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[59].u0/state_machine/delay_count[3]_i_2__43_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[59].u0/state_machine/delay_count[3]_i_2__43 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[59].u0/state_machine/delay_count[3]_i_2__43_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.878 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[55].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt3_min_latency_1_quad_rx_tx_i/gt3_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[55].u0/state_machine/delay_count[3]_i_2__55_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[55].u0/state_machine/delay_count[3]_i_2__55 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[55].u0/state_machine/delay_count[3]_i_2__55_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.778 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt3_min_latency_1_quad_rx_tx_i/gt3_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/delay_count[3]_i_2__6_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/delay_count[3]_i_2__6 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/delay_count[3]_i_2__6_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.701 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[3].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt3_min_latency_1_quad_rx_tx_i/gt3_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[3].u0/state_machine/delay_count[3]_i_2__16_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[3].u0/state_machine/delay_count[3]_i_2__16 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[3].u0/state_machine/delay_count[3]_i_2__16_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.626 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[33].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt1_min_latency_1_quad_rx_tx_i/gt1_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[33].u0/state_machine/delay_count[3]_i_2__54_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[33].u0/state_machine/delay_count[3]_i_2__54 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[33].u0/state_machine/delay_count[3]_i_2__54_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.583 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[13].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[3].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt1_min_latency_1_quad_rx_tx_i/gt1_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[13].u0/state_machine/delay_count[3]_i_2__38_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[13].u0/state_machine/delay_count[3]_i_2__38 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[13].u0/state_machine/delay_count[3]_i_2__38_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.542 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[25].u0/state_machine/current_state[1]. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[25].u0/state_machine/FSM_sequential_current_state_reg[1] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[25].u0/state_machine/current_state[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.512 | INFO: [Physopt 32-663] Processed net MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT0/cntr_0/enable2_i. Re-placed instance MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT0/cntr_0/enable2_i_reg INFO: [Physopt 32-735] Processed net MGT_IF.MGT_ipb/QUAD_FOR[19].quad/MGT_GT0/cntr_0/enable2_i. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.485 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].DPR_RAW_out_i_1dly_reg_n_1_[14][35]. Re-placed instance READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].DPR_RAW_out_i_1dly_reg[14][35] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].DPR_RAW_out_i_1dly_reg_n_1_[14][35]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.460 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[32].u0/state_machine/delay_count[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0/min_latency_1_quad_rx_tx_i/gt0_min_latency_1_quad_rx_tx_i/gt0_rxchariscomma_out[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[32].u0/state_machine/delay_count[3]_i_2__42_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[32].u0/state_machine/delay_count[3]_i_2__42 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[32].u0/state_machine/delay_count[3]_i_2__42_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.433 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/Q[5]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/rd_en. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[54].u0/state_machine/current_state[1]. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[54].u0/state_machine/FSM_sequential_current_state_reg[1] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[54].u0/state_machine/current_state[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.422 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/current_state[1]. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/FSM_sequential_current_state_reg[1] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[63].u0/state_machine/current_state[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.412 | INFO: [Physopt 32-663] Processed net MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT1/cntr_1/enable1_i. Re-placed instance MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT1/cntr_1/enable1_i_reg INFO: [Physopt 32-735] Processed net MGT_IF.MGT_ipb/QUAD_FOR[18].quad/MGT_GT1/cntr_1/enable1_i. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.402 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[61].u0/state_machine/current_state[1]. Re-placed instance DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[61].u0/state_machine/FSM_sequential_current_state_reg[1] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/data_alignment_block/synch_gen[61].u0/state_machine/current_state[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.396 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[27]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk200_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_6__54_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 13 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_39. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.336 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[1]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[1] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.082 | TNS=-9.331 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[20]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[20] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[20]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.080 | TNS=-9.326 | INFO: [Physopt 32-608] Optimized 1 net. Swapped 34 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_7__54_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.078 | TNS=-9.213 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[27]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_5__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 15 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_109. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.077 | TNS=-9.178 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry__0_i_3__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 15 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_113. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.077 | TNS=-9.178 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 12 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_104. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.077 | TNS=-8.933 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[2].SORT_CELL/Q[18]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[1].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 34 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[1].SORT_CELL/Inhibit1_carry_i_8__25_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.075 | TNS=-8.704 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__54_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_35. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[0]_i_2__1 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_35. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-8.624 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[18]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[18] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-8.550 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/Q[5]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/rd_en. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-8.550 | Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.25 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14449 ; free virtual = 35995 Phase 3 Critical Path Optimization | Checksum: 12f50bbbe Time (s): cpu = 00:01:08 ; elapsed = 00:01:08 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14449 ; free virtual = 35995 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-8.550 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[21] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[3].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-8.477 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/ADDER_TREE/ET/stage_gen[4].adder_gen[13].ADD/OutCarry_reg_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk200_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/ADDER_TREE/ET/stage_gen[4].adder_gen[13].ADD/OutWord_reg[15]_i_1__94_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/ADDER_TREE/ET/stage_gen[4].adder_gen[13].ADD/OutWord_reg[11]_i_1__94_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/ADDER_TREE/ET/stage_gen[4].adder_gen[13].ADD/OutWord_reg[7]_i_1__94_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/ADDER_TREE/ET/stage_gen[4].adder_gen[13].ADD/OutWord[7]_i_5_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU_BDT/ADDER_TREE/ET/stage_gen[4].adder_gen[13].ADD/p_0_in. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O932[4]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/ShiftTowers_reg[2][7][Layer2][2][4] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O932[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.071 | TNS=-8.350 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/D[27]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__54_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_35. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[0]_i_2__1 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_35. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.070 | TNS=-7.890 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/D[27]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_6__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_107. Rewiring did not optimize the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 6 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_107. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.067 | TNS=-7.680 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/D[10]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[0].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__4_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_120_repN. Rewiring did not optimize the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 20 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_120_repN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.067 | TNS=-7.037 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/D[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_8__24_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_86. Rewiring did not optimize the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 16 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_86. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.064 | TNS=-6.981 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry__0_i_4__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_111. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[8]_i_2__5 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_111. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.063 | TNS=-6.946 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[1].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry__0_i_3__14_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_114. Rewiring did not optimize the net. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_114. Replicated 1 times. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_114. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.059 | TNS=-6.375 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[10]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/StoredWord_reg[10] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[10]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.059 | TNS=-6.392 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/D[21]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[4].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_6__44_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_56. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[4]_i_2__2 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_56. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-5.206 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/Q[5]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U1_TOB_sorting_gen.U1_TOBs_sorting/U5_T_TOBs_fifo/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg_0[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/rd_en. Replicated 1 times. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/rd_en. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-5.131 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[14]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[14] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[14]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-5.074 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[15]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[15] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[15]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-5.017 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[16]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[16] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[16]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-4.961 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[18]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[18] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[18]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-4.904 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[5]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[5] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[5]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-4.847 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[6]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[6] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[6]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-4.791 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[7]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[7] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.057 | TNS=-4.734 | INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[9]. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/StoredWord_reg[9] INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[5].SerialSorter_eg/SortingCells[0].SORT_CELL/D[9]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.056 | TNS=-4.678 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[2].SORT_CELL/Q[18]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk200_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[1].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 18 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[1].SORT_CELL/Inhibit1_carry__0_i_3__25_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.053 | TNS=-4.566 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/D[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/CO[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/out_tob_for[2].SerialSorter_tau/SortingCells[0].SORT_CELL/Inhibit1_carry_i_7__24_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_89. Re-placed instance DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/StoredWord[3]_i_2__4 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_REGISTERS/reg_reg[1][0]_89. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.053 | TNS=-4.550 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.053 | TNS=-4.550 | Netlist sorting complete. Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.28 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14442 ; free virtual = 35990 Phase 4 Critical Path Optimization | Checksum: cb72c502 Time (s): cpu = 00:01:20 ; elapsed = 00:01:21 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14442 ; free virtual = 35990 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14442 ; free virtual = 35990 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.053 | TNS=-4.550 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:04 | | Critical Path | 0.136 | 11.083 | 3 | 0 | 65 | 0 | 2 | 00:00:29 | | Total | 0.136 | 11.083 | 3 | 0 | 65 | 0 | 3 | 00:00:32 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14442 ; free virtual = 35990 Ending Physical Synthesis Task | Checksum: 1476bcf6e Time (s): cpu = 00:01:24 ; elapsed = 00:01:24 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14441 ; free virtual = 35989 INFO: [Common 17-83] Releasing license: Implementation 567 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:02:35 ; elapsed = 00:02:36 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14441 ; free virtual = 35989 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.47 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14084 ; free virtual = 35991 Wrote PlaceDB: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13760 ; free virtual = 35988 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13760 ; free virtual = 35988 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.56 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13759 ; free virtual = 35989 Wrote Netlist Cache: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13728 ; free virtual = 35988 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13720 ; free virtual = 35982 Write Physdb Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13720 ; free virtual = 35982 report_design_analysis: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 13689 ; free virtual = 35953 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:02 ; elapsed = 00:01:06 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14223 ; free virtual = 35884 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: 7183ec44 ConstDB: 0 ShapeSum: 7cb82b19 RouteDB: 5324b193 Post Restoration Checksum: NetGraph: 7f39e0e0 | NumContArr: 167920c9 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 21b04f6e3 Time (s): cpu = 00:02:08 ; elapsed = 00:02:09 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14332 ; free virtual = 35994 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 21b04f6e3 Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14331 ; free virtual = 35993 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 21b04f6e3 Time (s): cpu = 00:02:13 ; elapsed = 00:02:13 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14331 ; free virtual = 35993 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 23efb8a6f Time (s): cpu = 00:04:16 ; elapsed = 00:04:17 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14166 ; free virtual = 35829 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.249 | TNS=-4.082 | WHS=-0.517 | THS=-12851.528| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 1c0ef23e7 Time (s): cpu = 00:05:41 ; elapsed = 00:05:42 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14057 ; free virtual = 35720 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.249 | TNS=-6.136 | WHS=-0.569 | THS=-3397.537| Phase 2.4 Update Timing for Bus Skew | Checksum: 2653e54a7 Time (s): cpu = 00:05:42 ; elapsed = 00:05:43 . Memory (MB): peak = 9829.445 ; gain = 0.000 ; free physical = 14056 ; free virtual = 35720 Router Utilization Summary Global Vertical Routing Utilization = 1.80662e-05 % Global Horizontal Routing Utilization = 9.83014e-06 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 420669 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 420667 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2414b8968 Time (s): cpu = 00:05:47 ; elapsed = 00:05:48 . Memory (MB): peak = 9840.805 ; gain = 11.359 ; free physical = 14037 ; free virtual = 35701 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2414b8968 Time (s): cpu = 00:05:48 ; elapsed = 00:05:49 . Memory (MB): peak = 9840.805 ; gain = 11.359 ; free physical = 14037 ; free virtual = 35701 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 1a72d7334 Time (s): cpu = 00:07:55 ; elapsed = 00:07:56 . Memory (MB): peak = 9855.805 ; gain = 26.359 ; free physical = 14037 ; free virtual = 35702 Phase 4 Initial Routing | Checksum: 1a72d7334 Time (s): cpu = 00:07:56 ; elapsed = 00:07:57 . Memory (MB): peak = 9855.805 ; gain = 26.359 ; free physical = 14036 ; free virtual = 35701 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 30936 Number of Nodes with overlaps = 1905 Number of Nodes with overlaps = 396 Number of Nodes with overlaps = 95 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.230 | TNS=-7.021 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 1875df704 Time (s): cpu = 00:15:49 ; elapsed = 00:15:51 . Memory (MB): peak = 10111.656 ; gain = 282.211 ; free physical = 13767 ; free virtual = 35435 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 178 Number of Nodes with overlaps = 202 Number of Nodes with overlaps = 102 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.201 | TNS=-0.953 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 2e1df287d Time (s): cpu = 00:18:08 ; elapsed = 00:18:10 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13742 ; free virtual = 35411 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 54 Number of Nodes with overlaps = 101 Number of Nodes with overlaps = 107 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.143 | TNS=-0.793 | WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 27231193a Time (s): cpu = 00:20:08 ; elapsed = 00:20:10 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13745 ; free virtual = 35414 Phase 5.4 Global Iteration 3 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 70 Number of Nodes with overlaps = 44 Number of Nodes with overlaps = 37 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.142 | TNS=-0.480 | WHS=N/A | THS=N/A | Phase 5.4 Global Iteration 3 | Checksum: 1e2d42bef Time (s): cpu = 00:22:16 ; elapsed = 00:22:19 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13740 ; free virtual = 35411 Phase 5.5 Global Iteration 4 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.142 | TNS=-0.390 | WHS=N/A | THS=N/A | Phase 5.5 Global Iteration 4 | Checksum: 2381e21e3 Time (s): cpu = 00:23:12 ; elapsed = 00:23:15 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13737 ; free virtual = 35408 Phase 5 Rip-up And Reroute | Checksum: 2381e21e3 Time (s): cpu = 00:23:13 ; elapsed = 00:23:16 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13737 ; free virtual = 35408 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 20f5d201f Time (s): cpu = 00:23:39 ; elapsed = 00:23:42 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13740 ; free virtual = 35411 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.068 | TNS=-0.123 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 6.1 Delay CleanUp | Checksum: 1ce7ac536 Time (s): cpu = 00:23:43 ; elapsed = 00:23:47 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13734 ; free virtual = 35406 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 1ce7ac536 Time (s): cpu = 00:23:44 ; elapsed = 00:23:48 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13734 ; free virtual = 35406 Phase 6 Delay and Skew Optimization | Checksum: 1ce7ac536 Time (s): cpu = 00:23:45 ; elapsed = 00:23:49 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13734 ; free virtual = 35406 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.068 | TNS=-0.123 | WHS=-0.057 | THS=-0.057 | Phase 7.1 Hold Fix Iter | Checksum: 2f375e766 Time (s): cpu = 00:24:16 ; elapsed = 00:24:19 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13742 ; free virtual = 35413 Phase 7.2 Non Free Resource Hold Fix Iter Phase 7.2 Non Free Resource Hold Fix Iter | Checksum: 32bd57daa Time (s): cpu = 00:24:17 ; elapsed = 00:24:20 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13744 ; free virtual = 35416 Phase 7 Post Hold Fix | Checksum: 32bd57daa Time (s): cpu = 00:24:18 ; elapsed = 00:24:21 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13744 ; free virtual = 35416 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 332ec1bf8 Time (s): cpu = 00:24:59 ; elapsed = 00:25:02 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13748 ; free virtual = 35420 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.068 | TNS=-0.123 | WHS=0.051 | THS=0.000 | Phase 8 Timing Verification | Checksum: 332ec1bf8 Time (s): cpu = 00:25:00 ; elapsed = 00:25:03 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13748 ; free virtual = 35420 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 32.7452 % Global Horizontal Routing Utilization = 25.528 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 4x4 Area, Max Cong = 85.473%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X48Y208 -> INT_R_X51Y211 INT_L_X52Y200 -> INT_FEEDTHRU_2_X144Y212 South Dir 2x2 Area, Max Cong = 88.964%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X136Y296 -> INT_R_X137Y297 INT_L_X136Y294 -> INT_R_X137Y295 INT_L_X130Y256 -> INT_R_X131Y257 INT_L_X126Y246 -> INT_R_X127Y247 INT_L_X94Y236 -> INT_R_X95Y237 East Dir 1x1 Area, Max Cong = 88.2353%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X135Y342 -> INT_R_X135Y342 INT_R_X137Y340 -> INT_R_X137Y340 INT_L_X82Y295 -> INT_L_X82Y295 INT_L_X86Y236 -> INT_L_X86Y236 West Dir 2x2 Area, Max Cong = 88.2353%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X88Y308 -> INT_R_X89Y309 INT_L_X104Y298 -> INT_R_X105Y299 INT_L_X48Y220 -> INT_R_X49Y221 INT_L_X50Y218 -> INT_R_X51Y219 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 2 Effective congestion level: 3 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 1 Sparse Ratio: 1.1875 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 0.666667 Sparse Ratio: 1.9375 Phase 9 Route finalize | Checksum: 332ec1bf8 Time (s): cpu = 00:25:02 ; elapsed = 00:25:05 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13748 ; free virtual = 35420 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 332ec1bf8 Time (s): cpu = 00:25:04 ; elapsed = 00:25:07 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13749 ; free virtual = 35421 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 310edef1b Time (s): cpu = 00:25:30 ; elapsed = 00:25:34 . Memory (MB): peak = 10128.023 ; gain = 298.578 ; free physical = 13747 ; free virtual = 35419 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 10128.023 ; gain = 0.000 ; free physical = 13751 ; free virtual = 35423 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.034. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 271c57ef9 Time (s): cpu = 00:04:15 ; elapsed = 00:04:17 . Memory (MB): peak = 10810.953 ; gain = 682.930 ; free physical = 13048 ; free virtual = 34722 Phase 12 Incr Placement Change | Checksum: 271c57ef9 Time (s): cpu = 00:29:54 ; elapsed = 00:29:59 . Memory (MB): peak = 10810.953 ; gain = 981.508 ; free physical = 13050 ; free virtual = 34724 Phase 13 Build RT Design Checksum: PlaceDB: 97397e1b ConstDB: 0 ShapeSum: ddef400b RouteDB: fc9cc0d3 Post Restoration Checksum: NetGraph: ac99798b | NumContArr: 962cc4e7 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 13 Build RT Design | Checksum: 2c81833ac Time (s): cpu = 00:31:19 ; elapsed = 00:31:23 . Memory (MB): peak = 10810.953 ; gain = 981.508 ; free physical = 13054 ; free virtual = 34728 Phase 14 Router Initialization Phase 14.1 Fix Topology Constraints Phase 14.1 Fix Topology Constraints | Checksum: 2c81833ac Time (s): cpu = 00:31:22 ; elapsed = 00:31:27 . Memory (MB): peak = 10810.953 ; gain = 981.508 ; free physical = 13056 ; free virtual = 34730 Phase 14.2 Pre Route Cleanup Phase 14.2 Pre Route Cleanup | Checksum: 2c0e3eecd Time (s): cpu = 00:31:25 ; elapsed = 00:31:30 . Memory (MB): peak = 10810.953 ; gain = 981.508 ; free physical = 13056 ; free virtual = 34730 Number of Nodes with overlaps = 0 Phase 14.3 Update Timing Phase 14.3 Update Timing | Checksum: 179e2542d Time (s): cpu = 00:33:37 ; elapsed = 00:33:42 . Memory (MB): peak = 10810.953 ; gain = 981.508 ; free physical = 13056 ; free virtual = 34734 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.077 | TNS=-0.077 | WHS=-0.517 | THS=-12773.626| Phase 14.4 Update Timing for Bus Skew Phase 14.4.1 Update Timing Phase 14.4.1 Update Timing | Checksum: 26da6c703 Time (s): cpu = 00:34:51 ; elapsed = 00:34:56 . Memory (MB): peak = 10818.953 ; gain = 989.508 ; free physical = 13028 ; free virtual = 34707 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.077 | TNS=0.000 | WHS=-0.290 | THS=-1.673 | Phase 14.4 Update Timing for Bus Skew | Checksum: 1c2703007 Time (s): cpu = 00:34:53 ; elapsed = 00:34:58 . Memory (MB): peak = 10818.953 ; gain = 989.508 ; free physical = 13028 ; free virtual = 34707 Router Utilization Summary Global Vertical Routing Utilization = 32.6689 % Global Horizontal Routing Utilization = 25.486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 719 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 426 Number of Partially Routed Nets = 293 Number of Node Overlaps = 0 Phase 14 Router Initialization | Checksum: 16ffaee0f Time (s): cpu = 00:34:59 ; elapsed = 00:35:04 . Memory (MB): peak = 10818.953 ; gain = 989.508 ; free physical = 13023 ; free virtual = 34702 Phase 15 Global Routing Phase 15 Global Routing | Checksum: 16ffaee0f Time (s): cpu = 00:35:00 ; elapsed = 00:35:05 . Memory (MB): peak = 10818.953 ; gain = 989.508 ; free physical = 13023 ; free virtual = 34701 Phase 16 Initial Routing Phase 16.1 Initial Net Routing Pass Phase 16.1 Initial Net Routing Pass | Checksum: 2577dd1dd Time (s): cpu = 00:35:06 ; elapsed = 00:35:12 . Memory (MB): peak = 10818.953 ; gain = 989.508 ; free physical = 13031 ; free virtual = 34709 Phase 16 Initial Routing | Checksum: 2577dd1dd Time (s): cpu = 00:35:08 ; elapsed = 00:35:13 . Memory (MB): peak = 10818.953 ; gain = 989.508 ; free physical = 13031 ; free virtual = 34709 Phase 17 Rip-up And Reroute Phase 17.1 Global Iteration 0 Number of Nodes with overlaps = 933 Number of Nodes with overlaps = 310 Number of Nodes with overlaps = 167 Number of Nodes with overlaps = 86 Number of Nodes with overlaps = 64 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.050 | TNS=-0.088 | WHS=N/A | THS=N/A | Phase 17.1 Global Iteration 0 | Checksum: 282964c85 Time (s): cpu = 00:37:52 ; elapsed = 00:37:57 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12866 ; free virtual = 34546 Phase 17.2 Global Iteration 1 Number of Nodes with overlaps = 2173 Number of Nodes with overlaps = 454 Number of Nodes with overlaps = 134 Number of Nodes with overlaps = 89 Number of Nodes with overlaps = 33 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.050 | TNS=-0.050 | WHS=N/A | THS=N/A | Phase 17.2 Global Iteration 1 | Checksum: 26f632ef1 Time (s): cpu = 00:39:25 ; elapsed = 00:39:30 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12877 ; free virtual = 34558 Phase 17 Rip-up And Reroute | Checksum: 26f632ef1 Time (s): cpu = 00:39:26 ; elapsed = 00:39:31 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12877 ; free virtual = 34558 Phase 18 Delay and Skew Optimization Phase 18.1 Delay CleanUp Phase 18.1.1 Update Timing Phase 18.1.1 Update Timing | Checksum: 25d491e2a Time (s): cpu = 00:39:53 ; elapsed = 00:39:59 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12874 ; free virtual = 34555 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.021 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18.1 Delay CleanUp | Checksum: 245eb03d5 Time (s): cpu = 00:39:54 ; elapsed = 00:40:00 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12874 ; free virtual = 34555 Phase 18.2 Clock Skew Optimization Phase 18.2 Clock Skew Optimization | Checksum: 245eb03d5 Time (s): cpu = 00:39:55 ; elapsed = 00:40:01 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12874 ; free virtual = 34555 Phase 18 Delay and Skew Optimization | Checksum: 245eb03d5 Time (s): cpu = 00:39:56 ; elapsed = 00:40:02 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12874 ; free virtual = 34555 Phase 19 Post Hold Fix Phase 19.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.021 | TNS=0.000 | WHS=0.051 | THS=0.000 | Phase 19.1 Hold Fix Iter | Checksum: 29bcce30f Time (s): cpu = 00:40:27 ; elapsed = 00:40:32 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12868 ; free virtual = 34549 Phase 19 Post Hold Fix | Checksum: 29bcce30f Time (s): cpu = 00:40:28 ; elapsed = 00:40:33 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12868 ; free virtual = 34549 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 223af6447 Time (s): cpu = 00:41:09 ; elapsed = 00:41:14 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12860 ; free virtual = 34541 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.021 | TNS=0.000 | WHS=0.051 | THS=0.000 | Phase 20 Timing Verification | Checksum: 223af6447 Time (s): cpu = 00:41:10 ; elapsed = 00:41:15 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12860 ; free virtual = 34541 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 32.7529 % Global Horizontal Routing Utilization = 25.5384 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 21 Route finalize | Checksum: 223af6447 Time (s): cpu = 00:41:12 ; elapsed = 00:41:18 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12859 ; free virtual = 34540 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 223af6447 Time (s): cpu = 00:41:13 ; elapsed = 00:41:19 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12859 ; free virtual = 34540 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 1b470dce0 Time (s): cpu = 00:41:40 ; elapsed = 00:41:46 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12857 ; free virtual = 34538 Phase 24 Post Process Routing Phase 24 Post Process Routing | Checksum: 1b470dce0 Time (s): cpu = 00:41:42 ; elapsed = 00:41:47 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12857 ; free virtual = 34538 Phase 25 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.023 | TNS=0.000 | WHS=0.052 | THS=0.000 | Phase 25 Post Router Timing | Checksum: 2155dedb4 Time (s): cpu = 00:43:15 ; elapsed = 00:43:20 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12855 ; free virtual = 34538 INFO: [Route 35-61] The design met the timing requirement. Total Elapsed time in route_design: 2600.64 secs Phase 26 Post-Route Event Processing Phase 26 Post-Route Event Processing | Checksum: 1a955b904 Time (s): cpu = 00:43:18 ; elapsed = 00:43:24 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12855 ; free virtual = 34537 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 1a955b904 Time (s): cpu = 00:43:24 ; elapsed = 00:43:29 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12854 ; free virtual = 34536 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 595 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:43:29 ; elapsed = 00:43:35 . Memory (MB): peak = 10977.320 ; gain = 1147.875 ; free physical = 12856 ; free virtual = 34539 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx Command: report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:17 ; elapsed = 00:01:17 . Memory (MB): peak = 10977.320 ; gain = 0.000 ; free physical = 12835 ; free virtual = 34520 INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx Command: report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.2/efex_processor.2.runs/impl_1/top_efex_processor_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:46 ; elapsed = 00:02:47 . Memory (MB): peak = 10977.320 ; gain = 0.000 ; free physical = 12823 ; free virtual = 34510 INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_processor_timing_summary_routed.rpt -pb top_efex_processor_timing_summary_routed.pb -rpx top_efex_processor_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 10977.320 ; gain = 0.000 ; free physical = 12729 ; free virtual = 34502 INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_processor_timing_summary_routed_1.rpt -pb top_efex_processor_timing_summary_routed_1.pb -rpx top_efex_processor_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 10977.320 ; gain = 0.000 ; free physical = 12724 ; free virtual = 34500 INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_processor_route_status.rpt -pb top_efex_processor_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_processor_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_processor_bus_skew_routed.rpt -pb top_efex_processor_bus_skew_routed.pb -rpx top_efex_processor_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx Command: report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 614 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:16 ; elapsed = 00:00:58 . Memory (MB): peak = 11113.324 ; gain = 136.004 ; free physical = 12709 ; free virtual = 34505 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_processor_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 11113.324 ; gain = 0.000 ; free physical = 12703 ; free virtual = 34499 generate_parallel_reports: Time (s): cpu = 00:07:38 ; elapsed = 00:07:25 . Memory (MB): peak = 11113.324 ; gain = 136.004 ; free physical = 12703 ; free virtual = 34499 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.2... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.1-4A2152C INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_processor.2 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] The git SHA value 4a2152c will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.2... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.2 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.1-4A2152C INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.2-v1.7.1-4A2152C... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 11113.324 ; gain = 0.000 ; free physical = 12684 ; free virtual = 34487