*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Wed Apr 2 18:59:31 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1767.641 ; gain = 139.836 ; free physical = 27276 ; free virtual = 43875 Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.FASTMULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/FastMult/FastMult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[2].SPEED.FASTMULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3204.039 ; gain = 11.000 ; free physical = 25860 ; free virtual = 42458 INFO: [Netlist 29-17] Analyzing 28189 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] get_clocks: Time (s): cpu = 00:00:30 ; elapsed = 00:00:13 . Memory (MB): peak = 5006.895 ; gain = 1104.250 ; free physical = 24180 ; free virtual = 40806 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'FIFO_209b_512'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:54] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay2'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1714] 112 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 5731.949 ; gain = 0.000 ; free physical = 23493 ; free virtual = 40119 INFO: [Project 1-111] Unisim Transformation Summary: A total of 66 instances were transformed. OBUFDS => OBUFDS: 66 instances 35 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:47 ; elapsed = 00:01:58 . Memory (MB): peak = 5731.949 ; gain = 3947.465 ; free physical = 23493 ; free virtual = 40119 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5739.953 ; gain = 0.000 ; free physical = 23491 ; free virtual = 40118 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 244132938 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 5898.953 ; gain = 159.000 ; free physical = 23288 ; free virtual = 39915 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 244132938 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.47 . Memory (MB): peak = 6255.719 ; gain = 0.000 ; free physical = 22949 ; free virtual = 39576 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 244132938 Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.61 . Memory (MB): peak = 6255.719 ; gain = 0.000 ; free physical = 22949 ; free virtual = 39576 Phase 1 Initialization | Checksum: 244132938 Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.66 . Memory (MB): peak = 6255.719 ; gain = 0.000 ; free physical = 22949 ; free virtual = 39576 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 244132938 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 6255.719 ; gain = 0.000 ; free physical = 22936 ; free virtual = 39563 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 244132938 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6455.719 ; gain = 200.000 ; free physical = 22794 ; free virtual = 39421 Phase 2 Timer Update And Timing Data Collection | Checksum: 244132938 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6455.719 ; gain = 200.000 ; free physical = 22794 ; free virtual = 39421 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 28 inverters resulting in an inversion of 128 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1d7220810 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 6455.719 ; gain = 200.000 ; free physical = 22792 ; free virtual = 39419 Retarget | Checksum: 1d7220810 INFO: [Opt 31-389] Phase Retarget created 159 cells and removed 562 cells INFO: [Opt 31-1021] In phase Retarget, 225 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 24e18869b Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 6455.719 ; gain = 200.000 ; free physical = 22790 ; free virtual = 39417 Constant propagation | Checksum: 24e18869b INFO: [Opt 31-389] Phase Constant propagation created 38 cells and removed 177 cells INFO: [Opt 31-1021] In phase Constant propagation, 157 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6455.719 ; gain = 0.000 ; free physical = 22788 ; free virtual = 39415 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 6455.719 ; gain = 0.000 ; free physical = 22786 ; free virtual = 39413 Phase 5 Sweep | Checksum: 1e8e97f84 Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 6455.719 ; gain = 200.000 ; free physical = 22786 ; free virtual = 39413 Sweep | Checksum: 1e8e97f84 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3377 cells INFO: [Opt 31-1021] In phase Sweep, 900 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 1aa9d1f14 Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22786 ; free virtual = 39413 BUFG optimization | Checksum: 1aa9d1f14 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1aa9d1f14 Time (s): cpu = 00:00:32 ; elapsed = 00:00:29 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22786 ; free virtual = 39413 Shift Register Optimization | Checksum: 1aa9d1f14 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 18dc95e86 Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22786 ; free virtual = 39413 Post Processing Netlist | Checksum: 18dc95e86 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 300 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1e2d0e31f Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22794 ; free virtual = 39422 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.56 . Memory (MB): peak = 6487.734 ; gain = 0.000 ; free physical = 22802 ; free virtual = 39429 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1e2d0e31f Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22802 ; free virtual = 39429 Phase 9 Finalization | Checksum: 1e2d0e31f Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22802 ; free virtual = 39429 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 159 | 562 | 225 | | Constant propagation | 38 | 177 | 157 | | Sweep | 0 | 3377 | 900 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 300 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1e2d0e31f Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 6487.734 ; gain = 232.016 ; free physical = 22802 ; free virtual = 39429 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 788 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 97 newly gated: 186 Total Ports: 1576 Ending PowerOpt Patch Enables Task | Checksum: 13aea16e2 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19809 ; free virtual = 36441 Ending Power Optimization Task | Checksum: 13aea16e2 Time (s): cpu = 00:02:17 ; elapsed = 00:01:46 . Memory (MB): peak = 9575.465 ; gain = 3087.730 ; free physical = 19809 ; free virtual = 36441 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 164f392a8 Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19749 ; free virtual = 36382 Ending Final Cleanup Task | Checksum: 164f392a8 Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19749 ; free virtual = 36382 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19749 ; free virtual = 36382 Ending Netlist Obfuscation Task | Checksum: 164f392a8 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19749 ; free virtual = 36382 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:02 ; elapsed = 00:03:30 . Memory (MB): peak = 9575.465 ; gain = 3843.516 ; free physical = 19749 ; free virtual = 36382 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.3/efex_processor.3.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19744 ; free virtual = 36377 generate_parallel_reports: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19744 ; free virtual = 36377 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.44 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19366 ; free virtual = 36358 Wrote PlaceDB: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19358 ; free virtual = 36352 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19358 ; free virtual = 36352 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.51 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19357 ; free virtual = 36352 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19357 ; free virtual = 36352 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19357 ; free virtual = 36353 Write Physdb Complete: Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.61 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19357 ; free virtual = 36353 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.3/efex_processor.3.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19537 ; free virtual = 36248 Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19613 ; free virtual = 36325 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f64e0311 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19613 ; free virtual = 36325 Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19613 ; free virtual = 36325 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1094fcf75 Time (s): cpu = 00:01:00 ; elapsed = 00:01:00 . Memory (MB): peak = 9575.465 ; gain = 0.000 ; free physical = 19644 ; free virtual = 36356 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 18c8ccbe9 Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19597 ; free virtual = 36309 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 18c8ccbe9 Time (s): cpu = 00:02:06 ; elapsed = 00:02:07 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19597 ; free virtual = 36309 Phase 1 Placer Initialization | Checksum: 18c8ccbe9 Time (s): cpu = 00:02:07 ; elapsed = 00:02:08 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36309 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1bb0eb93c Time (s): cpu = 00:02:31 ; elapsed = 00:02:32 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19603 ; free virtual = 36316 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1bd493e8b Time (s): cpu = 00:02:51 ; elapsed = 00:02:51 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19606 ; free virtual = 36319 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 249eceeca Time (s): cpu = 00:02:51 ; elapsed = 00:02:52 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19612 ; free virtual = 36325 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1a9e3056f Time (s): cpu = 00:05:55 ; elapsed = 00:05:56 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19603 ; free virtual = 36317 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 22afda383 Time (s): cpu = 00:06:19 ; elapsed = 00:06:20 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36310 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 45 LUTNM shape to break, 14341 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 33, two critical 12, total 45, new lutff created 3 INFO: [Physopt 32-1138] End 1 Pass. Optimized 6901 nets or LUTs. Breaked 45 LUTs, combined 6856 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-1408] Pass 1. Identified 20 candidate nets for high-fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg_n_1_[10]. Replicated 10 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/IN_Load. Replicated 74 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 68 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start. Replicated 31 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 11 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 10 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 8 times. INFO: [Physopt 32-232] Optimized 20 nets. Created 306 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 20 nets or cells. Created 306 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19596 ; free virtual = 36310 INFO: [Physopt 32-76] Pass 1. Identified 30 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[10]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[8]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[15]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[3]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[14]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[9]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[11]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[5]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[13]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1063[12]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1064[14]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1064[8]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1052[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1064[10]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-232] Optimized 30 nets. Created 254 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 30 nets or cells. Created 254 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.6 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 INFO: [Physopt 32-46] Identified 16 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[2]_rep_n_1. Replicated 4 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[8]_rep_n_1. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[9]_rep_n_1. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[7]_rep_n_1. Replicated 1 times. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[3]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[4] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[8] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[0]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[7] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[9] was not replicated. INFO: [Physopt 32-232] Optimized 4 nets. Created 7 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 4 nets or cells. Created 7 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 INFO: [Physopt 32-457] Pass 1. Identified 9 candidate cells for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[1].SPEED.FASTMULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.reg_mult.m_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 16 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU_BDT/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 16 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 8 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 9 nets or cells. Created 120 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1402] Pass 1: Identified 47 candidate cells for Shift Register optimization. INFO: [Physopt 32-775] End 1 Pass. Optimized 38 nets or cells. Created 59 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 INFO: [Physopt 32-527] Pass 1: Identified 1 candidate cell for BRAM register optimization INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. 32 registers were pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 32 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.42 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19595 ; free virtual = 36310 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 45 | 6856 | 6901 | 0 | 1 | 00:00:07 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 306 | 0 | 20 | 0 | 1 | 00:00:09 | | Fanout | 254 | 0 | 30 | 0 | 1 | 00:00:03 | | Critical Cell | 7 | 0 | 4 | 0 | 1 | 00:00:00 | | DSP Register | 120 | 0 | 9 | 0 | 1 | 00:00:01 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 59 | 0 | 38 | 0 | 1 | 00:00:01 | | BRAM Register | 32 | 0 | 1 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 823 | 6856 | 7003 | 0 | 12 | 00:00:21 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1c7b201f3 Time (s): cpu = 00:07:07 ; elapsed = 00:07:09 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36311 Phase 2.5 Global Place Phase2 | Checksum: 172bd94d2 Time (s): cpu = 00:07:18 ; elapsed = 00:07:20 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19595 ; free virtual = 36309 Phase 2 Global Placement | Checksum: 172bd94d2 Time (s): cpu = 00:07:18 ; elapsed = 00:07:20 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19593 ; free virtual = 36308 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 220be1f01 Time (s): cpu = 00:07:42 ; elapsed = 00:07:44 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19595 ; free virtual = 36310 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1827043c1 Time (s): cpu = 00:08:34 ; elapsed = 00:08:36 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36312 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ba120e74 Time (s): cpu = 00:08:38 ; elapsed = 00:08:40 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19603 ; free virtual = 36318 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f7445a4c Time (s): cpu = 00:08:39 ; elapsed = 00:08:41 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19603 ; free virtual = 36318 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 19737a7be Time (s): cpu = 00:09:39 ; elapsed = 00:09:41 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19610 ; free virtual = 36326 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 1b55b7e13 Time (s): cpu = 00:11:26 ; elapsed = 00:11:28 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19598 ; free virtual = 36316 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 14d56d2e6 Time (s): cpu = 00:11:38 ; elapsed = 00:11:40 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19603 ; free virtual = 36321 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 2569e0e9e Time (s): cpu = 00:11:42 ; elapsed = 00:11:44 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19602 ; free virtual = 36320 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 265972f1c Time (s): cpu = 00:13:07 ; elapsed = 00:13:10 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19601 ; free virtual = 36320 Phase 3 Detail Placement | Checksum: 265972f1c Time (s): cpu = 00:13:10 ; elapsed = 00:13:12 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19607 ; free virtual = 36326 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 177ed480a Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.520 | TNS=-8.402 | Phase 1 Physical Synthesis Initialization | Checksum: 1742cb0ad Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19608 ; free virtual = 36327 INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 23bfa3456 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19607 ; free virtual = 36326 Phase 4.1.1.1 BUFG Insertion | Checksum: 177ed480a Time (s): cpu = 00:15:01 ; elapsed = 00:15:04 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19607 ; free virtual = 36326 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.046. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 12b83c1e7 Time (s): cpu = 00:16:58 ; elapsed = 00:17:02 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19594 ; free virtual = 36315 Time (s): cpu = 00:16:58 ; elapsed = 00:17:02 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19594 ; free virtual = 36315 Phase 4.1 Post Commit Optimization | Checksum: 12b83c1e7 Time (s): cpu = 00:17:01 ; elapsed = 00:17:04 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19593 ; free virtual = 36314 Post Placement Optimization Initialization | Checksum: 1cf536ad5 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.293 | TNS=-2.044 | Phase 1 Physical Synthesis Initialization | Checksum: 185d6e2e4 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19592 ; free virtual = 36315 INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 281b624ea Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19594 ; free virtual = 36318 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.046. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1be2a0c0f Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.046 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1b55ecf45 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19590 ; free virtual = 36315 INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/SR[0], BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 3 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 3, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 24104d9c3 Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19586 ; free virtual = 36310 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.046. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1c4b320c8 Time (s): cpu = 00:24:54 ; elapsed = 00:24:59 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19597 ; free virtual = 36322 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 8x8| 8x8| |___________|___________________|___________________| | South| 32x32| 8x8| |___________|___________________|___________________| | East| 32x32| 4x4| |___________|___________________|___________________| | West| 8x8| 16x16| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1c4b320c8 Time (s): cpu = 00:24:57 ; elapsed = 00:25:02 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19597 ; free virtual = 36322 Phase 4.3 Placer Reporting | Checksum: 1c4b320c8 Time (s): cpu = 00:24:59 ; elapsed = 00:25:04 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19597 ; free virtual = 36322 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19597 ; free virtual = 36322 Time (s): cpu = 00:24:59 ; elapsed = 00:25:04 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19597 ; free virtual = 36322 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21c64e377 Time (s): cpu = 00:25:02 ; elapsed = 00:25:07 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36321 Ending Placer Task | Checksum: 1a7895853 Time (s): cpu = 00:25:04 ; elapsed = 00:25:09 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36321 208 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:25:22 ; elapsed = 00:25:27 . Memory (MB): peak = 9583.465 ; gain = 8.000 ; free physical = 19596 ; free virtual = 36321 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.67 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19579 ; free virtual = 36304 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:01 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19552 ; free virtual = 36279 generate_parallel_reports: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19552 ; free virtual = 36279 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.73 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19185 ; free virtual = 36293 Wrote PlaceDB: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18910 ; free virtual = 36305 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18910 ; free virtual = 36305 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.52 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18910 ; free virtual = 36305 Wrote Netlist Cache: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.32 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18881 ; free virtual = 36305 Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18881 ; free virtual = 36306 Write Physdb Complete: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18881 ; free virtual = 36306 report_design_analysis: Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18868 ; free virtual = 36296 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.3/efex_processor.3.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:12 ; elapsed = 00:01:16 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19462 ; free virtual = 36302 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Starting Initial Update Timing Task Time (s): cpu = 00:01:03 ; elapsed = 00:01:04 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19471 ; free virtual = 36311 INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.046 | TNS= 0.000 | INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 219 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:05 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19471 ; free virtual = 36311 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.69 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19081 ; free virtual = 36301 Wrote PlaceDB: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18798 ; free virtual = 36305 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18798 ; free virtual = 36305 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.51 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18798 ; free virtual = 36305 Wrote Netlist Cache: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.3 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18767 ; free virtual = 36304 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18767 ; free virtual = 36306 Write Physdb Complete: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 18767 ; free virtual = 36305 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.3/efex_processor.3.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19242 ; free virtual = 36194 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: a6d3cf56 ConstDB: 0 ShapeSum: ad90d76a RouteDB: 5324b193 Post Restoration Checksum: NetGraph: 6d51642 | NumContArr: 929e9854 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 21ec5a3d0 Time (s): cpu = 00:01:56 ; elapsed = 00:01:57 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19352 ; free virtual = 36306 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 21ec5a3d0 Time (s): cpu = 00:01:59 ; elapsed = 00:01:59 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19354 ; free virtual = 36307 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 21ec5a3d0 Time (s): cpu = 00:02:00 ; elapsed = 00:02:01 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19354 ; free virtual = 36307 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2bfacde3f Time (s): cpu = 00:03:54 ; elapsed = 00:03:54 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19359 ; free virtual = 36314 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.122 | TNS=-0.459 | WHS=-0.506 | THS=-11100.086| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 31e584921 Time (s): cpu = 00:05:13 ; elapsed = 00:05:14 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19365 ; free virtual = 36321 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.122 | TNS=-0.241 | WHS=-0.546 | THS=-3191.858| Phase 2.4 Update Timing for Bus Skew | Checksum: 243dbc9d1 Time (s): cpu = 00:05:14 ; elapsed = 00:05:15 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19364 ; free virtual = 36320 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 9.83014e-06 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 405471 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 405469 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2926440da Time (s): cpu = 00:05:19 ; elapsed = 00:05:20 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19364 ; free virtual = 36319 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2926440da Time (s): cpu = 00:05:19 ; elapsed = 00:05:20 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19364 ; free virtual = 36319 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 24325040e Time (s): cpu = 00:07:27 ; elapsed = 00:07:28 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19346 ; free virtual = 36303 Phase 4 Initial Routing | Checksum: 24325040e Time (s): cpu = 00:07:28 ; elapsed = 00:07:29 . Memory (MB): peak = 9583.465 ; gain = 0.000 ; free physical = 19346 ; free virtual = 36302 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 36257 Number of Nodes with overlaps = 2862 Number of Nodes with overlaps = 588 Number of Nodes with overlaps = 131 Number of Nodes with overlaps = 27 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.029 | TNS=-0.029 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 1582b0615 Time (s): cpu = 00:13:19 ; elapsed = 00:13:21 . Memory (MB): peak = 9843.684 ; gain = 260.219 ; free physical = 19093 ; free virtual = 36051 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 1880 Number of Nodes with overlaps = 324 Number of Nodes with overlaps = 124 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.014 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 2b2a1780d Time (s): cpu = 00:14:49 ; elapsed = 00:14:52 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19072 ; free virtual = 36031 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 1302 Number of Nodes with overlaps = 188 Number of Nodes with overlaps = 68 Number of Nodes with overlaps = 46 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.006 | WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 2474274c8 Time (s): cpu = 00:16:28 ; elapsed = 00:16:30 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36038 Phase 5 Rip-up And Reroute | Checksum: 2474274c8 Time (s): cpu = 00:16:29 ; elapsed = 00:16:31 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36038 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 26b93eeb9 Time (s): cpu = 00:16:53 ; elapsed = 00:16:56 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36038 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.006 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 6.1 Delay CleanUp | Checksum: 27349ac02 Time (s): cpu = 00:16:57 ; elapsed = 00:17:00 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36037 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 27349ac02 Time (s): cpu = 00:16:58 ; elapsed = 00:17:01 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36037 Phase 6 Delay and Skew Optimization | Checksum: 27349ac02 Time (s): cpu = 00:16:59 ; elapsed = 00:17:01 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36037 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.006 | WHS=0.013 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 20fba8a85 Time (s): cpu = 00:17:26 ; elapsed = 00:17:29 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19074 ; free virtual = 36034 Phase 7 Post Hold Fix | Checksum: 20fba8a85 Time (s): cpu = 00:17:27 ; elapsed = 00:17:30 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19074 ; free virtual = 36034 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 2183a1933 Time (s): cpu = 00:18:05 ; elapsed = 00:18:08 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19074 ; free virtual = 36034 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.006 | TNS=-0.006 | WHS=0.013 | THS=0.000 | Phase 8 Timing Verification | Checksum: 2183a1933 Time (s): cpu = 00:18:06 ; elapsed = 00:18:09 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19074 ; free virtual = 36034 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 26.2962 % Global Horizontal Routing Utilization = 26.7304 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 8x8 Area, Max Cong = 89.71%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X56Y364 -> INT_R_X63Y371 INT_L_X56Y356 -> INT_R_X63Y363 South Dir 2x2 Area, Max Cong = 88.5135%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X42Y278 -> INT_R_X43Y279 INT_L_X46Y250 -> INT_R_X47Y251 East Dir 8x8 Area, Max Cong = 91.3833%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X112Y340 -> INT_R_X119Y347 INT_L_X104Y332 -> INT_R_X111Y339 INT_L_X112Y332 -> INT_R_X119Y339 INT_L_X104Y324 -> INT_R_X111Y331 INT_L_X112Y324 -> INT_R_X119Y331 West Dir 2x2 Area, Max Cong = 89.3382%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X16Y368 -> INT_R_X17Y369 INT_L_X62Y362 -> INT_R_X63Y363 INT_L_X64Y360 -> INT_R_X65Y361 INT_L_X64Y354 -> INT_R_X65Y355 INT_L_X16Y330 -> INT_R_X17Y331 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 2 Effective congestion level: 4 Aspect Ratio: 0.666667 Sparse Ratio: 1.0625 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 0.5 Sparse Ratio: 0.5625 Direction: East ---------------- Congested clusters found at Level 2 Effective congestion level: 4 Aspect Ratio: 0.416667 Sparse Ratio: 2.5625 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 2 Aspect Ratio: 1 Sparse Ratio: 2.125 Phase 9 Route finalize | Checksum: 2183a1933 Time (s): cpu = 00:18:08 ; elapsed = 00:18:11 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19073 ; free virtual = 36034 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 2183a1933 Time (s): cpu = 00:18:10 ; elapsed = 00:18:12 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19072 ; free virtual = 36033 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 1fba11d9f Time (s): cpu = 00:18:34 ; elapsed = 00:18:37 . Memory (MB): peak = 9860.051 ; gain = 276.586 ; free physical = 19078 ; free virtual = 36038 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9860.051 ; gain = 0.000 ; free physical = 19078 ; free virtual = 36038 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.154. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 1471c5473 Time (s): cpu = 00:03:20 ; elapsed = 00:03:21 . Memory (MB): peak = 10462.512 ; gain = 602.461 ; free physical = 18555 ; free virtual = 35449 Phase 12 Incr Placement Change | Checksum: 1471c5473 Time (s): cpu = 00:22:02 ; elapsed = 00:22:06 . Memory (MB): peak = 10462.512 ; gain = 879.047 ; free physical = 18553 ; free virtual = 35446 Phase 13 Build RT Design Checksum: PlaceDB: 9b15ee1a ConstDB: 0 ShapeSum: 3bc154 RouteDB: abcaa505 Post Restoration Checksum: NetGraph: 77cc154a | NumContArr: e718be3f | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 13 Build RT Design | Checksum: 2e436c8c3 Time (s): cpu = 00:23:20 ; elapsed = 00:23:24 . Memory (MB): peak = 10462.512 ; gain = 879.047 ; free physical = 18547 ; free virtual = 35442 Phase 14 Router Initialization Phase 14.1 Fix Topology Constraints Phase 14.1 Fix Topology Constraints | Checksum: 2e436c8c3 Time (s): cpu = 00:23:23 ; elapsed = 00:23:27 . Memory (MB): peak = 10462.512 ; gain = 879.047 ; free physical = 18550 ; free virtual = 35444 Phase 14.2 Pre Route Cleanup Phase 14.2 Pre Route Cleanup | Checksum: 2c706b3c4 Time (s): cpu = 00:23:26 ; elapsed = 00:23:29 . Memory (MB): peak = 10462.512 ; gain = 879.047 ; free physical = 18562 ; free virtual = 35457 Number of Nodes with overlaps = 0 Phase 14.3 Update Timing Phase 14.3 Update Timing | Checksum: 1ef614890 Time (s): cpu = 00:25:28 ; elapsed = 00:25:32 . Memory (MB): peak = 10462.512 ; gain = 879.047 ; free physical = 18538 ; free virtual = 35433 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.134 | TNS=0.000 | WHS=-0.506 | THS=-11027.946| Phase 14.4 Update Timing for Bus Skew Phase 14.4.1 Update Timing Phase 14.4.1 Update Timing | Checksum: 2546cb6d9 Time (s): cpu = 00:26:37 ; elapsed = 00:26:41 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18508 ; free virtual = 35404 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.134 | TNS=0.000 | WHS=-0.325 | THS=-1.635 | Phase 14.4 Update Timing for Bus Skew | Checksum: 1e591202a Time (s): cpu = 00:26:38 ; elapsed = 00:26:42 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18508 ; free virtual = 35404 Router Utilization Summary Global Vertical Routing Utilization = 26.2397 % Global Horizontal Routing Utilization = 26.6907 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 649 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 438 Number of Partially Routed Nets = 211 Number of Node Overlaps = 0 Phase 14 Router Initialization | Checksum: 246ba7268 Time (s): cpu = 00:26:43 ; elapsed = 00:26:47 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18512 ; free virtual = 35408 Phase 15 Global Routing Phase 15 Global Routing | Checksum: 246ba7268 Time (s): cpu = 00:26:44 ; elapsed = 00:26:48 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18512 ; free virtual = 35408 Phase 16 Initial Routing Phase 16.1 Initial Net Routing Pass Phase 16.1 Initial Net Routing Pass | Checksum: 26fd87b39 Time (s): cpu = 00:26:49 ; elapsed = 00:26:53 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18514 ; free virtual = 35410 Phase 16 Initial Routing | Checksum: 26fd87b39 Time (s): cpu = 00:26:50 ; elapsed = 00:26:54 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18514 ; free virtual = 35409 Phase 17 Rip-up And Reroute Phase 17.1 Global Iteration 0 Number of Nodes with overlaps = 1712 Number of Nodes with overlaps = 641 Number of Nodes with overlaps = 315 Number of Nodes with overlaps = 157 Number of Nodes with overlaps = 94 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.091 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 17.1 Global Iteration 0 | Checksum: 1d0a449e2 Time (s): cpu = 00:29:16 ; elapsed = 00:29:20 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18514 ; free virtual = 35411 Phase 17 Rip-up And Reroute | Checksum: 1d0a449e2 Time (s): cpu = 00:29:16 ; elapsed = 00:29:21 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18514 ; free virtual = 35411 Phase 18 Delay and Skew Optimization Phase 18.1 Delay CleanUp Phase 18.1.1 Update Timing Phase 18.1.1 Update Timing | Checksum: 207c06f36 Time (s): cpu = 00:29:42 ; elapsed = 00:29:46 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18522 ; free virtual = 35419 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.104 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18.1 Delay CleanUp | Checksum: 1d9bad93b Time (s): cpu = 00:29:43 ; elapsed = 00:29:47 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18522 ; free virtual = 35419 Phase 18.2 Clock Skew Optimization Phase 18.2 Clock Skew Optimization | Checksum: 1d9bad93b Time (s): cpu = 00:29:44 ; elapsed = 00:29:48 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18521 ; free virtual = 35419 Phase 18 Delay and Skew Optimization | Checksum: 1d9bad93b Time (s): cpu = 00:29:44 ; elapsed = 00:29:49 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18521 ; free virtual = 35419 Phase 19 Post Hold Fix Phase 19.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.104 | TNS=0.000 | WHS=0.013 | THS=0.000 | Phase 19.1 Hold Fix Iter | Checksum: 251b64232 Time (s): cpu = 00:30:13 ; elapsed = 00:30:17 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18514 ; free virtual = 35412 Phase 19 Post Hold Fix | Checksum: 251b64232 Time (s): cpu = 00:30:14 ; elapsed = 00:30:18 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18514 ; free virtual = 35412 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 21cf3475d Time (s): cpu = 00:30:52 ; elapsed = 00:30:56 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18507 ; free virtual = 35406 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.104 | TNS=0.000 | WHS=0.013 | THS=0.000 | Phase 20 Timing Verification | Checksum: 21cf3475d Time (s): cpu = 00:30:53 ; elapsed = 00:30:57 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18507 ; free virtual = 35406 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 26.4129 % Global Horizontal Routing Utilization = 26.7566 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 21 Route finalize | Checksum: 21cf3475d Time (s): cpu = 00:30:55 ; elapsed = 00:30:59 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18506 ; free virtual = 35405 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 21cf3475d Time (s): cpu = 00:30:56 ; elapsed = 00:31:00 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18506 ; free virtual = 35405 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 1b076482f Time (s): cpu = 00:31:20 ; elapsed = 00:31:25 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18501 ; free virtual = 35400 Phase 24 Post Process Routing Phase 24 Post Process Routing | Checksum: 1b076482f Time (s): cpu = 00:31:22 ; elapsed = 00:31:26 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18501 ; free virtual = 35400 Phase 25 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.105 | TNS=0.000 | WHS=0.014 | THS=0.000 | Phase 25 Post Router Timing | Checksum: 22796e82b Time (s): cpu = 00:32:48 ; elapsed = 00:32:52 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18502 ; free virtual = 35402 INFO: [Route 35-61] The design met the timing requirement. Total Elapsed time in route_design: 1972.53 secs Phase 26 Post-Route Event Processing Phase 26 Post-Route Event Processing | Checksum: 139cfbcb6 Time (s): cpu = 00:32:51 ; elapsed = 00:32:55 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18503 ; free virtual = 35403 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 139cfbcb6 Time (s): cpu = 00:32:56 ; elapsed = 00:33:00 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18501 ; free virtual = 35401 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 242 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:32:59 ; elapsed = 00:33:03 . Memory (MB): peak = 10485.512 ; gain = 902.047 ; free physical = 18502 ; free virtual = 35402 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx Command: report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.3/efex_processor.3.runs/impl_1/top_efex_processor_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:05 ; elapsed = 00:01:05 . Memory (MB): peak = 10485.512 ; gain = 0.000 ; free physical = 18482 ; free virtual = 35386 INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx Command: report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.3/efex_processor.3.runs/impl_1/top_efex_processor_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:35 ; elapsed = 00:02:36 . Memory (MB): peak = 10485.512 ; gain = 0.000 ; free physical = 18484 ; free virtual = 35389 INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_processor_timing_summary_routed.rpt -pb top_efex_processor_timing_summary_routed.pb -rpx top_efex_processor_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:01:25 ; elapsed = 00:01:27 . Memory (MB): peak = 10485.512 ; gain = 0.000 ; free physical = 18384 ; free virtual = 35375 INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_processor_timing_summary_routed_1.rpt -pb top_efex_processor_timing_summary_routed_1.pb -rpx top_efex_processor_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 10485.512 ; gain = 0.000 ; free physical = 18380 ; free virtual = 35373 INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_processor_route_status.rpt -pb top_efex_processor_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_processor_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_processor_bus_skew_routed.rpt -pb top_efex_processor_bus_skew_routed.pb -rpx top_efex_processor_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx Command: report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 261 Infos, 9 Warnings, 3 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:11 ; elapsed = 00:00:53 . Memory (MB): peak = 10685.516 ; gain = 200.004 ; free physical = 18297 ; free virtual = 35311 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_processor_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 10685.516 ; gain = 0.000 ; free physical = 18296 ; free virtual = 35310 generate_parallel_reports: Time (s): cpu = 00:07:00 ; elapsed = 00:06:47 . Memory (MB): peak = 10685.516 ; gain = 200.004 ; free physical = 18296 ; free virtual = 35310 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.3... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.3 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.1-3E3F3FD INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_processor.3 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.3 clean. INFO: [Hog:Msg-0] The git SHA value 3e3f3fd will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_processor.3... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.3 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.1-3E3F3FD INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_processor.3-v1.7.1-3E3F3FD... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 10685.516 ; gain = 0.000 ; free physical = 18267 ; free virtual = 35289