*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Wed Apr 2 16:56:48 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_control.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1767.219 ; gain = 171.805 ; free physical = 1816 ; free virtual = 11939 Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2234.625 ; gain = 0.000 ; free physical = 1362 ; free virtual = 11485 INFO: [Netlist 29-17] Analyzing 330 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:54] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_only_control.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports mii_tx_clk]'. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:57] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:57] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports mii_tx_clk]'. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:59] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:59] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1714] 6 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 30 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3080.918 ; gain = 0.000 ; free physical = 673 ; free virtual = 10808 INFO: [Project 1-111] Unisim Transformation Summary: A total of 49 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 19 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3080.918 ; gain = 1279.879 ; free physical = 673 ; free virtual = 10808 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3080.918 ; gain = 0.000 ; free physical = 668 ; free virtual = 10804 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3080.918 ; gain = 0.000 ; free physical = 656 ; free virtual = 10792 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 1 Initialization | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 2 Timer Update And Timing Data Collection | Checksum: e70c6ae5 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.26 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 24 inverters resulting in an inversion of 382 pins INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 18e87f74f Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.4 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Retarget | Checksum: 18e87f74f INFO: [Opt 31-389] Phase Retarget created 45 cells and removed 347 cells INFO: [Opt 31-1021] In phase Retarget, 184 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 14115f084 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.49 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Constant propagation | Checksum: 14115f084 INFO: [Opt 31-389] Phase Constant propagation created 158 cells and removed 438 cells INFO: [Opt 31-1021] In phase Constant propagation, 182 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 5 Sweep | Checksum: 181d76973 Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.59 . Memory (MB): peak = 3383.902 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Sweep | Checksum: 181d76973 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 234 cells INFO: [Opt 31-1021] In phase Sweep, 309 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 13b5bd573 Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.65 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 BUFG optimization | Checksum: 13b5bd573 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 13b5bd573 Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.66 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 Shift Register Optimization | Checksum: 13b5bd573 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: ab7be977 Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 Post Processing Netlist | Checksum: ab7be977 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 183 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1e5f8772b Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.8 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3415.918 ; gain = 0.000 ; free physical = 334 ; free virtual = 10470 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1e5f8772b Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.82 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 Phase 9 Finalization | Checksum: 1e5f8772b Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.82 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 45 | 347 | 184 | | Constant propagation | 158 | 438 | 182 | | Sweep | 6 | 234 | 309 | | BUFG optimization | 0 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 183 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1e5f8772b Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.82 . Memory (MB): peak = 3415.918 ; gain = 32.016 ; free physical = 334 ; free virtual = 10470 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 23 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 17 newly gated: 8 Total Ports: 46 Ending PowerOpt Patch Enables Task | Checksum: 18e97b499 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 349 ; free virtual = 10307 Ending Power Optimization Task | Checksum: 18e97b499 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3691.762 ; gain = 275.844 ; free physical = 349 ; free virtual = 10307 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 15a617588 Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 359 ; free virtual = 10317 Ending Final Cleanup Task | Checksum: 15a617588 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 359 ; free virtual = 10317 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 359 ; free virtual = 10317 Ending Netlist Obfuscation Task | Checksum: 15a617588 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 359 ; free virtual = 10317 INFO: [Common 17-83] Releasing license: Implementation 57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3691.762 ; gain = 610.844 ; free physical = 359 ; free virtual = 10317 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 369 ; free virtual = 10331 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 369 ; free virtual = 10332 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 369 ; free virtual = 10332 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 369 ; free virtual = 10332 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 369 ; free virtual = 10332 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 367 ; free virtual = 10332 Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 367 ; free virtual = 10332 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 361 ; free virtual = 10322 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1041c7239 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 361 ; free virtual = 10322 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 361 ; free virtual = 10322 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 176f4af40 Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:00.98 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 361 ; free virtual = 10322 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 165b5c368 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 342 ; free virtual = 10303 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 165b5c368 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 342 ; free virtual = 10303 Phase 1 Placer Initialization | Checksum: 165b5c368 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 342 ; free virtual = 10303 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1237dde64 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 341 ; free virtual = 10302 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 13c99b51e Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 341 ; free virtual = 10302 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 13c99b51e Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 341 ; free virtual = 10302 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1775fcec9 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: ed3826f3 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 531 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 235 nets or LUTs. Breaked 0 LUT, combined 235 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 235 | 235 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 235 | 235 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 233785688 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Phase 2.5 Global Place Phase2 | Checksum: 2894d582f Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Phase 2 Global Placement | Checksum: 2894d582f Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2b76e903f Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 340 ; free virtual = 10301 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 160c60dfb Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 341 ; free virtual = 10302 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1530d74a6 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 341 ; free virtual = 10302 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 173b6eb83 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 341 ; free virtual = 10302 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21e560f57 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 335 ; free virtual = 10296 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 200381536 Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 335 ; free virtual = 10296 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1bebce4fd Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 335 ; free virtual = 10296 Phase 3 Detail Placement | Checksum: 1bebce4fd Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 335 ; free virtual = 10296 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 147b234c8 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.891 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1534b8062 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 334 ; free virtual = 10295 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: f60b4791 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10294 Phase 4.1.1.1 BUFG Insertion | Checksum: 147b234c8 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10294 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.891. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1895f0e82 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Phase 4.1 Post Commit Optimization | Checksum: 1895f0e82 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1895f0e82 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1895f0e82 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Phase 4.3 Placer Reporting | Checksum: 1895f0e82 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 22149c70f Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 Ending Placer Task | Checksum: 137b0fccf Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 88 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 332 ; free virtual = 10293 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 331 ; free virtual = 10293 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 338 ; free virtual = 10300 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 325 ; free virtual = 10292 Wrote PlaceDB: Time (s): cpu = 00:00:00.29 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 317 ; free virtual = 10292 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 317 ; free virtual = 10292 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 317 ; free virtual = 10292 Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 317 ; free virtual = 10293 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 310 ; free virtual = 10287 Write Physdb Complete: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 310 ; free virtual = 10287 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Starting Initial Update Timing Task Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 309 ; free virtual = 10274 INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.189 | TNS= 0.000 | INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 98 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 310 ; free virtual = 10280 Wrote PlaceDB: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 309 ; free virtual = 10287 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 309 ; free virtual = 10287 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 309 ; free virtual = 10287 Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 308 ; free virtual = 10288 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 308 ; free virtual = 10289 Write Physdb Complete: Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.37 . Memory (MB): peak = 3691.762 ; gain = 0.000 ; free physical = 308 ; free virtual = 10289 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: 285cab30 ConstDB: 0 ShapeSum: ed05451a RouteDB: 224f0c85 Post Restoration Checksum: NetGraph: cc5b18b9 | NumContArr: d0130e6b | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 321c01c5e Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3806.836 ; gain = 115.074 ; free physical = 258 ; free virtual = 10136 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 321c01c5e Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3806.836 ; gain = 115.074 ; free physical = 258 ; free virtual = 10136 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 321c01c5e Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 3806.836 ; gain = 115.074 ; free physical = 258 ; free virtual = 10136 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 1f4d5fa92 Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 226 ; free virtual = 10053 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=-0.264 | THS=-315.713| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 1fc3ff893 Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 225 ; free virtual = 10052 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=-0.106 | THS=-1.785 | Phase 2.4 Update Timing for Bus Skew | Checksum: 1387619fc Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 224 ; free virtual = 10057 Router Utilization Summary Global Vertical Routing Utilization = 2.59626e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 10113 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 10111 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 22677e36c Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 22677e36c Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 2288e6d6e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 225 ; free virtual = 10059 Phase 4 Initial Routing | Checksum: 2288e6d6e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 225 ; free virtual = 10059 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 784 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.804 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 2538d1701 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 233 ; free virtual = 10067 Phase 5 Rip-up And Reroute | Checksum: 2538d1701 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 233 ; free virtual = 10067 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1 Delay CleanUp | Checksum: 2538d1701 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 233 ; free virtual = 10067 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 2538d1701 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 233 ; free virtual = 10067 Phase 6 Delay and Skew Optimization | Checksum: 2538d1701 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 233 ; free virtual = 10067 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.056 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 1b2febe97 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 7 Post Hold Fix | Checksum: 1b2febe97 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.549134 % Global Horizontal Routing Utilization = 0.606649 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 1b2febe97 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 1b2febe97 Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 10ac98b79 Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 10ac98b79 Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 231 ; free virtual = 10066 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.151 | TNS=0.000 | WHS=0.056 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 12 Post Router Timing | Checksum: 10ac98b79 Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 231 ; free virtual = 10066 Total Elapsed time in route_design: 46.63 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 1f60b98e8 Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 1f60b98e8 Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 109 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 3872.938 ; gain = 181.176 ; free physical = 232 ; free virtual = 10066 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_control_drc_routed.rpt -pb top_efex_control_drc_routed.pb -rpx top_efex_control_drc_routed.rpx Command: report_drc -file top_efex_control_drc_routed.rpt -pb top_efex_control_drc_routed.pb -rpx top_efex_control_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_drc_routed.rpt. report_drc completed successfully INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_control_methodology_drc_routed.rpt -pb top_efex_control_methodology_drc_routed.pb -rpx top_efex_control_methodology_drc_routed.rpx Command: report_methodology -file top_efex_control_methodology_drc_routed.rpt -pb top_efex_control_methodology_drc_routed.pb -rpx top_efex_control_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_control/efex_golden_control.runs/impl_1/top_efex_control_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_control_timing_summary_routed.rpt -pb top_efex_control_timing_summary_routed.pb -rpx top_efex_control_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_control_timing_summary_routed_1.rpt -pb top_efex_control_timing_summary_routed_1.pb -rpx top_efex_control_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_control_route_status.rpt -pb top_efex_control_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_control_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_control_bus_skew_routed.rpt -pb top_efex_control_bus_skew_routed.pb -rpx top_efex_control_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_control_power_routed.rpt -pb top_efex_control_power_summary_routed.pb -rpx top_efex_control_power_routed.rpx Command: report_power -file top_efex_control_power_routed.rpt -pb top_efex_control_power_summary_routed.pb -rpx top_efex_control_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 128 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_control_clock_utilization_routed.rpt generate_parallel_reports: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3872.938 ; gain = 0.000 ; free physical = 244 ; free virtual = 10033 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.1-60DBDD4 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_golden_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] The git SHA value 60dbdd4 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.1-60DBDD4 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_control-v1.7.1-60DBDD4... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.