*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Sat Apr 26 19:32:08 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_control.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1766.969 ; gain = 141.836 ; free physical = 5133 ; free virtual = 10978 Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub2_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.output_channel2_ila' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2459.273 ; gain = 0.000 ; free physical = 4446 ; free virtual = 10293 INFO: [Netlist 29-17] Analyzing 6739 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:54] get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3448.160 ; gain = 670.789 ; free physical = 3623 ; free virtual = 9510 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports mii_tx_clk]'. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:57] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:57] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports mii_tx_clk]'. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:59] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:59] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' INFO: [Project 1-1714] 66 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 46 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3484.543 ; gain = 0.000 ; free physical = 3574 ; free virtual = 9462 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:33 . Memory (MB): peak = 3484.543 ; gain = 1639.715 ; free physical = 3574 ; free virtual = 9462 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.84 . Memory (MB): peak = 3484.543 ; gain = 0.000 ; free physical = 3587 ; free virtual = 9476 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1bfe2c2ff Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3484.543 ; gain = 0.000 ; free physical = 3554 ; free virtual = 9443 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1.1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3860.215 ; gain = 0.000 ; free physical = 3927 ; free virtual = 9084 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3860.215 ; gain = 0.000 ; free physical = 3919 ; free virtual = 9076 Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 2098a0e5e Time (s): cpu = 00:01:15 ; elapsed = 00:01:23 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 1.1 Core Generation And Design Setup | Checksum: 2098a0e5e Time (s): cpu = 00:01:15 ; elapsed = 00:01:23 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2098a0e5e Time (s): cpu = 00:01:15 ; elapsed = 00:01:23 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 1 Initialization | Checksum: 2098a0e5e Time (s): cpu = 00:01:15 ; elapsed = 00:01:23 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 2098a0e5e Time (s): cpu = 00:01:17 ; elapsed = 00:01:26 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 2098a0e5e Time (s): cpu = 00:01:17 ; elapsed = 00:01:26 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 2 Timer Update And Timing Data Collection | Checksum: 2098a0e5e Time (s): cpu = 00:01:17 ; elapsed = 00:01:26 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3919 ; free virtual = 9076 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 43 inverters resulting in an inversion of 503 pins INFO: [Opt 31-138] Pushed 13 inverter(s) to 16 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 23fb71439 Time (s): cpu = 00:01:18 ; elapsed = 00:01:27 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3920 ; free virtual = 9077 Retarget | Checksum: 23fb71439 INFO: [Opt 31-389] Phase Retarget created 121 cells and removed 368 cells INFO: [Opt 31-1021] In phase Retarget, 469 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 23905d53d Time (s): cpu = 00:01:19 ; elapsed = 00:01:27 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3923 ; free virtual = 9080 Constant propagation | Checksum: 23905d53d INFO: [Opt 31-389] Phase Constant propagation created 178 cells and removed 624 cells INFO: [Opt 31-1021] In phase Constant propagation, 153 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3860.215 ; gain = 0.000 ; free physical = 3950 ; free virtual = 9107 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3860.215 ; gain = 0.000 ; free physical = 3949 ; free virtual = 9106 Phase 5 Sweep | Checksum: 2186084e4 Time (s): cpu = 00:01:20 ; elapsed = 00:01:29 . Memory (MB): peak = 3860.215 ; gain = 25.781 ; free physical = 3949 ; free virtual = 9106 Sweep | Checksum: 2186084e4 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 743 cells INFO: [Opt 31-1021] In phase Sweep, 4721 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 223fc49f1 Time (s): cpu = 00:01:21 ; elapsed = 00:01:29 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3947 ; free virtual = 9104 BUFG optimization | Checksum: 223fc49f1 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 26cabe0d8 Time (s): cpu = 00:01:21 ; elapsed = 00:01:29 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3947 ; free virtual = 9104 Shift Register Optimization | Checksum: 26cabe0d8 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 2a043309a Time (s): cpu = 00:01:22 ; elapsed = 00:01:30 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3949 ; free virtual = 9106 Post Processing Netlist | Checksum: 2a043309a INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 197a4c947 Time (s): cpu = 00:01:23 ; elapsed = 00:01:31 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3947 ; free virtual = 9104 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3892.230 ; gain = 0.000 ; free physical = 3947 ; free virtual = 9104 Phase 9.2 Verifying Netlist Connectivity | Checksum: 197a4c947 Time (s): cpu = 00:01:23 ; elapsed = 00:01:31 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3947 ; free virtual = 9104 Phase 9 Finalization | Checksum: 197a4c947 Time (s): cpu = 00:01:23 ; elapsed = 00:01:31 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3947 ; free virtual = 9104 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 121 | 368 | 469 | | Constant propagation | 178 | 624 | 153 | | Sweep | 6 | 743 | 4721 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 197a4c947 Time (s): cpu = 00:01:23 ; elapsed = 00:01:31 . Memory (MB): peak = 3892.230 ; gain = 57.797 ; free physical = 3947 ; free virtual = 9104 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 25c213d55 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2971 ; free virtual = 8138 Ending Power Optimization Task | Checksum: 25c213d55 Time (s): cpu = 00:00:41 ; elapsed = 00:00:35 . Memory (MB): peak = 4872.031 ; gain = 979.801 ; free physical = 2971 ; free virtual = 8138 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 1b9575cd9 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2930 ; free virtual = 8137 Ending Final Cleanup Task | Checksum: 1b9575cd9 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2930 ; free virtual = 8137 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2930 ; free virtual = 8137 Ending Netlist Obfuscation Task | Checksum: 1b9575cd9 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2930 ; free virtual = 8137 INFO: [Common 17-83] Releasing license: Implementation 85 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:30 ; elapsed = 00:02:33 . Memory (MB): peak = 4872.031 ; gain = 1387.488 ; free physical = 2930 ; free virtual = 8137 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2925 ; free virtual = 8133 generate_parallel_reports: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2925 ; free virtual = 8133 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2888 ; free virtual = 8145 Wrote PlaceDB: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2880 ; free virtual = 8137 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2880 ; free virtual = 8137 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2880 ; free virtual = 8138 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2880 ; free virtual = 8138 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2880 ; free virtual = 8139 Write Physdb Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2880 ; free virtual = 8139 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8100 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Running DRC as a precondition to command place_design CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block GTHE2_CHANNEL cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt2_MGT_TX_RX_6G4_i/gthe2_i is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems. CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block GTHE2_CHANNEL cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt3_MGT_TX_RX_6G4_i/gthe2_i is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Critical Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2913 ; free virtual = 8143 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12dbf6196 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2913 ; free virtual = 8143 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2913 ; free virtual = 8143 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14fae494b Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2905 ; free virtual = 8143 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 23f1c718a Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2883 ; free virtual = 8123 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 23f1c718a Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2882 ; free virtual = 8123 Phase 1 Placer Initialization | Checksum: 23f1c718a Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2882 ; free virtual = 8123 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 18fed4417 Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8120 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1eaed20bc Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2884 ; free virtual = 8126 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1eaed20bc Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2883 ; free virtual = 8125 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 222505c98 Time (s): cpu = 00:01:27 ; elapsed = 00:01:27 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2888 ; free virtual = 8132 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1f773ea43 Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2887 ; free virtual = 8131 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 51 LUTNM shape to break, 2291 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 43, two critical 8, total 51, new lutff created 4 INFO: [Physopt 32-1138] End 1 Pass. Optimized 911 nets or LUTs. Breaked 51 LUTs, combined 860 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-1408] Pass 1. Identified 2 candidate nets for high-fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 10 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 48 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 58 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 58 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8133 INFO: [Physopt 32-76] Pass 1. Identified 13 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 3 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 3 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-232] Optimized 12 nets. Created 51 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 12 nets or cells. Created 51 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8132 INFO: [Physopt 32-46] Identified 120 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[11]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/write_ptr[5] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/write_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-232] Optimized 1 net. Created 1 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 1 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8132 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 23 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_13. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/Memory_reg_1. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-775] End 1 Pass. Optimized 10 nets or cells. Created 10 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8132 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8133 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 51 | 860 | 911 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 58 | 0 | 2 | 0 | 1 | 00:00:01 | | Fanout | 51 | 0 | 12 | 0 | 1 | 00:00:01 | | Critical Cell | 1 | 0 | 1 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 10 | 0 | 10 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 171 | 860 | 936 | 0 | 11 | 00:00:03 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1ec5caa7c Time (s): cpu = 00:01:44 ; elapsed = 00:01:45 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2878 ; free virtual = 8133 Phase 2.5 Global Place Phase2 | Checksum: 16b53c305 Time (s): cpu = 00:01:47 ; elapsed = 00:01:48 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2879 ; free virtual = 8135 Phase 2 Global Placement | Checksum: 16b53c305 Time (s): cpu = 00:01:47 ; elapsed = 00:01:48 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2879 ; free virtual = 8135 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 11d852620 Time (s): cpu = 00:01:53 ; elapsed = 00:01:54 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2877 ; free virtual = 8133 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1af17a7fb Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2877 ; free virtual = 8133 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1bc8d1c42 Time (s): cpu = 00:02:06 ; elapsed = 00:02:07 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2874 ; free virtual = 8130 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 15c52ad65 Time (s): cpu = 00:02:06 ; elapsed = 00:02:07 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2874 ; free virtual = 8130 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 18f3a821e Time (s): cpu = 00:02:24 ; elapsed = 00:02:25 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2881 ; free virtual = 8137 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 89764f4c Time (s): cpu = 00:02:43 ; elapsed = 00:02:44 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2876 ; free virtual = 8133 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 80cd1c9a Time (s): cpu = 00:02:46 ; elapsed = 00:02:47 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2876 ; free virtual = 8132 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 13834746f Time (s): cpu = 00:02:47 ; elapsed = 00:02:48 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2875 ; free virtual = 8132 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1fb6a3bf1 Time (s): cpu = 00:03:13 ; elapsed = 00:03:14 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2879 ; free virtual = 8136 Phase 3 Detail Placement | Checksum: 1fb6a3bf1 Time (s): cpu = 00:03:13 ; elapsed = 00:03:15 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2879 ; free virtual = 8136 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 2298db81f Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.348 | TNS=-11.855 | Phase 1 Physical Synthesis Initialization | Checksum: 18c3cd8c2 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2855 ; free virtual = 8112 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 2570a3ad8 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2855 ; free virtual = 8112 Phase 4.1.1.1 BUFG Insertion | Checksum: 2298db81f Time (s): cpu = 00:03:40 ; elapsed = 00:03:41 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2855 ; free virtual = 8112 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.110. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 25bb35e31 Time (s): cpu = 00:04:53 ; elapsed = 00:04:55 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2876 ; free virtual = 8134 Time (s): cpu = 00:04:53 ; elapsed = 00:04:55 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2876 ; free virtual = 8134 Phase 4.1 Post Commit Optimization | Checksum: 25bb35e31 Time (s): cpu = 00:04:53 ; elapsed = 00:04:56 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2876 ; free virtual = 8134 Post Placement Optimization Initialization | Checksum: 2bf9d72cb Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.433 | TNS=-31.512 | Phase 1 Physical Synthesis Initialization | Checksum: 206685436 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2881 ; free virtual = 8140 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 272ee7a10 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2881 ; free virtual = 8140 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.110. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 24280b68f Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.110 | TNS=-0.447 | Phase 1 Physical Synthesis Initialization | Checksum: 1a5419918 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2875 ; free virtual = 8136 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 256f878f2 Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8131 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.110. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 28010a624 Time (s): cpu = 00:08:01 ; elapsed = 00:08:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2865 ; free virtual = 8126 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 4x4| 8x8| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 8x8| 2x2| |___________|___________________|___________________| | West| 1x1| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 28010a624 Time (s): cpu = 00:08:02 ; elapsed = 00:08:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2872 ; free virtual = 8133 Phase 4.3 Placer Reporting | Checksum: 28010a624 Time (s): cpu = 00:08:02 ; elapsed = 00:08:05 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8132 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8132 Time (s): cpu = 00:08:02 ; elapsed = 00:08:05 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8132 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1da3dcb48 Time (s): cpu = 00:08:03 ; elapsed = 00:08:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8132 Ending Placer Task | Checksum: 1523c638f Time (s): cpu = 00:08:03 ; elapsed = 00:08:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8132 231 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:08:07 ; elapsed = 00:08:10 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2871 ; free virtual = 8132 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.41 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2851 ; free virtual = 8113 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.5 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2840 ; free virtual = 8103 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2804 ; free virtual = 8119 Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2726 ; free virtual = 8123 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2726 ; free virtual = 8123 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2726 ; free virtual = 8123 Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2719 ; free virtual = 8124 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2719 ; free virtual = 8125 Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2719 ; free virtual = 8125 report_design_analysis: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2720 ; free virtual = 8127 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2804 ; free virtual = 8097 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Starting Initial Update Timing Task Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2846 ; free virtual = 8139 INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 17.56s | WALL: 17.61s Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2846 ; free virtual = 8139 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.110 | TNS=-0.447 | Phase 1 Physical Synthesis Initialization | Checksum: 1832a6ac3 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2854 ; free virtual = 8147 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.110 | TNS=-0.447 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Phase 2 DSP Register Optimization | Checksum: 1832a6ac3 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2854 ; free virtual = 8147 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.110 | TNS=-0.447 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/FULL. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net ttc_clk/inst/clk320_clk_ttc. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/empty. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.094 | TNS=-0.095 | INFO: [Physopt 32-702] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/state_sig[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_merger/ifg_delay_end_reg[1]. Critical path length was reduced through logic transformation on cell GOLDEN_IF.readout_packet_block/tob_merge_B/TOB_merger/FSM_sequential_state_sig[1]_i_1_comp. INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/tob_merge_B/FSM_sequential_state_sig[1]_i_2_n_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.002 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_veto_clk320_reg_0. Re-placed instance GOLDEN_IF.readout_packet_block/ttc_fifos/fifo_delay_start_i_3 INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_veto_clk320_reg_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.001 | TNS=-0.001 | INFO: [Physopt 32-663] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN. Re-placed instance GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_1_comp INFO: [Physopt 32-735] Processed net GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/RD_EN. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 Phase 3 Critical Path Optimization | Checksum: 1832a6ac3 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.008 | TNS=0.000 | Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 Phase 4 Critical Path Optimization | Checksum: 1832a6ac3 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=0.008 | TNS=0.000 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Path | 0.118 | 0.447 | 0 | 0 | 4 | 0 | 2 | 00:00:02 | | Total | 0.118 | 0.447 | 0 | 0 | 4 | 0 | 3 | 00:00:02 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 Ending Physical Synthesis Task | Checksum: 19fd5b362 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 INFO: [Common 17-83] Releasing license: Implementation 265 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2849 ; free virtual = 8143 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2809 ; free virtual = 8152 Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2723 ; free virtual = 8147 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2723 ; free virtual = 8147 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2726 ; free virtual = 8150 Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2714 ; free virtual = 8147 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2714 ; free virtual = 8148 Write Physdb Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2714 ; free virtual = 8148 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2780 ; free virtual = 8103 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: 757fdd2e ConstDB: 0 ShapeSum: b161e0f7 RouteDB: 224f0c85 Post Restoration Checksum: NetGraph: e07d83c7 | NumContArr: 8bc85b98 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2f197d499 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2814 ; free virtual = 8141 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2f197d499 Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2813 ; free virtual = 8140 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2f197d499 Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2813 ; free virtual = 8140 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 269509da2 Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2814 ; free virtual = 8141 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.054 | TNS=-0.239 | WHS=-2.782 | THS=-5039.937| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 2f54f6647 Time (s): cpu = 00:01:38 ; elapsed = 00:01:39 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2810 ; free virtual = 8137 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.054 | TNS=0.000 | WHS=-5.432 | THS=-655.599| Phase 2.4 Update Timing for Bus Skew | Checksum: 2b84b7606 Time (s): cpu = 00:01:38 ; elapsed = 00:01:39 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2803 ; free virtual = 8138 Router Utilization Summary Global Vertical Routing Utilization = 0.000142794 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 102660 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 102658 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 23e5a0b4f Time (s): cpu = 00:01:40 ; elapsed = 00:01:41 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2802 ; free virtual = 8137 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 23e5a0b4f Time (s): cpu = 00:01:40 ; elapsed = 00:01:41 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2802 ; free virtual = 8137 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 28b548853 Time (s): cpu = 00:02:44 ; elapsed = 00:02:45 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2820 ; free virtual = 8155 Phase 4 Initial Routing | Checksum: 28b548853 Time (s): cpu = 00:02:45 ; elapsed = 00:02:45 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2820 ; free virtual = 8155 INFO: [Route 35-580] Design has 24 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+======================================================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+======================================================================+ | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/delay_count_reg[3]/R | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/delay_count_reg[2]/R | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/delay_count_reg[1]/R | +--------------------+-------------------+----------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 8220 Number of Nodes with overlaps = 616 Number of Nodes with overlaps = 122 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.154 | TNS=-4.057 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 27dd744cd Time (s): cpu = 00:03:50 ; elapsed = 00:03:50 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2809 ; free virtual = 8144 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 484 Number of Nodes with overlaps = 52 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.141 | TNS=-0.729 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 1e2ec5e98 Time (s): cpu = 00:04:05 ; elapsed = 00:04:06 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2810 ; free virtual = 8146 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 1233 Number of Nodes with overlaps = 185 Number of Nodes with overlaps = 50 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.036 | TNS=-0.061 | WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 2aef951e9 Time (s): cpu = 00:04:24 ; elapsed = 00:04:25 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2809 ; free virtual = 8145 Phase 5.4 Global Iteration 3 Number of Nodes with overlaps = 779 Number of Nodes with overlaps = 166 Number of Nodes with overlaps = 107 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.036 | TNS=-0.063 | WHS=N/A | THS=N/A | Phase 5.4 Global Iteration 3 | Checksum: 25a28ee30 Time (s): cpu = 00:04:45 ; elapsed = 00:04:46 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2813 ; free virtual = 8149 Phase 5 Rip-up And Reroute | Checksum: 25a28ee30 Time (s): cpu = 00:04:45 ; elapsed = 00:04:46 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2813 ; free virtual = 8149 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 290a40ff5 Time (s): cpu = 00:04:51 ; elapsed = 00:04:52 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8148 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.058 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 6.1 Delay CleanUp | Checksum: 24b83dc94 Time (s): cpu = 00:04:52 ; elapsed = 00:04:53 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8148 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 24b83dc94 Time (s): cpu = 00:04:52 ; elapsed = 00:04:53 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2813 ; free virtual = 8149 Phase 6 Delay and Skew Optimization | Checksum: 24b83dc94 Time (s): cpu = 00:04:52 ; elapsed = 00:04:53 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2811 ; free virtual = 8147 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.058 | TNS=0.000 | WHS=-1.016 | THS=-64.364| Phase 7.1 Hold Fix Iter | Checksum: 1a61340fb Time (s): cpu = 00:05:00 ; elapsed = 00:05:01 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2808 ; free virtual = 8145 Phase 7.2 Non Free Resource Hold Fix Iter Phase 7.2 Non Free Resource Hold Fix Iter | Checksum: 18a4f6bbf Time (s): cpu = 00:05:01 ; elapsed = 00:05:02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2808 ; free virtual = 8144 Phase 7 Post Hold Fix | Checksum: 18a4f6bbf Time (s): cpu = 00:05:01 ; elapsed = 00:05:02 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2808 ; free virtual = 8144 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 1a6546a04 Time (s): cpu = 00:05:10 ; elapsed = 00:05:11 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8149 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.058 | TNS=0.000 | WHS=0.050 | THS=0.000 | Phase 8 Timing Verification | Checksum: 1a6546a04 Time (s): cpu = 00:05:10 ; elapsed = 00:05:11 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8149 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.5118 % Global Horizontal Routing Utilization = 9.98599 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Route finalize | Checksum: 1a6546a04 Time (s): cpu = 00:05:11 ; elapsed = 00:05:12 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8148 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 1a6546a04 Time (s): cpu = 00:05:11 ; elapsed = 00:05:12 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8149 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 207fee3d4 Time (s): cpu = 00:05:17 ; elapsed = 00:05:18 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2810 ; free virtual = 8147 Phase 12 Post Process Routing Phase 12 Post Process Routing | Checksum: 207fee3d4 Time (s): cpu = 00:05:17 ; elapsed = 00:05:19 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2810 ; free virtual = 8146 Phase 13 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.060 | TNS=0.000 | WHS=0.051 | THS=0.000 | Phase 13 Post Router Timing | Checksum: 1f812b7bc Time (s): cpu = 00:05:40 ; elapsed = 00:05:41 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2813 ; free virtual = 8150 INFO: [Route 35-61] The design met the timing requirement. Total Elapsed time in route_design: 341.35 secs Phase 14 Post-Route Event Processing Phase 14 Post-Route Event Processing | Checksum: 13ea985d9 Time (s): cpu = 00:05:41 ; elapsed = 00:05:42 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2812 ; free virtual = 8148 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 13ea985d9 Time (s): cpu = 00:05:42 ; elapsed = 00:05:43 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2811 ; free virtual = 8148 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 285 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:05:43 ; elapsed = 00:05:45 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2811 ; free virtual = 8148 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_control_drc_routed.rpt -pb top_efex_control_drc_routed.pb -rpx top_efex_control_drc_routed.rpx Command: report_drc -file top_efex_control_drc_routed.rpt -pb top_efex_control_drc_routed.pb -rpx top_efex_control_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2792 ; free virtual = 8128 INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_control_methodology_drc_routed.rpt -pb top_efex_control_methodology_drc_routed.pb -rpx top_efex_control_methodology_drc_routed.rpx Command: report_methodology -file top_efex_control_methodology_drc_routed.rpt -pb top_efex_control_methodology_drc_routed.pb -rpx top_efex_control_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2767 ; free virtual = 8104 INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_control_timing_summary_routed.rpt -pb top_efex_control_timing_summary_routed.pb -rpx top_efex_control_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2765 ; free virtual = 8126 INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_control_timing_summary_routed_1.rpt -pb top_efex_control_timing_summary_routed_1.pb -rpx top_efex_control_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2750 ; free virtual = 8114 INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_control_route_status.rpt -pb top_efex_control_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_control_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_control_bus_skew_routed.rpt -pb top_efex_control_bus_skew_routed.pb -rpx top_efex_control_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_control_power_routed.rpt -pb top_efex_control_power_summary_routed.pb -rpx top_efex_control_power_routed.rpx Command: report_power -file top_efex_control_power_routed.rpt -pb top_efex_control_power_summary_routed.pb -rpx top_efex_control_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 304 Infos, 5 Warnings, 2 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2743 ; free virtual = 8121 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_control_clock_utilization_routed.rpt generate_parallel_reports: Time (s): cpu = 00:01:48 ; elapsed = 00:01:46 . Memory (MB): peak = 4872.031 ; gain = 0.000 ; free physical = 2749 ; free virtual = 8128 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.2-B9127B7 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value b9127b7 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.2-B9127B7 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.7.2-B9127B7... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.