*** Running vivado with args -log io_delay2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source io_delay2.tcl ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Sat Apr 26 19:33:36 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source io_delay2.tcl -notrace create_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1767.984 ; gain = 172.805 ; free physical = 24862 ; free virtual = 42905 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: io_delay2 Command: synth_design -top io_delay2 -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 4334 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2685.570 ; gain = 430.703 ; free physical = 23692 ; free virtual = 41735 --------------------------------------------------------------------------------- INFO: [Synth 8-11241] undeclared symbol 'clk_in_int_buf', assumed default net type 'wire' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_selectio_wiz.v:95] INFO: [Synth 8-6157] synthesizing module 'io_delay2' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.v:55] INFO: [Synth 8-6157] synthesizing module 'io_delay2_selectio_wiz' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_selectio_wiz.v:55] Parameter SYS_W bound to: 1 - type: integer Parameter DEV_W bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:75840] Parameter DIFF_TERM bound to: FALSE - type: string Parameter IOSTANDARD bound to: LVDS - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:75840] INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:77934] Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: VAR_LOAD - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: double Parameter SIGNAL_PATTERN bound to: DATA - type: string INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:77934] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:43188] INFO: [Synth 8-6155] done synthesizing module 'FDRE' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:43188] INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:77921] INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:77921] INFO: [Synth 8-6155] done synthesizing module 'io_delay2_selectio_wiz' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_selectio_wiz.v:55] INFO: [Synth 8-6155] done synthesizing module 'io_delay2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.v:55] WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOB_RDOUT_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic TOB_RDOUT_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ALGOLIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ALGOLIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic INFRASTRUCTURE_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic INFRASTRUCTURE_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic USR_IP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic USR_IP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic FLAVOUR --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2759.539 ; gain = 504.672 ; free physical = 23544 ; free virtual = 41588 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2777.352 ; gain = 522.484 ; free physical = 23544 ; free virtual = 41587 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2777.352 ; gain = 522.484 ; free physical = 23544 ; free virtual = 41587 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2783.289 ; gain = 0.000 ; free physical = 23542 ; free virtual = 41585 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_ooc.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2_ooc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/io_delay2_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/io_delay2_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc] for cell 'inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/io_delay2_synth_1/dont_touch.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/io_delay2_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2856.227 ; gain = 0.000 ; free physical = 23531 ; free virtual = 41575 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2856.227 ; gain = 0.000 ; free physical = 23531 ; free virtual = 41575 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2856.227 ; gain = 601.359 ; free physical = 23531 ; free virtual = 41575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2864.230 ; gain = 609.363 ; free physical = 23531 ; free virtual = 41575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/io_delay2_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2864.230 ; gain = 609.363 ; free physical = 23531 ; free virtual = 41575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2864.230 ; gain = 609.363 ; free physical = 23527 ; free virtual = 41572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2864.230 ; gain = 609.363 ; free physical = 23527 ; free virtual = 41572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2931.230 ; gain = 676.363 ; free physical = 23462 ; free virtual = 41506 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2931.230 ; gain = 676.363 ; free physical = 23462 ; free virtual = 41506 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2940.246 ; gain = 685.379 ; free physical = 23454 ; free virtual = 41499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 1| |3 |FDRE | 1| |4 |IBUFDS | 1| +------+-----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.059 ; gain = 847.191 ; free physical = 23314 ; free virtual = 41359 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3102.059 ; gain = 768.316 ; free physical = 23322 ; free virtual = 41366 Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3102.066 ; gain = 847.191 ; free physical = 23322 ; free virtual = 41366 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3102.066 ; gain = 0.000 ; free physical = 23322 ; free virtual = 41366 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3102.066 ; gain = 0.000 ; free physical = 23499 ; free virtual = 41544 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: a6d8d191 INFO: [Common 17-83] Releasing license: Synthesis 32 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 3102.066 ; gain = 1317.238 ; free physical = 23499 ; free virtual = 41544 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2540.304; main = 2307.759; forked = 291.461 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4007.102; main = 3102.062; forked = 931.852 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3126.070 ; gain = 0.000 ; free physical = 23507 ; free virtual = 41551 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/io_delay2_synth_1/io_delay2.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP io_delay2, cache-ID = 672764ff02dc9500 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3182.098 ; gain = 0.000 ; free physical = 23489 ; free virtual = 41533 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_processor.4/efex_processor.4.runs/io_delay2_synth_1/io_delay2.dcp' has been generated. INFO: [Vivado 12-24828] Executing command : report_utilization -file io_delay2_utilization_synth.rpt -pb io_delay2_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 19:34:24 2025...