## efex_processor.4 Synthesis Utilization report


                                                                                                        
| **Site Type**    |    **Used** |   **Fixed** |   **Prohibited** |    **Available** |    **Util%** |   
| ---    |         ---  |        --- |         --- |              ---  |             ---  |             
| Slice  LUTs*     |    191750   |   0         |   0              |    346400        |    55.36     |   
| Slice  Registers |    234224   |   0         |   0              |    692800        |    33.81     |   
| Block  RAM       Tile |        24  |         0   |              0    |             1180 |         2.03
| DSPs   |         0    |        0   |         0   |              2880 |             0.00 |             
| Bonded IOB       |    501      |   0         |   0              |    600           |    83.50     |   
                                                                                                        
## efex_processor.4 Implementation Utilization report


                                                                                                           
| **Site Type**    |    **Used** |     **Fixed** |   **Prohibited** |    **Available** |    **Util%** |    
| ---    |         ---  |        ---   |         --- |              ---  |             ---  |              
| Slice  LUTs      |    199162   |     0         |   0              |    346400        |    57.49     |    
| Slice  Registers |    258956   |     0         |   0              |    692800        |    37.38     |    
| Block  RAM       Tile |        747.5 |         0   |              0    |             1180 |         63.35
| DSPs   |         96   |        0     |         0   |              2880 |             3.33 |              
| Bonded IOB       |    251      |     249       |   0              |    600           |    41.83     |