*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Sat Apr 26 19:20:12 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1767.609 ; gain = 141.836 ; free physical = 2460 ; free virtual = 12580 Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2261.297 ; gain = 0.000 ; free physical = 1958 ; free virtual = 12078 INFO: [Netlist 29-17] Analyzing 155 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[0].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[0].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[1].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[1].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[2].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[2].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'DIFF_TERM' constraint because cell 'input_f5_to_f1[3].f5_to_f1' is not directly connected to top level port. 'DIFF_TERM' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. WARNING: [Constraints 18-549] Could not create 'IBUF_LOW_PWR' constraint because cell 'input_f5_to_f1[3].f5_to_f1' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored by Vivado but preserved inside the database. Resolution: It is recommended to apply the I/O constraint directly to the top level port instead of applying the constraint to the cell connected to the port. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3233.074 ; gain = 596.727 ; free physical = 1166 ; free virtual = 11299 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:54] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga1.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga1.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_only_fpga1.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_only_fpga1.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3233.074 ; gain = 0.000 ; free physical = 1166 ; free virtual = 11299 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3233.074 ; gain = 1446.652 ; free physical = 1166 ; free virtual = 11299 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3241.078 ; gain = 0.000 ; free physical = 1160 ; free virtual = 11293 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1f604dd98 Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3259.922 ; gain = 18.844 ; free physical = 1160 ; free virtual = 11293 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1f604dd98 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1f604dd98 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 1 Initialization | Checksum: 1f604dd98 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1f604dd98 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1f604dd98 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 2 Timer Update And Timing Data Collection | Checksum: 1f604dd98 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 3 inverters resulting in an inversion of 30 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 290f7a3e2 Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Retarget | Checksum: 290f7a3e2 INFO: [Opt 31-389] Phase Retarget created 5 cells and removed 72 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 23c869256 Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Constant propagation | Checksum: 23c869256 INFO: [Opt 31-389] Phase Constant propagation created 2 cells and removed 49 cells Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 5 Sweep | Checksum: 2bdc6a446 Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3587.875 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Sweep | Checksum: 2bdc6a446 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 47 cells INFO: [Opt 31-1021] In phase Sweep, 92 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 22dba5831 Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.3 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 BUFG optimization | Checksum: 22dba5831 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 1 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 22dba5831 Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 Shift Register Optimization | Checksum: 22dba5831 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 2b583c81a Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 Post Processing Netlist | Checksum: 2b583c81a INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 23c764fd2 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3619.891 ; gain = 0.000 ; free physical = 822 ; free virtual = 10956 Phase 9.2 Verifying Netlist Connectivity | Checksum: 23c764fd2 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 Phase 9 Finalization | Checksum: 23c764fd2 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.4 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 5 | 72 | 1 | | Constant propagation | 2 | 49 | 0 | | Sweep | 0 | 47 | 92 | | BUFG optimization | 0 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 1 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 23c764fd2 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.4 . Memory (MB): peak = 3619.891 ; gain = 32.016 ; free physical = 822 ; free virtual = 10956 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 20 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 16 newly gated: 8 Total Ports: 40 Ending PowerOpt Patch Enables Task | Checksum: 24988fbd8 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 694 ; free virtual = 10829 Ending Power Optimization Task | Checksum: 24988fbd8 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 193.906 ; free physical = 694 ; free virtual = 10829 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 246b3f26f Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 692 ; free virtual = 10828 Ending Final Cleanup Task | Checksum: 246b3f26f Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 692 ; free virtual = 10828 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 692 ; free virtual = 10828 Ending Netlist Obfuscation Task | Checksum: 246b3f26f Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 692 ; free virtual = 10828 INFO: [Common 17-83] Releasing license: Implementation 50 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3813.797 ; gain = 580.723 ; free physical = 692 ; free virtual = 10828 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 675 ; free virtual = 10820 Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 675 ; free virtual = 10820 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 675 ; free virtual = 10820 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 667 ; free virtual = 10813 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 667 ; free virtual = 10813 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 667 ; free virtual = 10814 Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 667 ; free virtual = 10814 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/impl_1/top_efex_processor_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 644 ; free virtual = 10781 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1be4cc9c6 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 644 ; free virtual = 10781 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 644 ; free virtual = 10781 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: da7f6d60 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 644 ; free virtual = 10782 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1a31747af Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10784 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a31747af Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10784 Phase 1 Placer Initialization | Checksum: 1a31747af Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10784 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: cfe490ca Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10784 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1a6e33633 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10784 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1a6e33633 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10784 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1a4a2e7e0 Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 660 ; free virtual = 10797 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1a4a2e7e0 Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 661 ; free virtual = 10799 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 159 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 70 nets or LUTs. Breaked 0 LUT, combined 70 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 661 ; free virtual = 10799 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 70 | 70 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 70 | 70 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 191572b99 Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 661 ; free virtual = 10799 Phase 2.5 Global Place Phase2 | Checksum: 223b15ea9 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 663 ; free virtual = 10801 Phase 2 Global Placement | Checksum: 223b15ea9 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 663 ; free virtual = 10801 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba7514e4 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 663 ; free virtual = 10801 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: fb61e697 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 675 ; free virtual = 10812 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1532f366b Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 675 ; free virtual = 10812 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175df3f04 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 675 ; free virtual = 10812 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: ec31f004 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 673 ; free virtual = 10810 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: f23d5f45 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 674 ; free virtual = 10812 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1173edf22 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 674 ; free virtual = 10812 Phase 3 Detail Placement | Checksum: 1173edf22 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 674 ; free virtual = 10812 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 13d80cc04 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.617 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: fe9c756d Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 678 ; free virtual = 10815 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 19465bf20 Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 676 ; free virtual = 10814 Phase 4.1.1.1 BUFG Insertion | Checksum: 13d80cc04 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 676 ; free virtual = 10814 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=2.617. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1be720024 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 676 ; free virtual = 10814 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 676 ; free virtual = 10814 Phase 4.1 Post Commit Optimization | Checksum: 1be720024 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 676 ; free virtual = 10814 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1be720024 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 683 ; free virtual = 10821 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1be720024 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 683 ; free virtual = 10821 Phase 4.3 Placer Reporting | Checksum: 1be720024 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 683 ; free virtual = 10821 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 683 ; free virtual = 10821 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 683 ; free virtual = 10821 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d03eab3d Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 683 ; free virtual = 10821 Ending Placer Task | Checksum: 11dcb4190 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 684 ; free virtual = 10821 81 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 684 ; free virtual = 10821 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 668 ; free virtual = 10806 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 655 ; free virtual = 10794 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 656 ; free virtual = 10804 Wrote PlaceDB: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 656 ; free virtual = 10809 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 656 ; free virtual = 10809 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 656 ; free virtual = 10809 Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 655 ; free virtual = 10808 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 653 ; free virtual = 10808 Write Physdb Complete: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 653 ; free virtual = 10808 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/impl_1/top_efex_processor_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Starting Initial Update Timing Task Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.95 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 644 ; free virtual = 10785 INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 2.617 | TNS= 0.000 | INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 91 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 646 ; free virtual = 10796 Wrote PlaceDB: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 645 ; free virtual = 10800 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 645 ; free virtual = 10800 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 645 ; free virtual = 10800 Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 645 ; free virtual = 10801 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 645 ; free virtual = 10802 Write Physdb Complete: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3813.797 ; gain = 0.000 ; free physical = 645 ; free virtual = 10802 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' Starting Routing Task Phase 1 Build RT Design Checksum: PlaceDB: 7426cdad ConstDB: 0 ShapeSum: 567fc250 RouteDB: 5324b193 Post Restoration Checksum: NetGraph: ec2927f8 | NumContArr: 700e398 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2787c00ca Time (s): cpu = 00:00:58 ; elapsed = 00:00:58 . Memory (MB): peak = 4127.121 ; gain = 313.324 ; free physical = 423 ; free virtual = 10441 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2787c00ca Time (s): cpu = 00:00:58 ; elapsed = 00:00:58 . Memory (MB): peak = 4127.121 ; gain = 313.324 ; free physical = 423 ; free virtual = 10441 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2787c00ca Time (s): cpu = 00:00:58 ; elapsed = 00:00:58 . Memory (MB): peak = 4127.121 ; gain = 313.324 ; free physical = 423 ; free virtual = 10441 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2917983e1 Time (s): cpu = 00:01:03 ; elapsed = 00:01:03 . Memory (MB): peak = 4233.496 ; gain = 419.699 ; free physical = 462 ; free virtual = 10355 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.566 | TNS=0.000 | WHS=-0.221 | THS=-106.288| Router Utilization Summary Global Vertical Routing Utilization = 6.02207e-06 % Global Horizontal Routing Utilization = 9.83014e-06 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 5689 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 5688 Number of Partially Routed Nets = 1 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2297093c4 Time (s): cpu = 00:01:06 ; elapsed = 00:01:06 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 440 ; free virtual = 10333 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2297093c4 Time (s): cpu = 00:01:06 ; elapsed = 00:01:06 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 440 ; free virtual = 10333 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 1d7fee659 Time (s): cpu = 00:01:08 ; elapsed = 00:01:08 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 439 ; free virtual = 10332 Phase 4 Initial Routing | Checksum: 1d7fee659 Time (s): cpu = 00:01:08 ; elapsed = 00:01:08 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 439 ; free virtual = 10332 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 412 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.832 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 1ad1b445d Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 437 ; free virtual = 10331 Phase 5 Rip-up And Reroute | Checksum: 1ad1b445d Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 437 ; free virtual = 10331 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1 Delay CleanUp | Checksum: 1ad1b445d Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 437 ; free virtual = 10331 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 1ad1b445d Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 437 ; free virtual = 10331 Phase 6 Delay and Skew Optimization | Checksum: 1ad1b445d Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 437 ; free virtual = 10331 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.917 | TNS=0.000 | WHS=0.025 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 246c319a0 Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 437 ; free virtual = 10330 Phase 7 Post Hold Fix | Checksum: 246c319a0 Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 Phase 8 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.119375 % Global Horizontal Routing Utilization = 0.153232 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 8 Route finalize | Checksum: 246c319a0 Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 439 ; free virtual = 10332 Phase 9 Verifying routed nets Verification completed successfully Phase 9 Verifying routed nets | Checksum: 246c319a0 Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 439 ; free virtual = 10332 Phase 10 Depositing Routes Phase 10 Depositing Routes | Checksum: 208651b2e Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 Phase 11 Post Process Routing Phase 11 Post Process Routing | Checksum: 208651b2e Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 Phase 12 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=2.917 | TNS=0.000 | WHS=0.025 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 12 Post Router Timing | Checksum: 208651b2e Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 Total Elapsed time in route_design: 71.12 secs Phase 13 Post-Route Event Processing Phase 13 Post-Route Event Processing | Checksum: 1cdea5539 Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 1cdea5539 Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 101 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 4244.855 ; gain = 431.059 ; free physical = 438 ; free virtual = 10331 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx Command: report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/impl_1/top_efex_processor_drc_routed.rpt. report_drc completed successfully INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx Command: report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/golden/efex_golden_processor.1/efex_golden_processor.1.runs/impl_1/top_efex_processor_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_processor_timing_summary_routed.rpt -pb top_efex_processor_timing_summary_routed.pb -rpx top_efex_processor_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_processor_timing_summary_routed_1.rpt -pb top_efex_processor_timing_summary_routed_1.pb -rpx top_efex_processor_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_processor_route_status.rpt -pb top_efex_processor_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_processor_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_processor_bus_skew_routed.rpt -pb top_efex_processor_bus_skew_routed.pb -rpx top_efex_processor_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx Command: report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 120 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_processor_clock_utilization_routed.rpt generate_parallel_reports: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4244.855 ; gain = 0.000 ; free physical = 393 ; free virtual = 10291 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_processor.1... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.2-3326DE2 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_golden_processor.1 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1 clean. INFO: [Hog:Msg-0] The git SHA value 3326de2 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_golden_processor.1... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/golden/efex_golden_processor.1 clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.2-3326DE2 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/golden/efex_golden_processor.1-v1.7.2-3326DE2... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.