*** Running vivado with args -log top_efex_control.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_control.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Mon Nov 10 19:38:44 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_control.tcl -notrace Command: link_design -top top_efex_control -part xc7vx330tffg1157-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.combined_ttc_ila' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.crc_ila_hub1' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub1_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.dcp' for cell 'GOLDEN_IF.hub2_axi_stream_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0.dcp' for cell 'GOLDEN_IF.output_channel2_ila' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.dcp' for cell 'ttc_clk' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.dcp' for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.dcp' for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1.dcp' for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.dcp' for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.dcp' for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0.dcp' for cell 'eth/emac0' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.dcp' for cell 'eth/fifo' Netlist sorting complete. Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2167.062 ; gain = 0.000 ; free physical = 6527 ; free virtual = 13887 INFO: [Netlist 29-17] Analyzing 6739 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Chipscope 16-324] Core: GOLDEN_IF.combined_ttc_ila UUID: bea82e6f-d741-5e47-8991-9b48389c8e5f INFO: [Chipscope 16-324] Core: GOLDEN_IF.crc_ila_hub1 UUID: 4e0c642b-a9dc-5961-a2bc-ca2676835227 INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel1_ila UUID: 06d948b5-d0b9-5775-982b-1bbdd4ae9e4b INFO: [Chipscope 16-324] Core: GOLDEN_IF.output_channel2_ila UUID: e8b8e448-8dc6-56f7-93aa-b63f1f2e1d92 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila UUID: ffa2dada-c8e4-56e5-b1e8-34982d8b3eb3 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila UUID: 8c028890-e602-58b6-9829-942564595598 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila UUID: 8576164c-903c-5824-a733-fc7eaa390c62 INFO: [Chipscope 16-324] Core: GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila UUID: 17cfd698-ea4b-5c9e-9fe9-4ad6e47761ed Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc_board.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc:54] get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3163.918 ; gain = 671.789 ; free physical = 5693 ; free virtual = 13080 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc.xdc] for cell 'ttc_clk/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.combined_ttc_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel1_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.output_channel2_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila_impl.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.crc_ila_hub1/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_v6_2/constraints/ila.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_board.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0.xdc] for cell 'eth/emac0/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc:6] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/golden_control.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/top_fpga_ctrl.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/inter_fpga_xdc.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/xdc/ctrl_fpga_mgt.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo_clocks.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2_clocks.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4_clocks.xdc] for cell 'eth/fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo_clocks.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:40] INFO: [Vivado 12-3272] Current instance is the top level cell 'eth/emac0/U0' of design 'design_1' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:41] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports mii_tx_clk]'. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:57] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:57] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports mii_tx_clk]'. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:59] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc:59] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/synth/temac_gbe_v9_0_clocks.xdc] for cell 'eth/emac0/U0' INFO: [Project 1-1714] 66 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-1687] 46 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.301 ; gain = 0.000 ; free physical = 5636 ; free virtual = 13023 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1797 instances were transformed. CFGLUT5 => CFGLUT5 (SRL16E, SRLC32E): 432 instances IOBUF => IOBUF (IBUF, OBUFT): 1 instance OBUFDS => OBUFDS: 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances 40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:32 . Memory (MB): peak = 3201.301 ; gain = 1652.098 ; free physical = 5636 ; free virtual = 13023 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/tcl/v7ht.tcl] Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx330t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3201.301 ; gain = 0.000 ; free physical = 5633 ; free virtual = 13020 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1d3ff36c9 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3201.301 ; gain = 0.000 ; free physical = 5590 ; free virtual = 12978 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1.1 Generate And Synthesize Debug Cores INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3565.004 ; gain = 0.000 ; free physical = 4735 ; free virtual = 12127 Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3565.004 ; gain = 0.000 ; free physical = 4771 ; free virtual = 12163 Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 234013fa7 Time (s): cpu = 00:01:05 ; elapsed = 00:01:11 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4771 ; free virtual = 12163 Phase 1.1 Core Generation And Design Setup | Checksum: 234013fa7 Time (s): cpu = 00:01:05 ; elapsed = 00:01:11 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4771 ; free virtual = 12163 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 234013fa7 Time (s): cpu = 00:01:05 ; elapsed = 00:01:11 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4771 ; free virtual = 12163 Phase 1 Initialization | Checksum: 234013fa7 Time (s): cpu = 00:01:05 ; elapsed = 00:01:11 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4771 ; free virtual = 12163 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 234013fa7 Time (s): cpu = 00:01:07 ; elapsed = 00:01:13 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4965 ; free virtual = 12357 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 234013fa7 Time (s): cpu = 00:01:08 ; elapsed = 00:01:13 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4965 ; free virtual = 12357 Phase 2 Timer Update And Timing Data Collection | Checksum: 234013fa7 Time (s): cpu = 00:01:08 ; elapsed = 00:01:13 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4965 ; free virtual = 12357 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 43 inverters resulting in an inversion of 503 pins INFO: [Opt 31-138] Pushed 13 inverter(s) to 16 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 20f110e6c Time (s): cpu = 00:01:09 ; elapsed = 00:01:14 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 4981 ; free virtual = 12373 Retarget | Checksum: 20f110e6c INFO: [Opt 31-389] Phase Retarget created 121 cells and removed 368 cells INFO: [Opt 31-1021] In phase Retarget, 469 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1b258afc9 Time (s): cpu = 00:01:09 ; elapsed = 00:01:15 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 5006 ; free virtual = 12399 Constant propagation | Checksum: 1b258afc9 INFO: [Opt 31-389] Phase Constant propagation created 178 cells and removed 624 cells INFO: [Opt 31-1021] In phase Constant propagation, 153 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3565.004 ; gain = 0.000 ; free physical = 5006 ; free virtual = 12398 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3565.004 ; gain = 0.000 ; free physical = 5029 ; free virtual = 12422 Phase 5 Sweep | Checksum: 236c658b8 Time (s): cpu = 00:01:11 ; elapsed = 00:01:16 . Memory (MB): peak = 3565.004 ; gain = 22.812 ; free physical = 5029 ; free virtual = 12422 Sweep | Checksum: 236c658b8 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 743 cells INFO: [Opt 31-1021] In phase Sweep, 4721 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 3 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 2039a15bd Time (s): cpu = 00:01:12 ; elapsed = 00:01:17 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5046 ; free virtual = 12438 BUFG optimization | Checksum: 2039a15bd INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 3 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1cb09fd04 Time (s): cpu = 00:01:12 ; elapsed = 00:01:17 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5046 ; free virtual = 12438 Shift Register Optimization | Checksum: 1cb09fd04 INFO: [Opt 31-389] Phase Shift Register Optimization created 2 cells and removed 4 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1bee52d46 Time (s): cpu = 00:01:12 ; elapsed = 00:01:17 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5046 ; free virtual = 12438 Post Processing Netlist | Checksum: 1bee52d46 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 385 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1224ca570 Time (s): cpu = 00:01:14 ; elapsed = 00:01:19 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5078 ; free virtual = 12470 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3597.020 ; gain = 0.000 ; free physical = 5078 ; free virtual = 12470 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1224ca570 Time (s): cpu = 00:01:14 ; elapsed = 00:01:19 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5078 ; free virtual = 12470 Phase 9 Finalization | Checksum: 1224ca570 Time (s): cpu = 00:01:14 ; elapsed = 00:01:19 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5078 ; free virtual = 12470 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 121 | 368 | 469 | | Constant propagation | 178 | 624 | 153 | | Sweep | 6 | 743 | 4721 | | BUFG optimization | 0 | 3 | 0 | | Shift Register Optimization | 2 | 4 | 0 | | Post Processing Netlist | 0 | 0 | 385 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1224ca570 Time (s): cpu = 00:01:14 ; elapsed = 00:01:19 . Memory (MB): peak = 3597.020 ; gain = 54.828 ; free physical = 5078 ; free virtual = 12470 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 21 BRAM(s) out of a total of 356 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 14 WE to EN ports Number of BRAM Ports augmented: 300 newly gated: 22 Total Ports: 712 Ending PowerOpt Patch Enables Task | Checksum: 2580b273e Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4264 ; free virtual = 11661 Ending Power Optimization Task | Checksum: 2580b273e Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 4588.219 ; gain = 991.199 ; free physical = 4264 ; free virtual = 11661 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 17de3e22e Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4266 ; free virtual = 11663 Ending Final Cleanup Task | Checksum: 17de3e22e Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4266 ; free virtual = 11663 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4266 ; free virtual = 11663 Ending Netlist Obfuscation Task | Checksum: 17de3e22e Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4266 ; free virtual = 11663 INFO: [Common 17-83] Releasing license: Implementation 86 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:19 ; elapsed = 00:02:20 . Memory (MB): peak = 4588.219 ; gain = 1386.918 ; free physical = 4266 ; free virtual = 11663 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx Command: report_drc -file top_efex_control_drc_opted.rpt -pb top_efex_control_drc_opted.pb -rpx top_efex_control_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4273 ; free virtual = 11670 generate_parallel_reports: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4273 ; free virtual = 11670 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4222 ; free virtual = 11668 Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4221 ; free virtual = 11669 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4221 ; free virtual = 11669 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4221 ; free virtual = 11669 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4221 ; free virtual = 11669 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4221 ; free virtual = 11671 Write Physdb Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4221 ; free virtual = 11671 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4246 ; free virtual = 11664 INFO: [Chipscope 16-240] Debug cores have already been implemented Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Running DRC as a precondition to command place_design CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block GTHE2_CHANNEL cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt2_MGT_TX_RX_6G4_i/gthe2_i is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems. CRITICAL WARNING: [DRC AVAL-326] Hard_block_must_have_LOC: The hard block GTHE2_CHANNEL cell GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i/U0/MGT_TX_RX_6G4_i/gt3_MGT_TX_RX_6G4_i/gthe2_i is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing or other issues. Please check your design and set a valid LOC for this block to avoid these problems. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Critical Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11663 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12dbf6196 Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11663 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11663 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14fae494b Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4236 ; free virtual = 11660 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d782a45d Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4223 ; free virtual = 11647 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d782a45d Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4223 ; free virtual = 11647 Phase 1 Placer Initialization | Checksum: 1d782a45d Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4223 ; free virtual = 11647 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 23a68b4c8 Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4233 ; free virtual = 11657 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1fbb40f57 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4233 ; free virtual = 11657 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1fbb40f57 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4233 ; free virtual = 11657 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 16d1ec619 Time (s): cpu = 00:01:27 ; elapsed = 00:01:27 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4235 ; free virtual = 11659 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 19650b917 Time (s): cpu = 00:01:33 ; elapsed = 00:01:33 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4243 ; free virtual = 11668 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 43 LUTNM shape to break, 2247 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 33, two critical 10, total 43, new lutff created 6 INFO: [Physopt 32-1138] End 1 Pass. Optimized 895 nets or LUTs. Breaked 43 LUTs, combined 852 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-1408] Pass 1. Identified 2 candidate nets for high-fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/rst_320_sig_reg_n_0. Replicated 8 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/IPBusblock/U1_rdout_ipb_slave/update_counter_reg. Replicated 45 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 53 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 53 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4243 ; free virtual = 11667 INFO: [Physopt 32-76] Pass 1. Identified 10 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 5 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/input_error_block.input_ok_reg__0. Replicated 6 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/input_error_block.input_ok_reg__0. Replicated 4 times. INFO: [Physopt 32-232] Optimized 10 nets. Created 46 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 10 nets or cells. Created 46 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4243 ; free virtual = 11667 INFO: [Physopt 32-46] Identified 127 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[3]. Replicated 2 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[2]. Replicated 2 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[1]. Replicated 2 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[6]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[4]. Replicated 2 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[11]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[9]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[8]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[5]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[11]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[9]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[3]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[1]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[10]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[2]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[8]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/read_ptr[12]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[12]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[3]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[3] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/write_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[10] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[2] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[1] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[9] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[4] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[8] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[6] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[12] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/read_ptr[11] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/write_ptr[7] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/write_ptr[3] was not replicated. INFO: [Physopt 32-81] Processed net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/write_ptr[0]. Replicated 1 times. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/read_ptr[0] was not replicated. INFO: [Physopt 32-571] Net GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/input_error_block.input_ok_reg_rep_n_0 was not replicated. INFO: [Physopt 32-232] Optimized 26 nets. Created 30 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 26 nets or cells. Created 30 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4243 ; free virtual = 11667 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-527] Pass 1: Identified 41 candidate cells for BRAM register optimization INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[0].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[2].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[1].raw_ram_fifo/Memory_reg_8. 4 registers were pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[0].tob_fifo_B/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_6. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_0. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_11. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg_5. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_4. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_15. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-665] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_16. 1 register was pushed out. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg_7. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_3. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/Memory_reg_10. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_2. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Bulk_sources[3].raw_ram_fifo/Memory_reg_16. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_A/data_ram_fifo/Memory_reg_9. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg_8. No change. INFO: [Physopt 32-666] Processed cell GOLDEN_IF.readout_packet_block/TOB_sources[1].tob_fifo_B/data_ram_fifo/Memory_reg_12. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 13 nets or cells. Created 16 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4242 ; free virtual = 11667 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4242 ; free virtual = 11667 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 43 | 852 | 895 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 53 | 0 | 2 | 0 | 1 | 00:00:01 | | Fanout | 46 | 0 | 10 | 0 | 1 | 00:00:00 | | Critical Cell | 30 | 0 | 26 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 16 | 0 | 13 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 188 | 852 | 946 | 0 | 11 | 00:00:04 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1ee1b29e9 Time (s): cpu = 00:01:44 ; elapsed = 00:01:45 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4254 ; free virtual = 11678 Phase 2.5 Global Place Phase2 | Checksum: 16d5b844a Time (s): cpu = 00:01:47 ; elapsed = 00:01:47 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4252 ; free virtual = 11677 Phase 2 Global Placement | Checksum: 16d5b844a Time (s): cpu = 00:01:47 ; elapsed = 00:01:48 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4252 ; free virtual = 11677 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18256f2e6 Time (s): cpu = 00:01:53 ; elapsed = 00:01:53 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4251 ; free virtual = 11676 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ff1ca811 Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4250 ; free virtual = 11675 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 228129cfa Time (s): cpu = 00:02:06 ; elapsed = 00:02:07 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4251 ; free virtual = 11676 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1ef48201f Time (s): cpu = 00:02:07 ; elapsed = 00:02:07 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4251 ; free virtual = 11676 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 1516aabce Time (s): cpu = 00:02:24 ; elapsed = 00:02:24 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4255 ; free virtual = 11680 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 26407e134 Time (s): cpu = 00:02:43 ; elapsed = 00:02:44 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4257 ; free virtual = 11683 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1997210b0 Time (s): cpu = 00:02:46 ; elapsed = 00:02:47 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4258 ; free virtual = 11683 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 29a24cfc4 Time (s): cpu = 00:02:47 ; elapsed = 00:02:47 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4257 ; free virtual = 11683 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1dfd0809f Time (s): cpu = 00:03:13 ; elapsed = 00:03:14 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4257 ; free virtual = 11683 Phase 3 Detail Placement | Checksum: 1dfd0809f Time (s): cpu = 00:03:13 ; elapsed = 00:03:14 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4257 ; free virtual = 11682 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 282518736 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.379 | TNS=-14.561 | Phase 1 Physical Synthesis Initialization | Checksum: 2a3a72245 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11671 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 27830ed4e Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11671 Phase 4.1.1.1 BUFG Insertion | Checksum: 282518736 Time (s): cpu = 00:03:40 ; elapsed = 00:03:41 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4247 ; free virtual = 11672 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.027. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1132c2410 Time (s): cpu = 00:05:28 ; elapsed = 00:05:30 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4242 ; free virtual = 11669 Time (s): cpu = 00:05:28 ; elapsed = 00:05:30 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4242 ; free virtual = 11669 Phase 4.1 Post Commit Optimization | Checksum: 1132c2410 Time (s): cpu = 00:05:28 ; elapsed = 00:05:31 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4242 ; free virtual = 11669 Post Placement Optimization Initialization | Checksum: 200e4400c Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.444 | TNS=-5.142 | Phase 1 Physical Synthesis Initialization | Checksum: 24e41fd0a Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4238 ; free virtual = 11665 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 272727b4e Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4240 ; free virtual = 11667 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.027. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 286778b74 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.027 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 24925fd11 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/update_counter_reg, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net GOLDEN_IF.backplane_reg/xoff_cntr_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 2fd21c6af Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.027. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2ba0cf594 Time (s): cpu = 00:08:07 ; elapsed = 00:08:10 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4246 ; free virtual = 11673 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 4x4| |___________|___________________|___________________| | East| 16x16| 2x2| |___________|___________________|___________________| | West| 2x2| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 2ba0cf594 Time (s): cpu = 00:08:08 ; elapsed = 00:08:11 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4246 ; free virtual = 11674 Phase 4.3 Placer Reporting | Checksum: 2ba0cf594 Time (s): cpu = 00:08:08 ; elapsed = 00:08:11 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 Time (s): cpu = 00:08:08 ; elapsed = 00:08:11 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2b3a39fbc Time (s): cpu = 00:08:09 ; elapsed = 00:08:12 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 Ending Placer Task | Checksum: 212914fdf Time (s): cpu = 00:08:09 ; elapsed = 00:08:12 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 250 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:08:13 ; elapsed = 00:08:16 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4245 ; free virtual = 11673 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_control_io_placed.rpt report_io: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.37 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4232 ; free virtual = 11660 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_control_utilization_placed.rpt -pb top_efex_control_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_control_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.47 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4196 ; free virtual = 11625 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4152 ; free virtual = 11634 Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4085 ; free virtual = 11648 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4085 ; free virtual = 11648 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4085 ; free virtual = 11648 Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4069 ; free virtual = 11641 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4069 ; free virtual = 11642 Write Physdb Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4069 ; free virtual = 11642 report_design_analysis: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4067 ; free virtual = 11640 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4160 ; free virtual = 11619 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Starting Initial Update Timing Task Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4188 ; free virtual = 11647 INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.027 | TNS= 0.000 | INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 262 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4188 ; free virtual = 11647 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4156 ; free virtual = 11667 Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4062 ; free virtual = 11654 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4062 ; free virtual = 11654 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4062 ; free virtual = 11655 Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4054 ; free virtual = 11655 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4054 ; free virtual = 11657 Write Physdb Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4054 ; free virtual = 11657 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4071 ; free virtual = 11560 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: ff29a2d6 ConstDB: 0 ShapeSum: f118a084 RouteDB: 224f0c85 Post Restoration Checksum: NetGraph: 2b881b6e | NumContArr: 84473775 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 23521481d Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4158 ; free virtual = 11647 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 23521481d Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4158 ; free virtual = 11647 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 23521481d Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4158 ; free virtual = 11647 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 1de0c3103 Time (s): cpu = 00:01:16 ; elapsed = 00:01:16 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4166 ; free virtual = 11657 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.048 | TNS=0.000 | WHS=-2.812 | THS=-5060.431| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 1fac30019 Time (s): cpu = 00:01:36 ; elapsed = 00:01:36 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4160 ; free virtual = 11650 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.048 | TNS=0.000 | WHS=-5.513 | THS=-603.558| Phase 2.4 Update Timing for Bus Skew | Checksum: 27551c54b Time (s): cpu = 00:01:36 ; elapsed = 00:01:37 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4160 ; free virtual = 11650 Router Utilization Summary Global Vertical Routing Utilization = 5.19251e-05 % Global Horizontal Routing Utilization = 4.23801e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 102617 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 102615 Number of Partially Routed Nets = 2 Number of Node Overlaps = 1 Phase 2 Router Initialization | Checksum: 21dbdc6c0 Time (s): cpu = 00:01:38 ; elapsed = 00:01:38 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4160 ; free virtual = 11650 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 21dbdc6c0 Time (s): cpu = 00:01:38 ; elapsed = 00:01:39 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4160 ; free virtual = 11650 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 249f766f5 Time (s): cpu = 00:03:02 ; elapsed = 00:03:03 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4164 ; free virtual = 11655 Phase 4 Initial Routing | Checksum: 249f766f5 Time (s): cpu = 00:03:02 ; elapsed = 00:03:03 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4164 ; free virtual = 11655 INFO: [Route 35-580] Design has 24 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+=======================================================================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+=======================================================================================+ | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/temp1_reg_srl2/D | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_ttc_combined/temp1_reg_srl2/D | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/FSM_sequential_current_state_reg[0]/R | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/Mux_Value_reg[1]/R | | clk40_clk_ttc | clk40_clk_ttc | GOLDEN_IF.synch_hub2_combined_ttc/state_machine/delay_count_reg[1]/R | +--------------------+-------------------+---------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 8415 Number of Nodes with overlaps = 764 Number of Nodes with overlaps = 171 Number of Nodes with overlaps = 51 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.046 | TNS=-0.397 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 1d767081f Time (s): cpu = 00:04:12 ; elapsed = 00:04:13 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4176 ; free virtual = 11667 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 1080 Number of Nodes with overlaps = 165 Number of Nodes with overlaps = 45 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.035 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 1faad3a42 Time (s): cpu = 00:04:25 ; elapsed = 00:04:26 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4172 ; free virtual = 11663 Phase 5 Rip-up And Reroute | Checksum: 1faad3a42 Time (s): cpu = 00:04:26 ; elapsed = 00:04:26 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4172 ; free virtual = 11663 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1 Delay CleanUp | Checksum: 1faad3a42 Time (s): cpu = 00:04:26 ; elapsed = 00:04:27 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4172 ; free virtual = 11663 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 1faad3a42 Time (s): cpu = 00:04:26 ; elapsed = 00:04:27 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4171 ; free virtual = 11663 Phase 6 Delay and Skew Optimization | Checksum: 1faad3a42 Time (s): cpu = 00:04:26 ; elapsed = 00:04:27 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4171 ; free virtual = 11663 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.052 | TNS=0.000 | WHS=-1.134 | THS=-71.618| Phase 7.1 Hold Fix Iter | Checksum: 19dd89bde Time (s): cpu = 00:04:34 ; elapsed = 00:04:35 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4174 ; free virtual = 11666 Phase 7.2 Non Free Resource Hold Fix Iter Phase 7.2 Non Free Resource Hold Fix Iter | Checksum: 202870e9b Time (s): cpu = 00:04:34 ; elapsed = 00:04:35 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4174 ; free virtual = 11666 Phase 7 Post Hold Fix | Checksum: 202870e9b Time (s): cpu = 00:04:34 ; elapsed = 00:04:35 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4174 ; free virtual = 11666 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 229f3dd54 Time (s): cpu = 00:04:44 ; elapsed = 00:04:44 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4172 ; free virtual = 11664 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.052 | TNS=0.000 | WHS=0.051 | THS=0.000 | Phase 8 Timing Verification | Checksum: 229f3dd54 Time (s): cpu = 00:04:44 ; elapsed = 00:04:45 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4171 ; free virtual = 11662 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 8.2919 % Global Horizontal Routing Utilization = 10.2253 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Route finalize | Checksum: 229f3dd54 Time (s): cpu = 00:04:44 ; elapsed = 00:04:45 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4174 ; free virtual = 11666 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 229f3dd54 Time (s): cpu = 00:04:45 ; elapsed = 00:04:46 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4174 ; free virtual = 11666 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 1f829527c Time (s): cpu = 00:04:50 ; elapsed = 00:04:51 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4171 ; free virtual = 11663 Phase 12 Post Process Routing Phase 12 Post Process Routing | Checksum: 1f829527c Time (s): cpu = 00:04:51 ; elapsed = 00:04:52 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4171 ; free virtual = 11663 Phase 13 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.054 | TNS=0.000 | WHS=0.052 | THS=0.000 | Phase 13 Post Router Timing | Checksum: 1aec4f03d Time (s): cpu = 00:05:13 ; elapsed = 00:05:14 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4166 ; free virtual = 11658 INFO: [Route 35-61] The design met the timing requirement. Total Elapsed time in route_design: 314.54 secs Phase 14 Post-Route Event Processing Phase 14 Post-Route Event Processing | Checksum: 116f9d8a7 Time (s): cpu = 00:05:14 ; elapsed = 00:05:15 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4166 ; free virtual = 11658 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 116f9d8a7 Time (s): cpu = 00:05:15 ; elapsed = 00:05:16 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4166 ; free virtual = 11658 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 278 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:05:16 ; elapsed = 00:05:17 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4166 ; free virtual = 11658 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_control_drc_routed.rpt -pb top_efex_control_drc_routed.pb -rpx top_efex_control_drc_routed.rpx Command: report_drc -file top_efex_control_drc_routed.rpt -pb top_efex_control_drc_routed.pb -rpx top_efex_control_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4144 ; free virtual = 11636 INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_control_methodology_drc_routed.rpt -pb top_efex_control_methodology_drc_routed.pb -rpx top_efex_control_methodology_drc_routed.rpx Command: report_methodology -file top_efex_control_methodology_drc_routed.rpt -pb top_efex_control_methodology_drc_routed.pb -rpx top_efex_control_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/impl_1/top_efex_control_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4150 ; free virtual = 11643 INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_control_timing_summary_routed.rpt -pb top_efex_control_timing_summary_routed.pb -rpx top_efex_control_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4133 ; free virtual = 11650 INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_control_timing_summary_routed_1.rpt -pb top_efex_control_timing_summary_routed_1.pb -rpx top_efex_control_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4117 ; free virtual = 11634 INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_control_route_status.rpt -pb top_efex_control_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_control_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_control_bus_skew_routed.rpt -pb top_efex_control_bus_skew_routed.pb -rpx top_efex_control_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_control_power_routed.rpt -pb top_efex_control_power_summary_routed.pb -rpx top_efex_control_power_routed.rpx Command: report_power -file top_efex_control_power_routed.rpt -pb top_efex_control_power_summary_routed.pb -rpx top_efex_control_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 297 Infos, 5 Warnings, 2 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4110 ; free virtual = 11642 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_control_clock_utilization_routed.rpt generate_parallel_reports: Time (s): cpu = 00:01:47 ; elapsed = 00:01:44 . Memory (MB): peak = 4588.219 ; gain = 0.000 ; free physical = 4100 ; free virtual = 11632 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_control was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] The git SHA value ea29254 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.7.3-EA29254... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found.