*** Running vivado with args -log top_efex_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_efex_control.tcl ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Mon Nov 10 19:33:22 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_control.tcl -notrace source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-synthesis.tcl INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.7.3-EA29254... INFO: [Hog:Msg-0] Running list file checker... INFO: [Hog:Msg-0] Opening project efex_control... Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2024.2/data/ip'. INFO: [Hog:Msg-0] Checking efex_control list files... INFO: [Hog:Msg-0] Retrieved project files... INFO: [Hog:Msg-0] Design List Files matches project. Nothing to do. INFO: [Hog:Msg-0] Constraint List Files matches project. Nothing to do. INFO: [Hog:Msg-0] /builds/atlas-l1calo-efex/eFEXFirmware/Top//efex_control/hog.conf matches project. Nothing to do INFO: [Hog:Msg-0] Simulation properties for cntl_rdout_sim are up-to-date. Nothing to do INFO: [Hog:Msg-0] Design List files and hog.conf match project. All ok! INFO: [Hog:Msg-0] Simulation list files match project. All ok! INFO: [Hog:Msg-0] Simulation config files match project. All ok! INFO: [Hog:Msg-0] All done. INFO: [Hog:Msg-0] Evaluating non committed changes... INFO: [Hog:Msg-0] No uncommitted changes found. INFO: [Hog:Msg-0] Git describe for ea29254 is: v1.7.3-EA29254 INFO: [Hog:Msg-0] Found last SHA for efex_control: ea29254 INFO: [Hog:Msg-0] Creating XML directory /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml... INFO: [Hog:Msg-0] Copying xml files to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing placeholders with xml version 01070001... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/L1CaloEfex.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_backplane.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_backplane_busy_status.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_common_id_version.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_fifo_status.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_merger_status.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_mgt_status.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_data_path_mux_status.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_infrastructure.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_mgt_channel.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_mgt_quad.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] Copying /builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xml/efex_cntrl_mgt.xml to /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/xml and replacing place holders... INFO: [Hog:CopyIPbusXMLs-0] 13 xml file/s copied INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:WriteGenerics-0] Passing parameters/generics to project's top module... INFO: [Hog:WriteGenerics-0] Setting parameters/generics... INFO: [Hog:Msg-0] Opening version file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/versions.txt... ------------------------- PRE SYNTHESIS ------------------------- 10/11/2025 at 19:33:50 Firmware date and time: 10112025, 00182025 Global SHA: ea29254, VER: 1.7.3 Constraints SHA: f1218c8f, VER: 1.7.1 IPbus XML SHA: de66f99, VER: 1.7.1 Top SHA: f11b1d5, VER: 1.7.1 Hog SHA: 58ef905, VER: 9.69.0 --- Libraries --- infrastructure_lib SHA: f1218c8, VER: 1.7.1 ips SHA: 15891c5, VER: 1.7.1 ipbus_lib SHA: d6f4f62, VER: 1.0.0 ----------------------------------------------------------------- INFO: [Hog:CheckYmlRef-0] Found the following yml files: hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml INFO: [Hog:CheckYmlRef-0] Hog included file hog.yml YAML/hog-common.yml YAML/hog-main.yml YAML/hog-child.yml matches with v9.69.0 in .gitlab-ci.yml. INFO: [Hog:Msg-0] All done. Command: synth_design -top top_efex_control -part xc7vx330tffg1157-2 -global_retiming on Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx330t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx330t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Device 21-403] Loading part xc7vx330tffg1157-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 1 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3274 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2434.262 ; gain = 425.828 ; free physical = 5912 ; free virtual = 13210 --------------------------------------------------------------------------------- WARNING: [Synth 8-4747] shared variables must be of a protected type [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:67] WARNING: [Synth 8-4747] shared variables must be of a protected type [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:68] WARNING: [Synth 8-4747] shared variables must be of a protected type [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:65] WARNING: [Synth 8-4747] shared variables must be of a protected type [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:50] INFO: [Synth 8-638] synthesizing module 'top_efex_control' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:182] Parameter GLOBAL_DATE bound to: 32'b00010000000100010010000000100101 Parameter GLOBAL_TIME bound to: 32'b00000000000110000010000000100101 Parameter GLOBAL_SHA bound to: 32'b00001110101000101001001001010100 Parameter GLOBAL_VER bound to: 32'b00000001000001110000000000000011 Parameter XML_SHA bound to: 32'b00001101111001100110111110011001 Parameter XML_VER bound to: 32'b00000001000001110000000000000001 Parameter TOP_SHA bound to: 32'b00001111000100011011000111010101 Parameter TOP_VER bound to: 32'b00000001000001110000000000000001 Parameter HOG_SHA bound to: 32'b00000101100011101111100100000101 Parameter HOG_VER bound to: 32'b00001001010001010000000000000000 Parameter CON_SHA bound to: 32'b11110001001000011000110010001111 Parameter CON_VER bound to: 32'b00000001000001110000000000000001 Parameter INFRASTRUCTURE_LIB_VER bound to: 32'b00000001000001110000000000000001 Parameter INFRASTRUCTURE_LIB_SHA bound to: 32'b00001111000100100001100011001000 Parameter IPBUS_LIB_SHA bound to: 32'b00001101011011110100111101100010 Parameter IPBUS_LIB_VER bound to: 32'b00000001000000000000000000000000 WARNING: [Synth 8-3819] Generic 'IPS_VER' not present in instantiated entity will be ignored WARNING: [Synth 8-3819] Generic 'IPS_SHA' not present in instantiated entity will be ignored INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 5 - type: integer Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'common_id_registers' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 4 - type: integer Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 1 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:107] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:109] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 2 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:121] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:123] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:135] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:149] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:151] INFO: [Synth 8-256] done synthesizing module 'common_id_registers' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/common_id_registers.vhd:79] INFO: [Synth 8-638] synthesizing module 'top_udp_config_FPGA' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:69] INFO: [Synth 8-638] synthesizing module 'interface_proc_fpga' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/interface_proc_fpga_struct.vhd:47] Parameter IPBUFWIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'UDP_hub_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_fifo.vhd:35] Parameter BUFWIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'UDP_hub_fifo' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_fifo.vhd:35] INFO: [Synth 8-638] synthesizing module 'UDP_hub_if' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_if.vhd:36] INFO: [Synth 8-256] done synthesizing module 'UDP_hub_if' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_if.vhd:36] INFO: [Synth 8-256] done synthesizing module 'interface_proc_fpga' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/interface_proc_fpga_struct.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrl' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] Parameter MAC_CFG bound to: 1'b0 Parameter IP_CFG bound to: 1'b0 Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b1 Parameter N_OOB bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'oob_in' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:89] WARNING: [Synth 8-506] null port 'oob_out' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:90] INFO: [Synth 8-638] synthesizing module 'UDP_if' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] Parameter BUFWIDTH bound to: 4 - type: integer Parameter INTERNALWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'udp_ipam_block' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:60] Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'udp_ipam_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:60] INFO: [Synth 8-638] synthesizing module 'udp_build_arp' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_arp' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_build_ping' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-256] done synthesizing module 'udp_build_ping' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:57] INFO: [Synth 8-638] synthesizing module 'udp_ipaddr_ipam' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'udp_ipaddr_ipam' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:62] INFO: [Synth 8-638] synthesizing module 'udp_build_payload' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-256] done synthesizing module 'udp_build_payload' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:59] INFO: [Synth 8-638] synthesizing module 'udp_build_resend' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_build_resend' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_build_status' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-256] done synthesizing module 'udp_build_status' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:54] INFO: [Synth 8-638] synthesizing module 'udp_status_buffer' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_status_buffer' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:75] INFO: [Synth 8-638] synthesizing module 'udp_byte_sum' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-256] done synthesizing module 'udp_byte_sum' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:51] INFO: [Synth 8-638] synthesizing module 'udp_do_rx_reset' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'udp_do_rx_reset' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'udp_packet_parser' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] Parameter SECONDARYPORT bound to: 1'b0 Parameter DHCP_RARP bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'udp_packet_parser' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:64] INFO: [Synth 8-638] synthesizing module 'udp_rxram_mux' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_rxram_mux' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:82] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] Parameter BUFWIDTH bound to: 1 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxram_shim' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] Parameter BUFWIDTH bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_rxram_shim' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd:56] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_rx' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:62] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_rx' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_rxtransactor_if' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-256] done synthesizing module 'udp_rxtransactor_if' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:49] INFO: [Synth 8-638] synthesizing module 'udp_DualPortRAM_tx' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] Parameter BUFWIDTH bound to: 4 - type: integer Parameter ADDRWIDTH bound to: 11 - type: integer INFO: [Synth 8-226] default block is never used [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:82] INFO: [Synth 8-256] done synthesizing module 'udp_DualPortRAM_tx' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd:48] INFO: [Synth 8-638] synthesizing module 'udp_buffer_selector__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_buffer_selector__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:58] INFO: [Synth 8-638] synthesizing module 'udp_tx_mux' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-256] done synthesizing module 'udp_tx_mux' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:78] INFO: [Synth 8-638] synthesizing module 'udp_txtransactor_if' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_txtransactor_if' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_txtransactor_if_simple.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_clock_crossing_if' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'udp_clock_crossing_if' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:69] INFO: [Synth 8-256] done synthesizing module 'UDP_if' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_if_flat.vhd:93] INFO: [Synth 8-638] synthesizing module 'transactor' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-638] synthesizing module 'transactor_if' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-256] done synthesizing module 'transactor_if' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_if.vhd:57] INFO: [Synth 8-638] synthesizing module 'transactor_sm' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-256] done synthesizing module 'transactor_sm' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_sm.vhd:65] INFO: [Synth 8-638] synthesizing module 'transactor_cfg' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor_cfg' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor_cfg.vhd:53] INFO: [Synth 8-256] done synthesizing module 'transactor' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/transactor.vhd:60] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrl' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_ctrl.vhd:95] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:261] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:262] INFO: [Synth 8-638] synthesizing module 'mac_arbiter' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_eth/firmware/hdl/mac_arbiter.vhd:61] Parameter NSRC bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'mac_arbiter' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_eth/firmware/hdl/mac_arbiter.vhd:61] INFO: [Synth 8-638] synthesizing module 'udp_hub_rarp' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_rarp.vhd:24] INFO: [Synth 8-256] done synthesizing module 'udp_hub_rarp' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_rarp.vhd:24] INFO: [Synth 8-638] synthesizing module 'unique_address' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/unique_address.vhd:22] INFO: [Synth 8-256] done synthesizing module 'unique_address' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/unique_address.vhd:22] INFO: [Synth 8-256] done synthesizing module 'top_udp_config_FPGA' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd:69] INFO: [Synth 8-638] synthesizing module 'interconnect' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'parity_checker' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-256] done synthesizing module 'parity_checker' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd:26] INFO: [Synth 8-638] synthesizing module 'parity_gen' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] Parameter width bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'parity_gen' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/parity_gen_spec.vhd:27] INFO: [Synth 8-256] done synthesizing module 'interconnect' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/interconnect_struct.vhd:36] INFO: [Synth 8-638] synthesizing module 'clocks_7s_extphy' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] INFO: [Synth 8-113] binding component instance 'ibufgds0' to cell 'IBUFGDS' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:51] INFO: [Synth 8-113] binding component instance 'bufg200' to cell 'BUFG' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:57] INFO: [Synth 8-113] binding component instance 'bufg125' to cell 'BUFG' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:62] INFO: [Synth 8-113] binding component instance 'bufgipb' to cell 'BUFG' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:69] Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT3_DIVIDE bound to: 5 - type: integer INFO: [Synth 8-113] binding component instance 'mmcm' to cell 'MMCME2_BASE' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:76] INFO: [Synth 8-638] synthesizing module 'ipbus_clock_div' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] INFO: [Synth 8-113] binding component instance 'reset_gen' to cell 'SRL16' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:58] INFO: [Synth 8-256] done synthesizing module 'ipbus_clock_div' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_util/firmware/hdl/ipbus_clock_div.vhd:51] INFO: [Synth 8-256] done synthesizing module 'clocks_7s_extphy' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd:41] INFO: [Synth 8-638] synthesizing module 'eth_7s_gmii' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:45] INFO: [Synth 8-113] binding component instance 'idelayctrl0' to cell 'IDELAYCTRL' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:116] INFO: [Synth 8-3491] module 'temac_gbe_v9_0' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/temac_gbe_v9_0_stub.vhdl:6' bound to instance 'emac0' of component 'temac_gbe_v9_0' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:124] INFO: [Synth 8-638] synthesizing module 'temac_gbe_v9_0' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/temac_gbe_v9_0_stub.vhdl:52] WARNING: [Synth 8-5640] Port 'wr_rst_busy' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:89] WARNING: [Synth 8-5640] Port 'rd_rst_busy' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:89] INFO: [Synth 8-3491] module 'mac_fifo_axi4' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mac_fifo_axi4_stub.vhdl:6' bound to instance 'fifo' of component 'mac_fifo_axi4' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:168] INFO: [Synth 8-638] synthesizing module 'mac_fifo_axi4' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mac_fifo_axi4_stub.vhdl:33] INFO: [Synth 8-256] done synthesizing module 'eth_7s_gmii' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/eth_gmii/eth_7s_gmii.vhd:45] INFO: [Synth 8-638] synthesizing module 'infrastructure_slaves_cntrl' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd:69] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 7 - type: integer Parameter SEL_WIDTH bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_xadc_drp' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] Parameter reg48 bound to: 16'b0100111100000001 Parameter reg49 bound to: 16'b0000010100001111 INFO: [Synth 8-638] synthesizing module 'xadc_eFEX' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] Parameter reg48 bound to: 16'b0100111100000001 Parameter reg49 bound to: 16'b0000010100001111 INFO: [Synth 8-113] binding component instance 'U_BUFG' to cell 'BUFG' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:141] Parameter INIT_40 bound to: 16'b1001000000000000 Parameter INIT_41 bound to: 16'b0010111011110000 Parameter INIT_42 bound to: 16'b0000010000000000 Parameter INIT_43 bound to: 16'b0010111011110000 Parameter INIT_46 bound to: 16'b0000000000000001 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0100111100000001 Parameter INIT_49 bound to: 16'b0000010100001111 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101100110011001 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1101110111011101 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101000100010001 Parameter INIT_56 bound to: 16'b1001000111101011 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:147] INFO: [Synth 8-256] done synthesizing module 'xadc_eFEX' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd:79] INFO: [Synth 8-256] done synthesizing module 'ipbus_xadc_drp' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd:46] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized2' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 1 - type: integer Parameter N_STAT bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'd' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd:157] INFO: [Synth 8-638] synthesizing module 'ipbus_i2c_master_arb' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/i2c_arbitration.vhd:24] Parameter addr_width bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 2 - type: integer Parameter DECODE_BASE bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_i2c_master' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd:25] INFO: [Synth 8-638] synthesizing module 'i2c_master_top' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:111] INFO: [Synth 8-226] default block is never used [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:258] INFO: [Synth 8-3491] module 'i2c_master_byte_ctrl' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:80' bound to instance 'byte_controller' of component 'i2c_master_byte_ctrl' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:283] INFO: [Synth 8-638] synthesizing module 'i2c_master_byte_ctrl' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:106] INFO: [Synth 8-256] done synthesizing module 'i2c_master_byte_ctrl' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd:106] INFO: [Synth 8-3491] module 'i2c_master_bit_ctrl' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:122' bound to instance 'bit_controller' of component 'i2c_master_bit_ctrl' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:303] INFO: [Synth 8-638] synthesizing module 'i2c_master_bit_ctrl' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:146] INFO: [Synth 8-256] done synthesizing module 'i2c_master_bit_ctrl' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd:146] INFO: [Synth 8-3491] module 'i2c_master_registers' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:81' bound to instance 'registers' of component 'i2c_master_registers' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:322] INFO: [Synth 8-638] synthesizing module 'i2c_master_registers' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:101] INFO: [Synth 8-256] done synthesizing module 'i2c_master_registers' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_registers.vhd:101] INFO: [Synth 8-256] done synthesizing module 'i2c_master_top' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/i2c_master_top.vhd:111] INFO: [Synth 8-256] done synthesizing module 'ipbus_i2c_master' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/opencores_i2c/firmware/hdl/ipbus_i2c_master.vhd:25] INFO: [Synth 8-638] synthesizing module 'ipbus_watchdog' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] Parameter TIMER_WIDTH bound to: 20 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_watchdog' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd:37] INFO: [Synth 8-256] done synthesizing module 'ipbus_i2c_master_arb' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/i2c_arbitration.vhd:24] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] Parameter BYTE_SPI bound to: 0 - type: bool Parameter ADDR_WIDTH bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 4 - type: integer Parameter DECODE_BASE bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized3' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 4 - type: integer Parameter N_STAT bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized3' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'command_sync' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-256] done synthesizing module 'command_sync' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd:30] INFO: [Synth 8-638] synthesizing module 'spi32_8_control' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter BYTE_SPI bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'spi32_8_control' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] INFO: [Synth 8-638] synthesizing module 'clock_pulse' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'clock_pulse' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd:26] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_spi32__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] Parameter BYTE_SPI bound to: 1 - type: bool Parameter ADDR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_branch__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] Parameter NSLV bound to: 4 - type: integer Parameter DECODE_BASE bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_branch__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_branch.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram_flash__parameterized2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] Parameter ADDR_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram_flash__parameterized2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd:44] INFO: [Synth 8-638] synthesizing module 'spi32_8_control__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter BYTE_SPI bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'spi32_8_control__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd:50] INFO: [Synth 8-256] done synthesizing module 'ipbus_spi32__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd:47] INFO: [Synth 8-638] synthesizing module 'ipbus_ram' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ram' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ram.vhd:66] INFO: [Synth 8-256] done synthesizing module 'infrastructure_slaves_cntrl' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/infrastructure_slaves_cntrl.vhd:69] INFO: [Synth 8-638] synthesizing module 'pll_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/pll_selector.vhd:22] INFO: [Synth 8-256] done synthesizing module 'pll_selector' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/pll_selector.vhd:22] INFO: [Synth 8-638] synthesizing module 'startup' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] Parameter PROG_USR bound to: FALSE - type: string Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double INFO: [Synth 8-113] binding component instance 'STARTUPE2_inst' to cell 'STARTUPE2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:34] INFO: [Synth 8-256] done synthesizing module 'startup' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/startup.vhd:22] INFO: [Synth 8-638] synthesizing module 'reconfig' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:38] Parameter MAX_COUNT bound to: 1 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-113] binding component instance 'ICAPE2_inst' to cell 'ICAPE2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:70] INFO: [Synth 8-256] done synthesizing module 'reconfig' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd:38] INFO: [Synth 8-3491] module 'clk_ttc' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/clk_ttc_stub.vhdl:6' bound to instance 'ttc_clk' of component 'clk_ttc' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:976] INFO: [Synth 8-638] synthesizing module 'clk_ttc' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/clk_ttc_stub.vhdl:20] INFO: [Synth 8-638] synthesizing module 'nreset_pll' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_pll.vhd:27] INFO: [Synth 8-638] synthesizing module 'nreset_gen' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_gen.vhd:31] INFO: [Synth 8-256] done synthesizing module 'nreset_gen' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_gen.vhd:31] INFO: [Synth 8-256] done synthesizing module 'nreset_pll' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/nreset_pll.vhd:27] INFO: [Synth 8-638] synthesizing module 'top_mgt_cfpga' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:90] Parameter NProcessorFPGA bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'MGT_quad_gen' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd:89] Parameter num_quad_tx_rx bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt_tx_rx_6g4_wrapper' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_wrapper.vhd:221] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_support' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:420] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1434] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:111] INFO: [Synth 8-113] binding component instance 'ibufds_instq1_clk0' to cell 'IBUFDS_GTE2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:182] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg0_i' to cell 'BUFG' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:196] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg1_i' to cell 'BUFG' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:204] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_GT_USRCLK_SOURCE' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd:111] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4_common' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:70' bound to instance 'common0_i' of component 'MGT_TX_RX_6G4_common' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1473] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_common' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:92] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0000100000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-113] binding component instance 'gthe2_common_i' to cell 'GTHE2_COMMON' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:164] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_common' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd:92] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4_common_reset' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'MGT_TX_RX_6G4_common_reset' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1493] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4_common_reset' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-226] default block is never used [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_common_reset' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common_reset.vhd:91] INFO: [Synth 8-3491] module 'MGT_TX_RX_6G4' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/MGT_TX_RX_6G4_stub.vhdl:6' bound to instance 'MGT_TX_RX_6G4_init_i' of component 'MGT_TX_RX_6G4' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1506] INFO: [Synth 8-638] synthesizing module 'MGT_TX_RX_6G4' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/MGT_TX_RX_6G4_stub.vhdl:250] INFO: [Synth 8-256] done synthesizing module 'MGT_TX_RX_6G4_support' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:420] INFO: [Synth 8-256] done synthesizing module 'mgt_tx_rx_6g4_wrapper' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_wrapper.vhd:221] INFO: [Synth 8-256] done synthesizing module 'MGT_quad_gen' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd:89] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_gen' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:61] Parameter num_quad_tx_rx bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_wrapper' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:207] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_support' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:410] Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:72' bound to instance 'gt_usrclk_source' of component 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1370] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:111] INFO: [Synth 8-113] binding component instance 'ibufds_instq1_clk1' to cell 'IBUFDS_GTE2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:185] INFO: [Synth 8-113] binding component instance 'txoutclk_bufg0_i' to cell 'BUFH' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:199] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg0_i' to cell 'BUFH' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:207] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg1_i' to cell 'BUFH' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:215] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg2_i' to cell 'BUFH' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:222] INFO: [Synth 8-113] binding component instance 'rxoutclk_bufg3_i' to cell 'BUFH' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:229] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:111] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga_common' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:70' bound to instance 'common0_i' of component 'mgt11g2_tx_rx_cfpga_common' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1409] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_common' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:97] Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000001011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b010 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-113] binding component instance 'gthe2_common_i' to cell 'GTHE2_COMMON' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:169] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_common' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common.vhd:97] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga_common_reset' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:78' bound to instance 'common_reset_i' of component 'mgt11g2_tx_rx_cfpga_common_reset' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1434] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga_common_reset' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:91] Parameter STABLE_CLOCK_PERIOD bound to: 16 - type: integer INFO: [Synth 8-226] default block is never used [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:133] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_common_reset' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_common_reset.vhd:91] INFO: [Synth 8-3491] module 'mgt11g2_tx_rx_cfpga' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt11g2_tx_rx_cfpga_stub.vhdl:6' bound to instance 'mgt11g2_tx_rx_cfpga_init_i' of component 'mgt11g2_tx_rx_cfpga' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1448] INFO: [Synth 8-638] synthesizing module 'mgt11g2_tx_rx_cfpga' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt11g2_tx_rx_cfpga_stub.vhdl:237] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_support' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:410] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_wrapper' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:207] INFO: [Synth 8-256] done synthesizing module 'mgt11g2_tx_rx_cfpga_gen' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:61] INFO: [Synth 8-256] done synthesizing module 'top_mgt_cfpga' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:90] INFO: [Synth 8-638] synthesizing module 'top_cntrl_synch' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/top_ctrl_synch.vhd:54] INFO: [Synth 8-638] synthesizing module 'd_type' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/d_type.vhd:24] INFO: [Synth 8-256] done synthesizing module 'd_type' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/d_type.vhd:24] INFO: [Synth 8-638] synthesizing module 'tac_sm' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:37] INFO: [Synth 8-226] default block is never used [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:70] INFO: [Synth 8-256] done synthesizing module 'tac_sm' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/tac_sm.vhd:37] INFO: [Synth 8-638] synthesizing module 'first_stage_synch' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:52] INFO: [Synth 8-638] synthesizing module 'SRL16E_cntrl' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:31] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] Parameter INIT bound to: 16'b0000000000000000 INFO: [Synth 8-113] binding component instance 'SRL16E_inst_32' to cell 'SRL16E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:45] INFO: [Synth 8-256] done synthesizing module 'SRL16E_cntrl' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/srl16e_cntrl.vhd:31] INFO: [Synth 8-256] done synthesizing module 'first_stage_synch' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:52] INFO: [Synth 8-638] synthesizing module 'ctrl_synch_latch' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ctrl_synch_latch.vhd:26] INFO: [Synth 8-256] done synthesizing module 'ctrl_synch_latch' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ctrl_synch_latch.vhd:26] INFO: [Synth 8-256] done synthesizing module 'top_cntrl_synch' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/top_ctrl_synch.vhd:54] INFO: [Synth 8-638] synthesizing module 'cntrl_crc_checker' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/cntrl_crc_checker.vhd:34] INFO: [Synth 8-638] synthesizing module 'osum_crc9d32' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd:18] Parameter REVERSE_BIT_ORDER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'osum_crc9d32' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd:18] INFO: [Synth 8-638] synthesizing module 'ttc_crc_sm' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_crc_sm.vhd:43] INFO: [Synth 8-256] done synthesizing module 'ttc_crc_sm' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_crc_sm.vhd:43] INFO: [Synth 8-256] done synthesizing module 'cntrl_crc_checker' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/cntrl_crc_checker.vhd:34] INFO: [Synth 8-3491] module 'ila_1' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_1_stub.vhdl:6' bound to instance 'crc_ila_hub1' of component 'ila_1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1176] INFO: [Synth 8-638] synthesizing module 'ila_1' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_1_stub.vhdl:20] INFO: [Synth 8-3491] module 'ila_0' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_0_stub.vhdl:6' bound to instance 'combined_ttc_ila' of component 'ila_0' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1405] INFO: [Synth 8-638] synthesizing module 'ila_0' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_0_stub.vhdl:20] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1435] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-113] binding component instance 'SRLC32E_inst_12' to cell 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1449] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'ttc_parity' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd:23] INFO: [Synth 8-256] done synthesizing module 'ttc_parity' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Inter_Connection/ttc_parity.vhd:23] INFO: [Synth 8-638] synthesizing module 'backplane_registers' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:58] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized2' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 28 - type: integer Parameter SEL_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized4' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 2 - type: integer Parameter N_STAT bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized4' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized5' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 6 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized5' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:148] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:155] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:167] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:168] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:167] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:168] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:180] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized6' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 4 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized6' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:195] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:200] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:195] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:200] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:212] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:219] INFO: [Synth 8-638] synthesizing module 'cntr_generic' [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 32 - type: integer Parameter WRAPAROUND bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'backplane_registers' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/backplane_registers.vhd:58] INFO: [Synth 8-638] synthesizing module 'mgt_cntrl_slaves' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_cntrl_slaves.vhd:61] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized3' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 3 - type: integer Parameter SEL_WIDTH bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized3' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'cntrl_mgt_quad_slaves' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized4' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 8 - type: integer Parameter SEL_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized4' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'led_stretch' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/led_stretch.vhd:23] INFO: [Synth 8-256] done synthesizing module 'led_stretch' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/Process_Common_slave/led_stretch.vhd:23] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:147] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:160] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:187] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:188] INFO: [Synth 8-638] synthesizing module 'gt_information' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:67] Parameter addr_width bound to: 3 - type: integer WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:111] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:112] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:124] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:125] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:137] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:138] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:150] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:151] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:163] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:164] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:176] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:177] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:189] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:190] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:202] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:203] INFO: [Synth 8-638] synthesizing module 'counter' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] INFO: [Synth 8-256] done synthesizing module 'counter' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:31] INFO: [Synth 8-256] done synthesizing module 'gt_information' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd:67] INFO: [Synth 8-256] done synthesizing module 'cntrl_mgt_quad_slaves' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-638] synthesizing module 'cntrl_mgt_quad_slaves__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:147] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:160] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:187] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:188] INFO: [Synth 8-256] done synthesizing module 'cntrl_mgt_quad_slaves__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-638] synthesizing module 'cntrl_mgt_quad_slaves__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:147] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:160] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:173] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:187] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:188] INFO: [Synth 8-256] done synthesizing module 'cntrl_mgt_quad_slaves__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:63] INFO: [Synth 8-256] done synthesizing module 'mgt_cntrl_slaves' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_cntrl_slaves.vhd:61] INFO: [Synth 8-638] synthesizing module 'packet_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:99] Parameter NProcessorFPGA bound to: 4 - type: integer Parameter TOB_FIFO_ADDR_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_ADDR_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_ADDR_WIDTH bound to: 13 - type: integer Parameter TOB_SPY_ADDR_WIDTH bound to: 11 - type: integer Parameter RAW_SPY_ADDR_WIDTH bound to: 11 - type: integer Parameter MERGER_SPY_ADDR_WIDTH bound to: 10 - type: integer Parameter AURORA_SPY_ADDR_WIDTH bound to: 12 - type: integer Parameter MAX_BUILT_PACKET_WIDTH bound to: 9 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-638] synthesizing module 'mgt_buffer' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b00 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b00 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt_axi_fifo_stub.vhdl:6' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] INFO: [Synth 8-638] synthesizing module 'mgt_axi_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt_axi_fifo_stub.vhdl:33] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-638] synthesizing module 'ipbus_dpram' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:62] INFO: [Synth 8-3491] module 'ila_1' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_1_stub.vhdl:6' bound to instance 'mgt_ila' of component 'ila_1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:676] INFO: [Synth 8-638] synthesizing module 'fifo_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:37] INFO: [Synth 8-256] done synthesizing module 'fifo_selector' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:37] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:694] INFO: [Synth 8-638] synthesizing module 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_ram_fifo' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:16' bound to instance 'data_ram_fifo' of component 'packet_ram_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:94] INFO: [Synth 8-638] synthesizing module 'packet_ram_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_ram_fifo' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-3491] module 'packet_fifo' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo.vhd:14' bound to instance 'data_fifo' of component 'packet_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:116] INFO: [Synth 8-638] synthesizing module 'packet_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo.vhd:48] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_fifo' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo.vhd:48] INFO: [Synth 8-256] done synthesizing module 'packet_fifo_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:719] INFO: [Synth 8-638] synthesizing module 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:26] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-256] done synthesizing module 'fwft_register' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:26] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:738] INFO: [Synth 8-638] synthesizing module 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:25] INFO: [Synth 8-256] done synthesizing module 'packet_fifo_reset_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:25] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:748] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:773] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:792] Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b11 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b11 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt_axi_fifo_stub.vhdl:6' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-3491] module 'ila_1' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_1_stub.vhdl:6' bound to instance 'mgt_ila' of component 'ila_1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:676] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:694] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:719] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:738] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:748] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:773] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:792] Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized3' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b01 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver__parameterized3' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b01 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver__parameterized3' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt_axi_fifo_stub.vhdl:6' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-3491] module 'ila_1' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_1_stub.vhdl:6' bound to instance 'mgt_ila' of component 'ila_1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized3' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:676] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:694] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:719] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:738] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:748] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:773] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:792] Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 INFO: [Synth 8-3491] module 'mgt_buffer' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:19' bound to instance 'MGT_object' of component 'mgt_buffer' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized5' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b1 Parameter FPGA_NO bound to: 2'b10 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-3491] module 'mgt_readout_receiver' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:13' bound to instance 'MGT_receiver' of component 'mgt_readout_receiver' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:158] INFO: [Synth 8-638] synthesizing module 'mgt_readout_receiver__parameterized5' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] Parameter FPGA_NO bound to: 2'b10 Parameter FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'mgt_readout_receiver__parameterized5' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_readout_receiver.vhd:39] INFO: [Synth 8-3491] module 'mgt_axi_fifo' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/mgt_axi_fifo_stub.vhdl:6' bound to instance 'mgt_fifo' of component 'mgt_axi_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:181] Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-3491] module 'ipbus_dpram' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram.vhd:43' bound to instance 'IPbus_RAM' of component 'ipbus_dpram' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:200] INFO: [Synth 8-3491] module 'ila_1' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/ila_1_stub.vhdl:6' bound to instance 'mgt_ila' of component 'ila_1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:423] INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized5' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] INFO: [Synth 8-3491] module 'fifo_selector' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_selector.vhd:16' bound to instance 'tob_fifo_selector' of component 'fifo_selector' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:676] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_A' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:694] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_A' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:719] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_A' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:738] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'packet_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:16' bound to instance 'tob_fifo_B' of component 'packet_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:748] Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-3491] module 'fwft_register' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fwft_register.vhd:8' bound to instance 'TOB_register_B' of component 'fwft_register' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:773] INFO: [Synth 8-3491] module 'packet_fifo_reset_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_reset_block.vhd:13' bound to instance 'tob_fifo_reset_B' of component 'packet_fifo_reset_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:792] Parameter DELAY_DEPTH bound to: 63 - type: integer INFO: [Synth 8-3491] module 'ttc_fifo_block' declared at '/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:15' bound to instance 'ttc_fifos' of component 'ttc_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:804] INFO: [Synth 8-638] synthesizing module 'ttc_fifo_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:42] Parameter DELAY_DEPTH bound to: 63 - type: integer Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-3491] module 'SRLC32E' declared at '/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:149195' bound to instance 'SRLC32E_delay_strobe' of component 'SRLC32E' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:132] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-638] synthesizing module 'fifo_40M_160M' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/fifo_40M_160M_stub.vhdl:27] INFO: [Synth 8-256] done synthesizing module 'ttc_fifo_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/ttc_fifo_block.vhd:42] Parameter DATA_FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'efex_tob_merger' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_merger.vhd:50] Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'efex_tob_processer' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_processor.vhd:52] Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter NSRC bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_merger' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter NSRC bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_merger' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'efex_tob_processer' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_processor.vhd:52] Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter DEBUG_FORMAT_VERSION bound to: 3'b001 Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_merger__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_merger__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd:50] Parameter NSRC bound to: 4 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_mux' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter NSRC bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_mux' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'efex_tob_merger' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_tob_merger.vhd:50] Parameter RAM_ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'tob_merger_spy' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/tob_merger_spy.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 10 - type: integer Parameter IPBUS_ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'fifo_spy' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] Parameter IPBUS_ADDR_WIDTH bound to: 10 - type: integer Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram64' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] Parameter ADDR_WIDTH bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram64' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] INFO: [Synth 8-256] done synthesizing module 'fifo_spy' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] INFO: [Synth 8-256] done synthesizing module 'tob_merger_spy' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/tob_merger_spy.vhd:43] Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter RAM_ADDR_WIDTH bound to: 10 - type: integer Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_fifo_block__parameterized2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 11 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_ram_fifo__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_ram_fifo__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_fifo_block__parameterized2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd:43] Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter RAM_ADDR_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 11 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized7' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b00 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b00 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized7' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_ram_fifo__parameterized3' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_ram_fifo__parameterized3' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:56] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized9' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b11 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b11 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized9' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized11' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b01 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b01 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized11' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'mgt_buffer__parameterized13' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter INPUT_FPGA_NO bound to: 2'b10 Parameter DATA_FORMAT_VERSION bound to: 3'b001 Parameter IPBUS_ADDR_WIDTH bound to: 11 - type: integer Parameter ILA_ENABLED bound to: 1'b0 Parameter FPGA_NO bound to: 2'b10 Parameter FORMAT_VERSION bound to: 3'b001 Parameter ADDR_WIDTH bound to: 11 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'mgt_buffer__parameterized13' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:55] Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 13 - type: integer Parameter MAXWIDTH bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter BUFWIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_mux__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter NSRC bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_packet_mux__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_mux.vhd:48] Parameter NSRC bound to: 6 - type: integer Parameter DATA_WIDTH bound to: 65 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_packet_builder' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_builder.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-638] synthesizing module 'CRC20' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 9 - type: integer Parameter G_Poly bound to: 9'b011111011 Parameter G_InitVal bound to: 9'b111111111 INFO: [Synth 8-256] done synthesizing module 'CRC20' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-638] synthesizing module 'CRC20__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] Parameter Nbits bound to: 64 - type: integer Parameter CRC_Width bound to: 20 - type: integer Parameter G_Poly bound to: 20'b10000011010110011111 Parameter G_InitVal bound to: 20'b11111111111111111111 INFO: [Synth 8-256] done synthesizing module 'CRC20__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/crc-20.vhd:31] INFO: [Synth 8-256] done synthesizing module 'efex_packet_builder' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/efex_packet_builder.vhd:31] Parameter IPBUS_ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-638] synthesizing module 'fifo_spy__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] Parameter IPBUS_ADDR_WIDTH bound to: 12 - type: integer Parameter ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_dpram64__parameterized1' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] Parameter ADDR_WIDTH bound to: 12 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_dpram64__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_dpram64.vhd:64] INFO: [Synth 8-256] done synthesizing module 'fifo_spy__parameterized1' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/fifo_spy.vhd:44] Parameter DATA_WIDTH bound to: 65 - type: integer Parameter IPBUS_ADDR_WIDTH bound to: 12 - type: integer Parameter TOB_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'packet_status_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_status_block.vhd:176] Parameter TOB_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_ADDR_MAX_WIDTH bound to: 13 - type: integer Parameter MAX_PACKET_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'rdout_ipb_slave' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:185] Parameter TOB_FIFO_MAX_ADDR_WIDTH bound to: 13 - type: integer Parameter MERGED_FIFO_MAX_ADDR_WIDTH bound to: 13 - type: integer Parameter RAW_FIFO_MAX_ADDR_WIDTH bound to: 13 - type: integer Parameter PACKET_MAX_WIDTH bound to: 9 - type: integer INFO: [Synth 8-638] synthesizing module 'ipbus_fabric_sel__parameterized5' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] Parameter NSLV bound to: 62 - type: integer Parameter SEL_WIDTH bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'ipbus_fabric_sel__parameterized5' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/ipbus_fabric_sel.vhd:59] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized7' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 7 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized7' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:414] WARNING: [Synth 8-6778] Component port with null array found, Will be ignored [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:415] INFO: [Common 17-14] Message 'Synth 8-6778' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized8' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 9 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized8' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized9' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 0 - type: integer Parameter N_STAT bound to: 3 - type: integer WARNING: [Synth 8-506] null port 'ctrl_default' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:60] WARNING: [Synth 8-506] null port 'q' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:61] WARNING: [Synth 8-506] null port 'qmask' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:62] WARNING: [Synth 8-506] null port 'stb' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:63] WARNING: [Synth 8-6774] Null subtype or type declaration found [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:73] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:88] WARNING: [Synth 8-3919] null assignment ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:117] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized9' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-638] synthesizing module 'ipbus_ctrlreg_v__parameterized10' [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] Parameter N_CTRL bound to: 12 - type: integer Parameter N_STAT bound to: 0 - type: integer WARNING: [Synth 8-506] null port 'd' ignored [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:59] INFO: [Synth 8-256] done synthesizing module 'ipbus_ctrlreg_v__parameterized10' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_slaves/firmware/hdl/ipbus_ctrlreg_v.vhd:68] INFO: [Synth 8-256] done synthesizing module 'rdout_ipb_slave' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd:185] INFO: [Synth 8-638] synthesizing module 'rdout_err_cnt' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_err_cnt.vhd:91] INFO: [Synth 8-256] done synthesizing module 'rdout_err_cnt' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_err_cnt.vhd:91] INFO: [Synth 8-638] synthesizing module 'rdout_monitor' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_monitor.vhd:100] INFO: [Synth 8-638] synthesizing module 'cntr_generic__parameterized0' [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] Parameter width bound to: 35 - type: integer Parameter WRAPAROUND bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'cntr_generic__parameterized0' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/src/cntr_generic.vhd:34] INFO: [Synth 8-256] done synthesizing module 'rdout_monitor' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/rdout_monitor.vhd:100] INFO: [Synth 8-638] synthesizing module 'packet_tide_mark_block' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_tide_mark_block.vhd:33] Parameter NChannels bound to: 46 - type: integer INFO: [Synth 8-256] done synthesizing module 'packet_tide_mark_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_tide_mark_block.vhd:33] INFO: [Synth 8-256] done synthesizing module 'packet_status_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_status_block.vhd:176] Parameter INIT bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'packet_block' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:99] INFO: [Synth 8-638] synthesizing module 'axi_stream_fifo' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/axi_stream_fifo_stub.vhdl:35] INFO: [Synth 8-638] synthesizing module 'ufc_controller' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/ufc_controller.vhd:36] INFO: [Synth 8-256] done synthesizing module 'ufc_controller' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/ufc_controller.vhd:36] INFO: [Synth 8-638] synthesizing module 'aurora_hub2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_hub2.vhd:73] INFO: [Synth 8-638] synthesizing module 'aurora_reset' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_reset.vhd:46] INFO: [Synth 8-256] done synthesizing module 'aurora_reset' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_reset.vhd:46] INFO: [Synth 8-638] synthesizing module 'aurora_wrapper_hub2' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_wrapper_hub2.vhd:50] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_support' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:221] INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:75979] INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:75979] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_CLOCK_MODULE' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_clock_module.vhd:86] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:2676] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:2676] INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_CLOCK_MODULE' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_clock_module.vhd:86] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_SUPPORT_RESET_LOGIC' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support_reset_logic.vhd:81] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_cdc_sync_exdes' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd:153] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 1 - type: integer Parameter C_VECTOR_WIDTH bound to: 2 - type: integer Parameter C_MTBF_STAGES bound to: 3 - type: integer INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_cdc_sync_exdes' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd:153] INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_SUPPORT_RESET_LOGIC' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support_reset_logic.vhd:81] WARNING: [Synth 8-5640] Port 'gt_qpllclk_quad4_i' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt_qpllrefclk_quad4_i' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_gtrefclk0_common_in' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qplllock_out' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qplllockdetclk_in' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qpllrefclklost_out' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] WARNING: [Synth 8-5640] Port 'gt1_qpllreset_in' is missing in component declaration [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:404] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2_gt_common_wrapper' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_gt_common_wrapper.vhd:93] Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string Parameter BIAS_CFG bound to: 64'b0000000000000000000001000000000000000000000000000001000001010000 Parameter COMMON_CFG bound to: 32'b00000000000000000000000000011100 Parameter QPLL_CFG bound to: 28'b0000010010000000000111000111 Parameter QPLL_CLKOUT_CFG bound to: 4'b1111 Parameter QPLL_COARSE_FREQ_OVRD bound to: 6'b010000 Parameter QPLL_COARSE_FREQ_OVRD_EN bound to: 1'b0 Parameter QPLL_CP bound to: 10'b0000011111 Parameter QPLL_CP_MONITOR_EN bound to: 1'b0 Parameter QPLL_DMONITOR_SEL bound to: 1'b0 Parameter QPLL_FBDIV bound to: 10'b0010000000 Parameter QPLL_FBDIV_MONITOR_EN bound to: 1'b0 Parameter QPLL_FBDIV_RATIO bound to: 1'b1 Parameter QPLL_INIT_CFG bound to: 24'b000000000000000000000110 Parameter QPLL_LOCK_CFG bound to: 16'b0000010111101000 Parameter QPLL_LPF bound to: 4'b1111 Parameter QPLL_REFCLK_DIV bound to: 1 - type: integer Parameter QPLL_RP_COMP bound to: 1'b0 Parameter QPLL_VTRL_RESET bound to: 2'b00 Parameter RCAL_CFG bound to: 2'b00 Parameter RSVD_ATTR0 bound to: 16'b0000000000000000 Parameter RSVD_ATTR1 bound to: 16'b0000000000000000 Parameter SIM_QPLLREFCLK_SEL bound to: 3'b001 Parameter SIM_RESET_SPEEDUP bound to: FALSE - type: string Parameter SIM_VERSION bound to: 2.0 - type: string INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_gt_common_wrapper' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_gt_common_wrapper.vhd:93] INFO: [Synth 8-638] synthesizing module 'efex_aurora_hub2' [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/.Xil/Vivado-2785-runner-w-bkzzvvi-project-27372-concurrent-0-3q4o73qp/realtime/efex_aurora_hub2_stub.vhdl:134] INFO: [Synth 8-256] done synthesizing module 'efex_aurora_hub2_support' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd:221] INFO: [Synth 8-256] done synthesizing module 'aurora_wrapper_hub2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_wrapper_hub2.vhd:50] INFO: [Synth 8-256] done synthesizing module 'aurora_hub2' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_hub2.vhd:73] INFO: [Synth 8-256] done synthesizing module 'top_efex_control' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:182] WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_SHA WARNING: [Synth 8-6014] Unused sequential element mac_tx_valid_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_fifo.vhd:138] WARNING: [Synth 8-6014] Unused sequential element Got_IP_addr_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_if.vhd:85] WARNING: [Synth 8-6014] Unused sequential element dhcp_discover.ipam_we_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:70] WARNING: [Synth 8-6014] Unused sequential element dhcp_discover.ipam_mode_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipam_block.vhd:234] WARNING: [Synth 8-6014] Unused sequential element arp_we_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:63] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:202] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:207] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:212] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_arp.vhd:64] WARNING: [Synth 8-6014] Unused sequential element ping_end_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:103] WARNING: [Synth 8-6014] Unused sequential element ping_send_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:108] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:69] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:252] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:257] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:262] WARNING: [Synth 8-6014] Unused sequential element do_sum_ping_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:311] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:67] WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_ping.vhd:147] WARNING: [Synth 8-6014] Unused sequential element dhcp_offer.DHCP_vld_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:83] WARNING: [Synth 8-6014] Unused sequential element dhcp_offer.address_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:149] WARNING: [Synth 8-6014] Unused sequential element My_IP_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:250] WARNING: [Synth 8-6014] Unused sequential element My_MAC_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:255] WARNING: [Synth 8-6014] Unused sequential element Server_IP_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_ipaddr_ipam.vhd:260] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:72] WARNING: [Synth 8-6014] Unused sequential element payload_we_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:69] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:294] WARNING: [Synth 8-6014] Unused sequential element buf_to_load_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:299] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:304] WARNING: [Synth 8-6014] Unused sequential element do_sum_payload_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:388] WARNING: [Synth 8-6014] Unused sequential element clr_sum_payload_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:393] WARNING: [Synth 8-6014] Unused sequential element int_data_payload_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:398] WARNING: [Synth 8-6014] Unused sequential element int_valid_payload_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:403] WARNING: [Synth 8-6014] Unused sequential element cksum_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:408] WARNING: [Synth 8-6014] Unused sequential element next_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:434] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:152] WARNING: [Synth 8-6014] Unused sequential element low_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:149] WARNING: [Synth 8-6014] Unused sequential element byteswap_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:499] WARNING: [Synth 8-6014] Unused sequential element ipbus_in_hdr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_payload.vhd:541] WARNING: [Synth 8-6014] Unused sequential element resend_pkt_id_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_resend.vhd:91] WARNING: [Synth 8-6014] Unused sequential element address_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:62] WARNING: [Synth 8-6014] Unused sequential element load_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:245] WARNING: [Synth 8-6014] Unused sequential element send_buf_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_build_status.vhd:250] WARNING: [Synth 8-6014] Unused sequential element next_pkt_id_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_status_buffer.vhd:149] WARNING: [Synth 8-6014] Unused sequential element carry_bit_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:114] WARNING: [Synth 8-6014] Unused sequential element hi_byte_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_byte_sum.vhd:58] WARNING: [Synth 8-6014] Unused sequential element rx_reset_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_do_rx_reset.vhd:52] WARNING: [Synth 8-6014] Unused sequential element primary_mode.pkt_drop_arp_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:118] WARNING: [Synth 8-6014] Unused sequential element primary_mode.pkt_drop_ping_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:164] WARNING: [Synth 8-6014] Unused sequential element dhcp_offer.pkt_drop_ipam_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:252] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ip_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:154] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_ipbus_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:73] WARNING: [Synth 8-6014] Unused sequential element ipbus_status_mask_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:374] WARNING: [Synth 8-6014] Unused sequential element pkt_runt_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:384] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_reliable_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:424] WARNING: [Synth 8-6014] Unused sequential element pkt_reliable_drop_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:470] WARNING: [Synth 8-6014] Unused sequential element reliable_packet_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:493] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_status_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:524] WARNING: [Synth 8-6014] Unused sequential element pkt_drop_resend_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:559] WARNING: [Synth 8-6014] Unused sequential element pkt_broadcast_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_packet_parser.vhd:76] WARNING: [Synth 8-6014] Unused sequential element ram_ready_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd:88] WARNING: [Synth 8-6014] Unused sequential element free_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:101] WARNING: [Synth 8-6014] Unused sequential element clean_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:70] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:147] WARNING: [Synth 8-6014] Unused sequential element busy_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:69] WARNING: [Synth 8-6014] Unused sequential element sending_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:184] WARNING: [Synth 8-6014] Unused sequential element write_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:67] WARNING: [Synth 8-6014] Unused sequential element send_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:68] WARNING: [Synth 8-6014] Unused sequential element free_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:101] WARNING: [Synth 8-6014] Unused sequential element clean_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:70] WARNING: [Synth 8-6014] Unused sequential element send_pending_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:147] WARNING: [Synth 8-6014] Unused sequential element busy_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:69] WARNING: [Synth 8-6014] Unused sequential element sending_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:184] WARNING: [Synth 8-6014] Unused sequential element write_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:67] WARNING: [Synth 8-6014] Unused sequential element send_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_buffer_selector.vhd:68] WARNING: [Synth 8-6014] Unused sequential element ram_ok_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_rxtransactor_if_simple.vhd:55] WARNING: [Synth 8-6014] Unused sequential element rxram_busy_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:98] WARNING: [Synth 8-6014] Unused sequential element rxram_end_addr_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:140] WARNING: [Synth 8-6014] Unused sequential element addr_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:100] WARNING: [Synth 8-6014] Unused sequential element byteswapping_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:177] WARNING: [Synth 8-6014] Unused sequential element mac_tx_data_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:101] WARNING: [Synth 8-6014] Unused sequential element rxram_active_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:130] WARNING: [Synth 8-6014] Unused sequential element udpram_active_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:200] WARNING: [Synth 8-6014] Unused sequential element counting_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:156] WARNING: [Synth 8-6014] Unused sequential element prefetch_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:210] WARNING: [Synth 8-6014] Unused sequential element mac_tx_last_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:102] WARNING: [Synth 8-6014] Unused sequential element mac_tx_valid_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:103] WARNING: [Synth 8-6014] Unused sequential element set_addr_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:153] WARNING: [Synth 8-6014] Unused sequential element addr_to_set_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:154] WARNING: [Synth 8-6014] Unused sequential element default_mode.udpram_busy_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:99] WARNING: [Synth 8-6014] Unused sequential element default_mode.udp_short_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:105] WARNING: [Synth 8-6014] Unused sequential element default_mode.send_special_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:196] WARNING: [Synth 8-6014] Unused sequential element default_mode.special_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:197] WARNING: [Synth 8-6014] Unused sequential element default_mode.udp_counting_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:503] WARNING: [Synth 8-6014] Unused sequential element default_mode.udp_counter_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:508] WARNING: [Synth 8-6014] Unused sequential element default_mode.cksum_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:577] WARNING: [Synth 8-6014] Unused sequential element default_mode.clr_sum_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:582] WARNING: [Synth 8-6014] Unused sequential element default_mode.do_sum_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:587] WARNING: [Synth 8-6014] Unused sequential element default_mode.int_valid_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:592] WARNING: [Synth 8-6014] Unused sequential element default_mode.udpram_end_addr_sig_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:274] WARNING: [Synth 8-6014] Unused sequential element default_mode.int_data_reg was removed. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_tx_mux.vhd:671] INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net gt0_qpllreset_i in module/entity MGT_TX_RX_6G4_support does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_support.vhd:1325] WARNING: [Synth 8-3848] Net TXN_IN[0][TXP_OUT] in module/entity MGT_quad_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd:51] WARNING: [Synth 8-3848] Net TXP_IN[0][TXN_OUT] in module/entity MGT_quad_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd:52] WARNING: [Synth 8-3848] Net gt0_gtgrefclk_common_i in module/entity mgt11g2_tx_rx_cfpga_support does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1315] WARNING: [Synth 8-3848] Net gt0_gtnorthrefclk0_common_i in module/entity mgt11g2_tx_rx_cfpga_support does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1316] WARNING: [Synth 8-3848] Net gt0_gtnorthrefclk1_common_i in module/entity mgt11g2_tx_rx_cfpga_support does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1317] WARNING: [Synth 8-3848] Net gt0_gtsouthrefclk0_common_i in module/entity mgt11g2_tx_rx_cfpga_support does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1319] WARNING: [Synth 8-3848] Net gt0_gtsouthrefclk1_common_i in module/entity mgt11g2_tx_rx_cfpga_support does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_support.vhd:1320] WARNING: [Synth 8-3848] Net GT0_TXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:68] WARNING: [Synth 8-3848] Net GT0_RXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:72] WARNING: [Synth 8-3848] Net GT1_TXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:76] WARNING: [Synth 8-3848] Net GT1_RXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:80] WARNING: [Synth 8-3848] Net GT2_TXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:84] WARNING: [Synth 8-3848] Net GT2_RXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:88] WARNING: [Synth 8-3848] Net GT3_TXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:92] WARNING: [Synth 8-3848] Net GT3_RXUSRCLK2_OUT in module/entity mgt11g2_tx_rx_cfpga_wrapper does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_wrapper.vhd:96] WARNING: [Synth 8-3848] Net TXN_IN[1][TXP_OUT] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:32] WARNING: [Synth 8-3848] Net TXN_IN[0][TXP_OUT] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:32] WARNING: [Synth 8-3848] Net TXP_IN[1][TXN_OUT] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:33] WARNING: [Synth 8-3848] Net TXP_IN[0][TXN_OUT] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:33] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[1][gt0_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[1][gt1_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[1][gt2_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[1][gt3_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[0][gt0_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[0][gt1_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[0][gt2_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net txbufstatus_quad_array[0][gt3_txbufstatus] in module/entity mgt11g2_tx_rx_cfpga_gen does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfgpa_gen.vhd:50] WARNING: [Synth 8-3848] Net tx_bufstatus in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:58] WARNING: [Synth 8-3848] Net MGT_RXN_in[1][RXP_IN] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:96] WARNING: [Synth 8-3848] Net MGT_RXN_in[0][RXP_IN] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:96] WARNING: [Synth 8-3848] Net MGT_RXP_in[1][RXN_IN] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:96] WARNING: [Synth 8-3848] Net MGT_RXP_in[0][RXN_IN] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:96] WARNING: [Synth 8-3848] Net mgt_txdata[1][gt0_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[1][gt1_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[1][gt2_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[1][gt3_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[0][gt0_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[0][gt1_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[0][gt2_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[0][gt3_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txcharisk[1][gt0_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[1][gt1_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[1][gt2_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[1][gt3_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[0][gt0_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[0][gt1_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[0][gt2_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[0][gt3_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net MGT_RXN_in[2][RXP_IN] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:96] WARNING: [Synth 8-3848] Net MGT_RXP_in[2][RXN_IN] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:96] WARNING: [Synth 8-3848] Net mgt_txdata[2][gt0_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[2][gt1_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[2][gt2_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_txdata[2][gt3_txdata_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:101] WARNING: [Synth 8-3848] Net mgt_loopback_in[2][gt0_loopback_in] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:110] WARNING: [Synth 8-3848] Net mgt_txcharisk[2][gt0_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[2][gt1_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[2][gt2_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3848] Net mgt_txcharisk[2][gt3_txcharisk] in module/entity top_mgt_cfpga does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/mgt/top_mgt_cfpga.vhd:109] WARNING: [Synth 8-3936] Found unconnected internal register 'temp6_reg' and it is trimmed from '33' to '32' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:130] WARNING: [Synth 8-3936] Found unconnected internal register 'temp5_reg' and it is trimmed from '33' to '32' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:129] WARNING: [Synth 8-3936] Found unconnected internal register 'temp4_reg' and it is trimmed from '33' to '32' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:128] WARNING: [Synth 8-3848] Net phase_reg in module/entity cntrl_mgt_quad_slaves does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:70] WARNING: [Synth 8-3848] Net phase_reg in module/entity cntrl_mgt_quad_slaves__parameterized0 does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:70] WARNING: [Synth 8-3848] Net phase_reg in module/entity cntrl_mgt_quad_slaves__parameterized1 does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/cntrl_slaves/cntrl_mgt_quad_slaves.vhd:70] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'TOB_sources[0].MGT_object'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'TOB_sources[1].MGT_object'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'TOB_sources[2].MGT_object'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'TOB_sources[3].MGT_object'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_block.vhd:638] WARNING: [Synth 8-3848] Net prmry_ack in module/entity efex_aurora_hub2_cdc_sync_exdes does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd:135] WARNING: [Synth 8-3848] Net scndry_vect_out in module/entity efex_aurora_hub2_cdc_sync_exdes does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd:143] WARNING: [Synth 8-3848] Net tied_to_ground_i in module/entity aurora_wrapper_hub2 does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_wrapper_hub2.vhd:241] WARNING: [Synth 8-3848] Net drpclk_i in module/entity aurora_wrapper_hub2 does not have driver. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/aurora/aurora_wrapper_hub2.vhd:209] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.mgt_slaves'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1582] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.synch_hub2_combined_ttc'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1226] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.synch_ttc_combined'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1133] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.MGT_TX_RX'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1070] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.crc_checker_hub2'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1244] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.crc_checker_hub1'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1151] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.top_aurora_hub1'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1856] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.hub1_ufc_block'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1752] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.top_aurora_hub2'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1902] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'GOLDEN_IF.hub2_ufc_block'. This will prevent further optimization [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/top/top_efex_control.vhd:1791] WARNING: [Synth 8-3917] design top_efex_control has port i2c_rst_0 driven by constant 1 WARNING: [Synth 8-3917] design top_efex_control has port f5_user_led_1 driven by constant 1 WARNING: [Synth 8-3917] design top_efex_control has port ctrl_out[sk14] driven by constant 0 WARNING: [Synth 8-3917] design top_efex_control has port ctrl_out[sk15] driven by constant 0 WARNING: [Synth 8-7129] Port prmry_ack in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port scndry_vect_out[1] in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port scndry_vect_out[0] in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port prmry_resetn in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port scndry_resetn in module efex_aurora_hub2_cdc_sync_exdes is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[23] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[22] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[21] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[15] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[14] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[13] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[7] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[6] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[5] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt0_txctrl[4] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[23] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[22] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[21] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[15] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[14] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[13] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[7] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[6] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[5] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt1_txctrl[4] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[23] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[22] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[21] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[15] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[14] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[13] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[7] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[6] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[5] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt2_txctrl[4] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[23] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[22] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[21] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[15] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[14] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[13] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[7] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[6] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[5] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port aurora_gt3_txctrl[4] in module aurora_wrapper_hub2 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][31] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][30] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][29] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][28] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][27] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][26] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][25] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][24] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][23] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][22] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][21] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][20] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][19] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][18] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][17] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][16] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][15] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][14] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][13] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][12] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][11] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][10] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][9] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][8] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][7] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][6] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][5] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][4] in module ipbus_ctrlreg_v__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port clk in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port reset in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][31] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][30] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][29] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][28] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][27] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][26] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][25] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][24] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][23] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][22] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][21] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][20] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][19] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][18] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][17] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][16] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][15] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][14] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][13] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][12] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][11] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][10] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port ipbus_in[ipb_addr][9] in module ipbus_ctrlreg_v__parameterized9 is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2745.770 ; gain = 737.336 ; free physical = 5696 ; free virtual = 13004 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2745.770 ; gain = 737.336 ; free physical = 5696 ; free virtual = 13004 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2745.770 ; gain = 737.336 ; free physical = 5696 ; free virtual = 13004 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2745.770 ; gain = 0.000 ; free physical = 5746 ; free virtual = 13053 INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub1_axi_stream_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc] for cell 'GOLDEN_IF.hub2_axi_stream_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc] for cell 'ttc_clk' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc] for cell 'ttc_clk' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub1/aurora_core/aurora_module_i/efex_aurora_hub2_i' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/efex_aurora_hub2/efex_aurora_hub2/efex_aurora_hub2_in_context.xdc] for cell 'GOLDEN_IF.top_aurora_hub2/aurora_core/aurora_module_i/efex_aurora_hub2_i' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.combined_ttc_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.combined_ttc_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel1_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel1_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel2_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_0/ila_0/ila_0_in_context.xdc] for cell 'GOLDEN_IF.output_channel2_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.crc_ila_hub1' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/ila_1/ila_1/ila_1_in_context.xdc] for cell 'GOLDEN_IF.crc_ila_hub1' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_delay' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_A' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/ttc_fifos/ttc_fifo_B' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4/mac_fifo_axi4_in_context.xdc] for cell 'eth/fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mac_fifo_axi4/mac_fifo_axi4/mac_fifo_axi4_in_context.xdc] for cell 'eth/fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc] for cell 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[0].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga/mgt11g2_tx_rx_cfpga_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_11G2/MGT_GEN[1].mgt_1quad_Rx_Tx/mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4/MGT_TX_RX_6G4_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/MGT_TX_RX_6G4_ex/MGT_TX_RX_6G4/MGT_TX_RX_6G4_in_context.xdc] for cell 'GOLDEN_IF.MGT_TX_RX/MGT_TX_RX_6G4/MGT_GEN[0].mgt_quad_Rx_Tx/min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc] for cell 'eth/emac0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc] for cell 'eth/emac0' Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2897.488 ; gain = 0.000 ; free physical = 5765 ; free virtual = 13073 INFO: [Project 1-111] Unisim Transformation Summary: A total of 19 instances were transformed. IBUFGDS => IBUFDS: 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 16 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2897.488 ; gain = 0.000 ; free physical = 5761 ; free virtual = 13068 WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.crc_ila_hub1' at clock pin 'clk' is different from the actual clock period '6.250', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.hub1_axi_stream_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.hub2_axi_stream_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.output_channel1_ila' at clock pin 'clk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.output_channel2_ila' at clock pin 'clk' is different from the actual clock period '3.119', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/ila_block.mgt_ila' at clock pin 'clk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/mgt_fifo' at clock pin 'm_aclk' is different from the actual clock period '3.125', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'eth/fifo' at clock pin 's_aclk' is different from the actual clock period '8.000', this can lead to different synthesis results. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2905.426 ; gain = 896.992 ; free physical = 5760 ; free virtual = 13067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx330tffg1157-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2905.426 ; gain = 896.992 ; free physical = 5760 ; free virtual = 13067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- WARNING: set_property IS_IP_OOC_CELL could not find object (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/axi_stream_fifo/axi_stream_fifo/axi_stream_fifo_in_context.xdc, line 3). Applied set_property IO_BUFFER_TYPE = NONE for clk_40_n. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk_40_n. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for clk_40_p. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk_40_p. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/clk_ttc/clk_ttc/clk_ttc_in_context.xdc, line 8). WARNING: set_property IS_IP_OOC_CELL could not find object (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/fifo_40M_160M/fifo_40M_160M/fifo_40M_160M_in_context.xdc, line 3). WARNING: set_property IS_IP_OOC_CELL could not find object (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/mgt_axi_fifo/mgt_axi_fifo/mgt_axi_fifo_in_context.xdc, line 3). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_clk. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 5). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_clk. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 6). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_dv. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 7). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_dv. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 8). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rx_er. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 9). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rx_er. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 10). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[0]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 11). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[0]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 12). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[1]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 13). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[1]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 14). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[2]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 15). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[2]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 16). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[3]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 17). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[3]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 18). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[4]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 19). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[4]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 20). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[5]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 21). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[5]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 22). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[6]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 23). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[6]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 24). Applied set_property IO_BUFFER_TYPE = NONE for gmii_rxd[7]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 25). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_rxd[7]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 26). Applied set_property IO_BUFFER_TYPE = NONE for gmii_gtx_clk. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 27). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_gtx_clk. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 28). Applied set_property IO_BUFFER_TYPE = NONE for gmii_tx_en. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 29). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_tx_en. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 30). Applied set_property IO_BUFFER_TYPE = NONE for gmii_tx_er. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 31). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_tx_er. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 32). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[0]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 33). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[0]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 34). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[1]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 35). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[1]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 36). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[2]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 37). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[2]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 38). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[3]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 39). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[3]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 40). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[4]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 41). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[4]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 42). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[5]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 43). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[5]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 44). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[6]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 45). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[6]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 46). Applied set_property IO_BUFFER_TYPE = NONE for gmii_txd[7]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 47). Applied set_property CLOCK_BUFFER_TYPE = NONE for gmii_txd[7]. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_control/temac_gbe/temac_gbe_v9_0/temac_gbe_v9_0_in_context.xdc, line 48). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.hub1_axi_stream_fifo . (constraint file auto generated constraint). WARNING: set_property KEEP_HIERARCHY could not find object (constraint file auto generated constraint, line ). Applied set_property KEEP_HIERARCHY = SOFT for ttc_clk. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.top_aurora_hub1 /aurora_core/aurora_module_i/efex_aurora_hub2_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.top_aurora_hub2 /aurora_core/aurora_module_i/efex_aurora_hub2_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.combined_ttc_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.output_channel1_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.output_channel2_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[3].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[0].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[1].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[2].MGT_object /\ila_block.mgt_ila . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.crc_ila_hub1 . (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /ttc_fifos/ttc_fifo_A. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /ttc_fifos/ttc_fifo_delay. (constraint file auto generated constraint). WARNING: set_property KEEP_HIERARCHY could not find object (constraint file auto generated constraint, line ). Applied set_property KEEP_HIERARCHY = SOFT for eth/fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[0].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[1].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[2].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\TOB_sources[3].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[0].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[1].MGT_object /mgt_fifo. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.readout_packet_block /\Bulk_sources[2].MGT_object /mgt_fifo. (constraint file auto generated constraint). WARNING: set_property KEEP_HIERARCHY could not find object (constraint file auto generated constraint, line ). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.MGT_TX_RX /MGT_TX_RX_11G2/\MGT_GEN[0].mgt_1quad_Rx_Tx /mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.MGT_TX_RX /MGT_TX_RX_11G2/\MGT_GEN[1].mgt_1quad_Rx_Tx /mgt11g2_tx_rx_cfpga_support_i/mgt11g2_tx_rx_cfpga_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for \GOLDEN_IF.MGT_TX_RX /MGT_TX_RX_6G4/\MGT_GEN[0].mgt_quad_Rx_Tx /min_latency_1_quad_rx_tx_support_i/MGT_TX_RX_6G4_init_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for eth/emac0. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2905.426 ; gain = 896.992 ; free physical = 5760 ; free virtual = 13067 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'fifo_proc.DataOut_reg' and it is trimmed from '10' to '1' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_hub_fifo.vhd:72] WARNING: [Synth 8-3936] Found unconnected internal register 'pkt_rdy_ipb_clk.pkt_rdy_buf_reg' and it is trimmed from '3' to '2' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/ipbus_lib/components/ipbus_core/firmware/hdl/udp_clock_crossing_if.vhd:154] INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_if' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'transactor_sm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'xadc_eFEX' INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_byte_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'c_state_reg' in module 'i2c_master_bit_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'command_sync' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control' INFO: [Synth 8-802] inferred FSM for state register 'sequencer_reg' in module 'spi32_8_control__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'NEXT_STATE_reg' in module 'reconfig' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'nreset_gen' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'tac_sm' WARNING: [Synth 8-3936] Found unconnected internal register 'mux_out_reg' and it is trimmed from '34' to '33' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd:96] INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'ttc_crc_sm' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver' WARNING: [Synth 8-3936] Found unconnected internal register 'fifo_proc.valid_reg' and it is trimmed from '3' to '2' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:235] INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver__parameterized3' INFO: [Synth 8-802] inferred FSM for state register 'State_machine.next_state_reg' in module 'mgt_readout_receiver__parameterized5' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'efex_packet_merger' INFO: [Synth 8-802] inferred FSM for state register 'state_sig_reg' in module 'efex_tob_processer' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'efex_packet_merger__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'state_sig_reg' in module 'efex_packet_mux' INFO: [Synth 8-802] inferred FSM for state register 'state_sig_reg' in module 'efex_tob_merger' WARNING: [Synth 8-3936] Found unconnected internal register 'fifo_proc.valid_reg' and it is trimmed from '3' to '2' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:235] WARNING: [Synth 8-3936] Found unconnected internal register 'fifo_proc.valid_reg' and it is trimmed from '3' to '2' bits. [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd:235] INFO: [Synth 8-802] inferred FSM for state register 'state_sig_reg' in module 'efex_packet_mux__parameterized1' INFO: [Synth 8-802] inferred FSM for state register 'state_machine.next_state_reg' in module 'efex_packet_builder' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 0000010 | 000 st_first | 1000000 | 001 st_hdr | 0100000 | 010 st_prebody | 0010000 | 011 st_body | 0001000 | 100 st_done | 0000100 | 101 st_gap | 0000001 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_if' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 100000 | 000 st_hdr | 001000 | 001 st_addr | 010000 | 010 st_bus_cycle | 000010 | 011 st_rmw_1 | 000100 | 100 st_rmw_2 | 000001 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'transactor_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init_read | 00000000000000000000000000000000000000001 | 000000 read_waitdrdy | 00000000000000000000000000000000000000010 | 000001 write_waitdrdy | 00000000000000000000000000000000000000100 | 000010 read_reg00 | 00000000000000000000000000000000000001000 | 000011 reg00_waitdrdy | 00000000000000000000000000000000000010000 | 000100 read_reg01 | 00000000000000000000000000000000000100000 | 000101 reg01_waitdrdy | 00000000000000000000000000000000001000000 | 000110 read_reg02 | 00000000000000000000000000000000010000000 | 000111 reg02_waitdrdy | 00000000000000000000000000000000100000000 | 001000 read_reg03 | 00000000000000000000000000000001000000000 | 001001 reg03_waitdrdy | 00000000000000000000000000000010000000000 | 001010 read_reg06 | 00000000000000000000000000000100000000000 | 001011 reg06_waitdrdy | 00000000000000000000000000001000000000000 | 001100 read_reg10 | 00000000000000000000000000010000000000000 | 001101 reg10_waitdrdy | 00000000000000000000000000100000000000000 | 001110 read_reg11 | 00000000000000000000000001000000000000000 | 001111 reg11_waitdrdy | 00000000000000000000000010000000000000000 | 010000 read_reg12 | 00000000000000000000000100000000000000000 | 010001 reg12_waitdrdy | 00000000000000000000001000000000000000000 | 010010 read_reg13 | 00000000000000000000010000000000000000000 | 010011 reg13_waitdrdy | 00000000000000000000100000000000000000000 | 010100 read_reg14 | 00000000000000000001000000000000000000000 | 010101 reg14_waitdrdy | 00000000000000000010000000000000000000000 | 010110 read_reg15 | 00000000000000000100000000000000000000000 | 010111 reg15_waitdrdy | 00000000000000001000000000000000000000000 | 011000 read_reg20 | 00000000000000010000000000000000000000000 | 011001 reg20_waitdrdy | 00000000000000100000000000000000000000000 | 011010 read_reg21 | 00000000000001000000000000000000000000000 | 011011 reg21_waitdrdy | 00000000000010000000000000000000000000000 | 011100 read_reg22 | 00000000000100000000000000000000000000000 | 011101 reg22_waitdrdy | 00000000001000000000000000000000000000000 | 011110 read_reg23 | 00000000010000000000000000000000000000000 | 011111 reg23_waitdrdy | 00000000100000000000000000000000000000000 | 100000 read_reg24 | 00000001000000000000000000000000000000000 | 100001 reg24_waitdrdy | 00000010000000000000000000000000000000000 | 100010 read_reg25 | 00000100000000000000000000000000000000000 | 100011 reg25_waitdrdy | 00001000000000000000000000000000000000000 | 100100 read_reg26 | 00010000000000000000000000000000000000000 | 100101 reg26_waitdrdy | 00100000000000000000000000000000000000000 | 100110 read_reg27 | 01000000000000000000000000000000000000000 | 100111 reg27_waitdrdy | 10000000000000000000000000000000000000000 | 101000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'xadc_eFEX' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- st_idle | 000 | 00000 st_start | 001 | 00001 st_read | 010 | 00010 st_write | 011 | 00100 st_ack | 100 | 01000 st_stop | 101 | 10000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_byte_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000 | 00000000000000000 start_a | 00001 | 00000000000000001 start_b | 00010 | 00000000000000010 start_c | 00011 | 00000000000000100 start_d | 00100 | 00000000000001000 start_e | 00101 | 00000000000010000 stop_a | 00110 | 00000000000100000 stop_b | 00111 | 00000000001000000 stop_c | 01000 | 00000000010000000 stop_d | 01001 | 00000000100000000 wr_a | 01010 | 00010000000000000 wr_b | 01011 | 00100000000000000 wr_c | 01100 | 01000000000000000 wr_d | 01101 | 10000000000000000 rd_a | 01110 | 00000001000000000 rd_b | 01111 | 00000010000000000 rd_c | 10000 | 00000100000000000 rd_d | 10001 | 00001000000000000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'c_state_reg' using encoding 'sequential' in module 'i2c_master_bit_ctrl' INFO: [Synth 8-3971] The signal "ipbus_dpram_flash:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized0:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 001 | 00 request | 010 | 01 done | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'one-hot' in module 'command_sync' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control' INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized1:/ram_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram_flash__parameterized2:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000 | 000 start_frame | 001 | 001 read_mem | 010 | 010 shift_io | 011 | 011 write_mem | 100 | 100 end_frame | 101 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sequencer_reg' using encoding 'sequential' in module 'spi32_8_control__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000 | 0000 data_00 | 0001 | 0001 data_01 | 0010 | 0010 data_02 | 0011 | 0011 data_03 | 0100 | 0100 data_04 | 0101 | 0101 data_05 | 0110 | 0110 data_06 | 0111 | 0111 data_07 | 1000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'NEXT_STATE_reg' using encoding 'sequential' in module 'reconfig' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s0 | 00 | 00 s1 | 01 | 01 s2 | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'nreset_gen' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 wt_rstdone | 01 | 01 wt_comma | 10 | 10 wt_ttc_redge | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'tac_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000001 | 000 st0 | 000010 | 001 st1 | 000100 | 010 st2 | 001000 | 011 st3 | 010000 | 100 st4 | 100000 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'one-hot' in module 'ttc_crc_sm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver' INFO: [Synth 8-3971] The signal "ipbus_dpram:/ram_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver__parameterized3' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- init | 0000 | 0000 iSTATE | 0001 | 0001 * waiting | 0010 | 0010 new_packet | 0011 | 0011 save_payload | 0100 | 0100 tob_trailer | 0101 | 0101 padding | 0110 | 0110 corrective_trailer | 0111 | 0111 write_trailer | 1000 | 1000 write_last | 1001 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_machine.next_state_reg' using encoding 'sequential' in module 'mgt_readout_receiver__parameterized5' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 * searching | 0010 | 01 pause | 0100 | 10 active | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'efex_packet_merger' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000000000001 | 0000 * prepare_l1id | 000000000010 | 0001 parse_l1id | 000000000100 | 0010 check_l1id | 000000001000 | 0011 start_debug_merger | 000000010000 | 0100 send_debug_header | 000000100000 | 0101 send_debug | 000001000000 | 0110 wait_fifo | 000010000000 | 0111 send_status | 000100000000 | 1000 skip_payload_header | 001000000000 | 1001 send_payload | 010000000000 | 1010 end_event | 100000000000 | 1011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_sig_reg' using encoding 'one-hot' in module 'efex_tob_processer' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0100 | 00 * searching | 0001 | 01 pause | 1000 | 10 active | 0010 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'efex_packet_merger__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 001 | 10 * starting | 010 | 01 running | 100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_sig_reg' using encoding 'one-hot' in module 'efex_packet_mux' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000 | 000 * wait_fifos | 001 | 001 start_event | 010 | 010 prepare_tobs | 011 | 011 start_merger | 100 | 100 merge_tobs | 101 | 101 ifg | 110 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_sig_reg' using encoding 'sequential' in module 'efex_tob_merger' INFO: [Synth 8-3971] The signal "ipbus_dpram64:/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram64:/ram_th_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 001 | 10 * starting | 010 | 01 running | 100 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_sig_reg' using encoding 'one-hot' in module 'efex_packet_mux__parameterized1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00000000001 | 0000 * capture_l1id | 00000000010 | 0001 do_hdr_crc | 00000000100 | 0010 wait_hdr_crc | 00000001000 | 0011 send_l1id | 00000010000 | 0100 send_payload | 00000100000 | 0101 build_trailer | 00001000000 | 0110 do_trailer_crc | 00010000000 | 0111 wait_trailer_crc | 00100000000 | 1000 send_trailer | 01000000000 | 1001 wait_end | 10000000000 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_machine.next_state_reg' using encoding 'one-hot' in module 'efex_packet_builder' INFO: [Synth 8-3971] The signal "ipbus_dpram64__parameterized1:/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "ipbus_dpram64__parameterized1:/ram_th_reg" was recognized as a true dual port RAM template. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2905.426 ; gain = 896.992 ; free physical = 5756 ; free virtual = 13068 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 31 Bit Adders := 3 2 Input 26 Bit Adders := 1 2 Input 19 Bit Adders := 3 2 Input 16 Bit Adders := 52 2 Input 14 Bit Adders := 16 3 Input 13 Bit Adders := 16 2 Input 13 Bit Adders := 35 2 Input 12 Bit Adders := 11 2 Input 11 Bit Adders := 10 2 Input 10 Bit Adders := 18 2 Input 9 Bit Adders := 37 3 Input 8 Bit Adders := 8 2 Input 8 Bit Adders := 19 2 Input 7 Bit Adders := 5 3 Input 7 Bit Adders := 8 2 Input 6 Bit Adders := 14 2 Input 5 Bit Adders := 22 2 Input 4 Bit Adders := 94 3 Input 4 Bit Adders := 20 2 Input 3 Bit Adders := 16 2 Input 2 Bit Adders := 3 2 Input 1 Bit Adders := 1 +---XORs : 2 Input 20 Bit XORs := 296 2 Input 16 Bit XORs := 1 4 Input 16 Bit XORs := 1 2 Input 9 Bit XORs := 274 2 Input 1 Bit XORs := 48 3 Input 1 Bit XORs := 10 9 Input 1 Bit XORs := 8 4 Input 1 Bit XORs := 6 21 Input 1 Bit XORs := 3 15 Input 1 Bit XORs := 2 10 Input 1 Bit XORs := 4 19 Input 1 Bit XORs := 2 14 Input 1 Bit XORs := 2 12 Input 1 Bit XORs := 2 7 Input 1 Bit XORs := 2 13 Input 1 Bit XORs := 1 +---Registers : 136 Bit Registers := 1 129 Bit Registers := 8 128 Bit Registers := 6 120 Bit Registers := 1 112 Bit Registers := 2 76 Bit Registers := 1 65 Bit Registers := 98 64 Bit Registers := 110 50 Bit Registers := 1 48 Bit Registers := 7 45 Bit Registers := 2 42 Bit Registers := 1 40 Bit Registers := 1 38 Bit Registers := 1 36 Bit Registers := 2 34 Bit Registers := 1 33 Bit Registers := 8 32 Bit Registers := 558 31 Bit Registers := 3 28 Bit Registers := 6 26 Bit Registers := 1 24 Bit Registers := 7 20 Bit Registers := 7 19 Bit Registers := 3 17 Bit Registers := 2 16 Bit Registers := 282 14 Bit Registers := 34 13 Bit Registers := 87 12 Bit Registers := 39 11 Bit Registers := 26 10 Bit Registers := 55 9 Bit Registers := 69 8 Bit Registers := 132 7 Bit Registers := 9 6 Bit Registers := 32 5 Bit Registers := 33 4 Bit Registers := 108 3 Bit Registers := 81 2 Bit Registers := 124 1 Bit Registers := 1876 +---RAMs : 520K Bit (8192 X 65 bit) RAMs := 16 256K Bit (8192 X 32 bit) RAMs := 1 128K Bit (4096 X 32 bit) RAMs := 4 64K Bit (2048 X 32 bit) RAMs := 8 64K Bit (8192 X 8 bit) RAMs := 4 32K Bit (1024 X 32 bit) RAMs := 5 32K Bit (4096 X 8 bit) RAMs := 1 4K Bit (128 X 32 bit) RAMs := 2 1K Bit (16 X 65 bit) RAMs := 20 640 Bit (64 X 10 bit) RAMs := 4 512 Bit (16 X 32 bit) RAMs := 2 +---Muxes : 2 Input 136 Bit Muxes := 1 2 Input 129 Bit Muxes := 4 2 Input 128 Bit Muxes := 7 4 Input 128 Bit Muxes := 1 2 Input 120 Bit Muxes := 1 2 Input 112 Bit Muxes := 15 4 Input 112 Bit Muxes := 3 3 Input 76 Bit Muxes := 1 2 Input 65 Bit Muxes := 82 2 Input 64 Bit Muxes := 74 9 Input 64 Bit Muxes := 2 2 Input 48 Bit Muxes := 9 5 Input 48 Bit Muxes := 1 3 Input 42 Bit Muxes := 1 41 Input 41 Bit Muxes := 1 2 Input 41 Bit Muxes := 21 3 Input 38 Bit Muxes := 1 2 Input 36 Bit Muxes := 1 3 Input 36 Bit Muxes := 1 3 Input 34 Bit Muxes := 1 2 Input 32 Bit Muxes := 171 4 Input 32 Bit Muxes := 36 7 Input 32 Bit Muxes := 8 6 Input 32 Bit Muxes := 2 9 Input 32 Bit Muxes := 1 3 Input 32 Bit Muxes := 6 5 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 3 2 Input 26 Bit Muxes := 1 2 Input 24 Bit Muxes := 4 5 Input 24 Bit Muxes := 1 2 Input 20 Bit Muxes := 260 2 Input 19 Bit Muxes := 2 2 Input 17 Bit Muxes := 6 2 Input 16 Bit Muxes := 45 7 Input 16 Bit Muxes := 1 4 Input 16 Bit Muxes := 3 5 Input 16 Bit Muxes := 2 11 Input 16 Bit Muxes := 1 6 Input 16 Bit Muxes := 1 17 Input 16 Bit Muxes := 4 2 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 80 2 Input 13 Bit Muxes := 47 4 Input 13 Bit Muxes := 1 8 Input 13 Bit Muxes := 1 7 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 91 9 Input 12 Bit Muxes := 8 12 Input 12 Bit Muxes := 8 11 Input 11 Bit Muxes := 2 2 Input 11 Bit Muxes := 8 2 Input 10 Bit Muxes := 52 4 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 293 3 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 157 5 Input 8 Bit Muxes := 23 6 Input 8 Bit Muxes := 2 4 Input 8 Bit Muxes := 2 3 Input 8 Bit Muxes := 1 41 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 20 7 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 107 6 Input 6 Bit Muxes := 7 3 Input 6 Bit Muxes := 2 4 Input 6 Bit Muxes := 1 5 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 39 24 Input 5 Bit Muxes := 1 6 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 5 Input 5 Bit Muxes := 1 9 Input 4 Bit Muxes := 9 13 Input 4 Bit Muxes := 8 2 Input 4 Bit Muxes := 322 4 Input 4 Bit Muxes := 58 3 Input 4 Bit Muxes := 7 7 Input 4 Bit Muxes := 2 6 Input 4 Bit Muxes := 2 5 Input 4 Bit Muxes := 3 2 Input 3 Bit Muxes := 163 4 Input 3 Bit Muxes := 49 3 Input 3 Bit Muxes := 4 7 Input 3 Bit Muxes := 4 5 Input 3 Bit Muxes := 3 15 Input 3 Bit Muxes := 1 6 Input 3 Bit Muxes := 3 8 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 54 3 Input 2 Bit Muxes := 17 4 Input 2 Bit Muxes := 6 41 Input 2 Bit Muxes := 2 5 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 1498 7 Input 1 Bit Muxes := 56 9 Input 1 Bit Muxes := 79 3 Input 1 Bit Muxes := 51 4 Input 1 Bit Muxes := 82 6 Input 1 Bit Muxes := 74 12 Input 1 Bit Muxes := 8 8 Input 1 Bit Muxes := 11 11 Input 1 Bit Muxes := 14 41 Input 1 Bit Muxes := 23 18 Input 1 Bit Muxes := 7 5 Input 1 Bit Muxes := 7 13 Input 1 Bit Muxes := 9 16 Input 1 Bit Muxes := 8 17 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 1120 (col length:140) BRAMs: 1500 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3917] design top_efex_control has port i2c_rst_0 driven by constant 1 WARNING: [Synth 8-3917] design top_efex_control has port f5_user_led_1 driven by constant 1 WARNING: [Synth 8-3917] design top_efex_control has port ctrl_out[sk14] driven by constant 0 WARNING: [Synth 8-3917] design top_efex_control has port ctrl_out[sk15] driven by constant 0 INFO: [Synth 8-3971] The signal "\GOLDEN_IF.readout_packet_blocki_10 /\TOB_sources[1].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-3971] The signal "\GOLDEN_IF.readout_packet_blocki_11 /\TOB_sources[2].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\packet_tide_mark_block/tide_mark_procs[45].tide_mark_block.tide_mark_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\packet_tide_mark_block/tide_mark_procs[44].tide_mark_block.tide_mark_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mgt_bcn_error_count_bus_reg[7][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[0][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[0][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[1][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_bus_i_reg[1][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[0][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[0][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[1][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (U1_rdout_ipb_slave/\mux_orbit_active_watermark_bus_reg[1][15] ) INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3971] The signal "\TOB_sources[0].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_B/debug_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_B/debug_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_A/debug_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "tob_spy_A/debug_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM debug_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "\TOB_sources[3].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3886] merging instance 'ttc_fifos/ttc_veto_block_clk40.stretch_reg[15]' (FDS) to 'ttc_fifos/ttc_veto_clk40_reg' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[0]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[29]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[1]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[2]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[2]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[3]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[3]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[4]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[4]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[5]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[5]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[6]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[6]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[7]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[7]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[20]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[20]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[21]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[21]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[22]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[22]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[23]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[23]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[24]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[24]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[25]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[25]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[26]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[26]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[27]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[27]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[28]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[28]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[30]' INFO: [Synth 8-3886] merging instance 'tob_merge_B/TOB_Header_block.header_reg[30]' (FDE) to 'tob_merge_B/TOB_Header_block.header_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tob_merge_B/\TOB_Header_block.header_reg[31] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (tob_spy_A/\debug_spy/fifo_tready_i_reg ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (tob_spy_B/\debug_spy/fifo_tready_i_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[0].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3886] merging instance 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]' (FDE) to 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[2]' (FDE) to 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' (FDE) to 'TOB_sources[0].MGT_object/MGT_receiver/State_machine.trailer_info_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[0].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[3].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3886] merging instance 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[0]' (FDE) to 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[3]' (FDE) to 'TOB_sources[3].MGT_object/MGT_receiver/State_machine.trailer_info_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\TOB_sources[3].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[0]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[29]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[1]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[2]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[2]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[3]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[3]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[4]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[4]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[5]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[5]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[6]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[6]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[7]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[7]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[20]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[20]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[21]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[21]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[22]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[22]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[23]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[23]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[24]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[24]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[25]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[25]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[26]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[26]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[27]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[27]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[28]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[28]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[30]' INFO: [Synth 8-3886] merging instance 'tob_merge_A/TOB_Header_block.header_reg[30]' (FDE) to 'tob_merge_A/TOB_Header_block.header_reg[31]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (tob_merge_A/\TOB_Header_block.header_reg[31] ) INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'TOB_sources[1].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'TOB_sources[1].tob_fifo_A/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'TOB_sources[1].tob_fifo_A/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bulk_sources[1].MGT_object /\MGT_receiver/output_length_sig_reg[0] ) INFO: [Synth 8-3886] merging instance 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[0]' (FDE) to 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]' INFO: [Synth 8-3886] merging instance 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[2]' (FDE) to 'Bulk_sources[1].MGT_object/MGT_receiver/State_machine.trailer_info_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\Bulk_sources[1].MGT_object /\MGT_receiver/State_machine.trailer_info_reg[7] ) INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'Merged_FIFOs[1].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[3]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[3]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[4]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[4]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[5]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[5]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[6]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[6]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[7]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[7]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[8]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[8]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[9]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[9]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[10]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[10]' INFO: [Synth 8-3886] merging instance 'TOB_sources[0].tob_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[11]' (FD) to 'TOB_sources[0].tob_fifo_B/data_ram_fifo/new_read_ptr_reg[11]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[12]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[12]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[0]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[0]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[1]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[1]' INFO: [Synth 8-3886] merging instance 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/read_pointer_proc.NextAddr_reg[2]' (FD) to 'Merged_FIFOs[0].merged_fifo_B/data_ram_fifo/new_read_ptr_reg[2]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3332] Sequential element (TOB_sources[0].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[1].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[2].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[3].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_merger/FSM_onehot_state_reg[2]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (Debug_MUX/FSM_onehot_state_sig_reg[0]) is unused and will be removed from module efex_tob_merger__1. WARNING: [Synth 8-3332] Sequential element (TOB_sources[0].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_sources[1].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_sources[2].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_sources[3].tob_processer/Debug_packet_merger/FSM_onehot_state_reg[0]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (TOB_merger/FSM_onehot_state_reg[2]) is unused and will be removed from module efex_tob_merger. WARNING: [Synth 8-3332] Sequential element (Debug_MUX/FSM_onehot_state_sig_reg[0]) is unused and will be removed from module efex_tob_merger. INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Synth 8-4471] merging register 'spy_data_i_reg[31:0]' into 'MGT_receiver/data_from_mgt_fifo_sig_reg[31:0]' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/control_fpga/src/data_path/mgt_buffer.vhd:362] INFO: [Synth 8-3971] The signal "\Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 2 RAM instances of RAM IPbus_RAM/ram_reg to conserve power WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_sig_reg[0]) is unused and will be removed from module efex_packet_mux__parameterized1. WARNING: [Synth 8-3917] design packet_block__GCB4 has port ipbus_built_fifo_rbus_array[0][ipb_err] driven by constant 0 WARNING: [Synth 8-3917] design packet_block__GCB4 has port ipbus_built_fifo_rbus_array[1][ipb_err] driven by constant 0 INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg to conserve power INFO: [Synth 8-3971] The signal "packet_block__GCB4/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg" was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg to conserve power INFO: [Synth 8-3971] The signal "\infrastructure_control/spi_pll/spi_dpram_in/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power INFO: [Synth 8-3971] The signal "\infrastructure_control/spi_flash/spi_dpram_in/ram_reg " was recognized as a true dual port RAM template. INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM spi_dpram_in/ram_reg to conserve power INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "buf_to_load_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "buf_to_load_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "buf_to_load_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5587] ROM size for "addr_to_set_int" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "event_data" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ip_len_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ip_cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "udp_len_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "pay_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "ipbus_hdr_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5546] ROM "do_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clr_sum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "int_valid_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ip_len_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ip_cksum_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "udp_len_int" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "pay_len" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "ipbus_hdr_int" won't be mapped to Block RAM because address size (3) smaller than threshold (5) INFO: [Synth 8-5544] ROM "eFEX_mapping[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "eFEX_mapping[15]" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM internal_ram/ram_reg to conserve power INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM ram_reg to conserve power INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status_buffer/\header_reg[31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.IPAM_block /\dhcp_discover.dhcp_block.data_buffer_reg[7] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_5/udp_if /IPADDR/\dhcp_offer.MAC_IP_addr_rx_dhcp.pkt_mask_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.IPAM_block /\ipam_end_addr_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ARP /\arp_end_addr_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /payload/\do_cksum.payload_len_reg[14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\bigendian.unreliable_data_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.reliable_data_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\ipbus_pkt.pkt_data_reg[5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\littleendian.unreliable_data_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\primary_mode.ping.pkt_data_reg[5] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_5/udp_if /status_buffer/\header_reg[125] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status_buffer/\header_reg[119] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /tx_main/\default_mode.udp_build_data.pay_len_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /tx_main/\default_mode.udp_build_data.pay_len_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ping /\int_data_ping_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ping /\int_data_ping_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\resend.pkt_data_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ping /\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /\primary_mode.ARP /\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status/\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /status/\addr_to_set_reg[6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_7/parse_address.ip_addr_int_reg[7] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_5/udp_if /\primary_mode.IPAM_block /\ipam_req_block.req_end_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /tx_main/\state_machine.addr_to_set_int_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_7/mac_addr_reg[46] ) INFO: [Synth 8-3333] propagating constant 1 across sequential element (\U_0/U_7/mac_addr_reg[47] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /payload/\addr_to_set_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /payload/\addr_to_set_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/trans/sm/err_d_reg[3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\ipbus_pkt.pkt_data_reg[13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\bigendian.unreliable_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\primary_mode.ping.pkt_data_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\resend.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\ipbus_pkt.pkt_data_reg[21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\bigendian.unreliable_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\primary_mode.ping.pkt_data_reg[10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\bigendian.unreliable_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\U_0/U_5/udp_if /rx_packet_parser/\status_request.pkt_data_reg[11] ) INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_1/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_1/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_2/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_2/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-4471] merging register 'cntr_3/RESET_i_reg' into 'cntr_0/RESET_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:40] INFO: [Synth 8-4471] merging register 'cntr_3/enable2_i_reg' into 'cntr_0/enable2_i_reg' [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/process_Fpga_common/src/MGT/vhdl/counter.vhd:39] INFO: [Synth 8-3333] propagating constant 0 across sequential element (\l1a_stretch_block.reset_counter_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\GOLDEN_IF.mgt_slaves /quad_2/MGT_GT3/\cntr_3/enable1_i_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\GOLDEN_IF.mgt_slaves /quad_2/MGT_GT2/\cntr_3/enable1_i_reg ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\GOLDEN_IF.mgt_slaves /quad_2/MGT_GT1/\cntr_3/enable1_i_reg ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:40 ; elapsed = 00:01:56 . Memory (MB): peak = 2917.352 ; gain = 908.918 ; free physical = 4588 ; free virtual = 11987 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |\TOB_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[0].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[0].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[0].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[1].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[1].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_B | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_B | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\TOB_sources[1].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_A | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_A | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\TOB_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_10 /\TOB_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_11 /\TOB_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |top_efex_control | Bulk_sources[3].raw_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[0].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[2].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |ipbus_dpram_flash: | ram_reg | 16 x 32(READ_FIRST) | W | R | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_pll | spi_dpram_in/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |top_efex_control__GCB2 | infrastructure_control/RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | |\U_0/U_5/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |\TOB_sources[0].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[0].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[0].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[1].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Bulk_sources[3].raw_fifo_A/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[3].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control__GCB3 | U_0/U_0/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB3 | U_0/U_1/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB3 | U_0/U_2/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB3 | U_0/U_3/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:47 ; elapsed = 00:02:02 . Memory (MB): peak = 2928.430 ; gain = 919.996 ; free physical = 4318 ; free virtual = 11791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:02:26 ; elapsed = 00:02:44 . Memory (MB): peak = 3163.805 ; gain = 1155.371 ; free physical = 3749 ; free virtual = 11225 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |top_efex_control | TOB_sources[2].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\GOLDEN_IF.readout_packet_blocki_10 /\TOB_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |ipbus_dpram_flash: | ram_reg | 16 x 32(READ_FIRST) | W | R | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_pll | spi_dpram_in/ram_reg | 16 x 32(NO_CHANGE) | W | | 16 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_out/ram_reg | 128 x 32(READ_FIRST) | W | R | 128 x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\infrastructure_control/spi_flash | spi_dpram_in/ram_reg | 128 x 32(NO_CHANGE) | W | | 128 x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |top_efex_control__GCB2 | infrastructure_control/RAM/reg_reg | 1 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 1 | |\U_0/U_5/udp_if | internal_ram/ram_reg | 4 K x 8(READ_FIRST) | W | | 4 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram1_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram2_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram3_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if | ipbus_rx_ram/ram4_reg | 8 K x 8(NO_CHANGE) | W | | 8 K x 8(WRITE_FIRST) | | R | Port A and B | 0 | 2 | |\U_0/U_5/udp_if /ipbus_tx_ram | ram_reg | 8 K x 32(NO_CHANGE) | W | | 8 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 8 | |\TOB_sources[1].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[1].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[0].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[1].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\TOB_sources[0].tob_fifo_A | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[0].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\TOB_sources[0].tob_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Merged_FIFOs[1].merged_fifo_B | data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |tob_spy_B | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_B | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_A | debug_spy/IPbus_RAM/ram_bh_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |tob_spy_A | debug_spy/IPbus_RAM/ram_th_reg | 1 K x 32(NO_CHANGE) | W | | 1 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 1 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Bulk_sources[3].raw_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_ram_fifo/Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |packet_block__GCB4 | Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg | 4 K x 32(NO_CHANGE) | W | | 4 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 4 | |\Bulk_sources[0].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[1].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\GOLDEN_IF.readout_packet_blocki_11 /\TOB_sources[2].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | |\Bulk_sources[2].raw_ram_fifo | Memory_reg | 8 K x 65(READ_FIRST) | W | | 8 K x 65(WRITE_FIRST) | | R | Port A and B | 1 | 16 | |\Bulk_sources[3].MGT_object | IPbus_RAM/ram_reg | 2 K x 32(NO_CHANGE) | W | | 2 K x 32(READ_FIRST) | W | R | Port A and B | 0 | 2 | +-----------------------------------------------------------------+--------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Distributed RAM: Final Mapping Report +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ |top_efex_control | TOB_sources[2].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[2].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_B/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control__GCB3 | U_0/U_0/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB3 | U_0/U_1/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB3 | U_0/U_2/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |top_efex_control__GCB3 | U_0/U_3/U_2/fifo_proc.Memory_reg | Implied | 64 x 10 | RAM64X1D x 10 | |\TOB_sources[1].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[1].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[0].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[1].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[0].tob_fifo_A | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[0].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\TOB_sources[0].tob_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Merged_FIFOs[1].merged_fifo_B | data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | TOB_sources[3].tob_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[0].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Bulk_sources[3].raw_fifo_A/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |top_efex_control | Merged_FIFOs[1].merged_fifo_A/data_fifo/fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[3].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_A | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | |\Bulk_sources[2].raw_fifo_B | fifo_proc.Memory_reg | Implied | 16 x 65 | RAM16X1D x 65 | +--------------------------------+--------------------------------------------------------------+-----------+----------------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-5816] Retiming module `clocks_7s_extphy__GC0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `clocks_7s_extphy__GC0' done INFO: [Synth 8-5816] Retiming module `rdout_err_cnt` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `rdout_err_cnt' done INFO: [Synth 8-5816] Retiming module `packet_status_block__GB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_status_block__GB2' done INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized1' done INFO: [Synth 8-5816] Retiming module `packet_block__GCB1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_block__GCB1' done INFO: [Synth 8-5816] Retiming module `top_mgt_cfpga` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_mgt_cfpga' done INFO: [Synth 8-5816] Retiming module `ipbus_spi32` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ipbus_spi32' done INFO: [Synth 8-5816] Retiming module `ipbus_spi32__parameterized0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ipbus_spi32__parameterized0' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB2' done INFO: [Synth 8-5816] Retiming module `mgt_cntrl_slaves` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `mgt_cntrl_slaves' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB4` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB4' done INFO: [Synth 8-5816] Retiming module `top_efex_control_GT2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control_GT2' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance i_10/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_10/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_pll/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/infrastructure_control/RAM/reg_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-5816] Retiming module `packet_status_block__GB0_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `packet_status_block__GB0_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB0_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB0_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB3_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control__GCB3_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_3/U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-5816] Retiming module `ufc_controller__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ufc_controller__1' done INFO: [Synth 8-5816] Retiming module `ufc_controller` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ufc_controller' done INFO: [Synth 8-5816] Retiming module `top_cntrl_synch__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_cntrl_synch__1' done INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker__1' done INFO: [Synth 8-5816] Retiming module `top_cntrl_synch` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_cntrl_synch' done INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `cntrl_crc_checker' done INFO: [Synth 8-5816] Retiming module `aurora_hub2__xdcDup__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `aurora_hub2__xdcDup__1' done INFO: [Synth 8-5816] Retiming module `aurora_hub2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `aurora_hub2' done INFO: [Synth 8-5816] Retiming module `top_efex_control_GT0__1_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control_GT0__1_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized5` Numbers of forward move = 0, and backward move = 2 Retimed registers names: i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized5' done INFO: [Synth 8-5816] Retiming module `mgt_buffer` Numbers of forward move = 0, and backward move = 2 Retimed registers names: i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 INFO: [Synth 8-5816] Retiming module `mgt_buffer' done INFO: [Synth 8-5816] Retiming module `top_efex_control_GT0_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control_GT0_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_th_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_1/GOLDEN_IF.readout_packet_block/Packet_builders[1].built_fifo_spy/IPbus_RAM/ram_th_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. RETIMING: forward move fails for register i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret along load instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/i_55 RETIMING: forward move fails for register i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 along load instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/i_55 RETIMING: forward move fails for register i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 along load instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/i_55 RETIMING: forward move fails for register i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret along load instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/i_55 RETIMING: forward move fails for register i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 along load instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/i_55 RETIMING: forward move fails for register i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 along load instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/i_55 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized3` Numbers of forward move = 0, and backward move = 7 Retimed registers names: i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]_bret i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]_bret__0 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]_bret__1 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]_bret__2 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]_bret__3 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]_bret__4 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Errors_reg[1]_bret i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Length_Error_reg_bret i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Length_Error_reg_bret__0 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Length_Error_reg_bret__1 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Length_Error_reg_bret__2 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Length_Error_reg_bret__3 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.Length_Error_reg_bret__4 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]_bret i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]_bret__0 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/State_machine.trailer_info_reg[1]_bret__1 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__0 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__1 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__2 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__3 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret__4 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__0 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__1 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__2 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret__3 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__0 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__1 i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/MGT_receiver/Trailer_checker.write_block_reg_bret_bret__2 INFO: [Synth 8-5816] Retiming module `mgt_buffer__parameterized3' done WARNING: [Synth 8-3332] Sequential element (MGT_receiver/FSM_sequential_State_machine.next_state_reg[2]) is unused and will be removed from module mgt_buffer__parameterized3. WARNING: [Synth 8-3332] Sequential element (MGT_receiver/Trailer_checker.write_block_reg_bret) is unused and will be removed from module mgt_buffer__parameterized3. WARNING: [Synth 8-3332] Sequential element (MGT_receiver/Trailer_checker.TOB_trailer_OK_reg_bret) is unused and will be removed from module mgt_buffer__parameterized3. INFO: [Synth 8-5816] Retiming module `top_efex_control_GT1_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control_GT1_tempName' done INFO: [Synth 8-5816] Retiming module `top_efex_control` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `top_efex_control' done INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_9/GOLDEN_IF.readout_packet_block/Bulk_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:02:52 ; elapsed = 00:03:20 . Memory (MB): peak = 3199.754 ; gain = 1191.320 ; free physical = 3287 ; free virtual = 10772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[1].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_pll/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_pll/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_flash/spi_dpram_out/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/spi_flash/spi_dpram_in/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[3].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[0].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/TOB_sources[2].MGT_object/IPbus_RAM/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance infrastructure_control/RAM/reg_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/internal_ram/ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram2_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram2_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram3_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram3_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram4_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_rx_ram/ram4_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance U_0/U_5/udp_if/ipbus_tx_ram/ram_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_B/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_bh_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/tob_spy_A/debug_spy/IPbus_RAM/ram_th_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance GOLDEN_IF.readout_packet_block/Packet_builders[0].built_fifo_spy/IPbus_RAM/ram_bh_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:03:01 ; elapsed = 00:03:29 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10735 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:03:01 ; elapsed = 00:03:30 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:07 ; elapsed = 00:03:36 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10735 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:03:08 ; elapsed = 00:03:36 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:03:09 ; elapsed = 00:03:38 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:03:09 ; elapsed = 00:03:38 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +-----------------+-------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +-----------------+-------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top_cntrl_synch | temp2_reg | 3 | 2 | NO | NO | YES | 2 | 0 | |top_efex_control | GOLDEN_IF.readout_packet_block/TOB_sources[2].tob_fifo_B/data_ram_fifo/in_data_reg_reg[0] | 3 | 256 | NO | NO | YES | 256 | 0 | |top_efex_control | master_rx4_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | master_rx3_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | master_rx2_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | master_rx1_reg_reg[9] | 3 | 10 | NO | NO | NO | 10 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[44] | 37 | 1 | YES | NO | YES | 0 | 2 | |top_efex_control | U_0/U_5/udp_if/resend/resend_pkt_id_block.pkt_mask_reg[44] | 43 | 1 | YES | NO | YES | 0 | 2 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[33] | 6 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.arp.pkt_mask_reg[29] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_mask_reg[41] | 4 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[18] | 5 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.ping.pkt_mask_reg[35] | 23 | 1 | YES | NO | YES | 0 | 1 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[37] | 23 | 1 | YES | NO | YES | 0 | 1 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.arp.pkt_mask_reg[41] | 12 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.arp.pkt_mask_reg[19] | 8 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_mask_reg[75] | 12 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_mask_reg[60] | 8 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_mask_reg[51] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_mask_reg[30] | 25 | 1 | YES | NO | YES | 0 | 1 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ipbus_pkt.pkt_mask_reg[11] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_mask_reg[11] | 8 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[71] | 5 | 4 | YES | NO | YES | 4 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/ip_pkt.pkt_data_reg[59] | 4 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.arp.pkt_data_reg[111] | 10 | 4 | YES | NO | YES | 4 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.arp.pkt_data_reg[90] | 4 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/primary_mode.arp.pkt_data_reg[72] | 5 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_data_reg[135] | 11 | 2 | YES | NO | YES | 2 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_data_reg[129] | 5 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_data_reg[123] | 10 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_data_reg[106] | 4 | 1 | YES | NO | YES | 1 | 0 | |top_efex_control | U_0/U_5/udp_if/rx_packet_parser/dhcp_offer.dhcp.pkt_data_reg[100] | 7 | 1 | YES | NO | YES | 1 | 0 | +-----------------+-------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Retiming Report: +--------------------+----+ |Retiming summary: | | +--------------------+----+ |Forward Retiming | 0 | |Backward Retiming | 11 | |New registers added | 51 | |Registers deleted | 10 | +--------------------+----+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------------+----------+ | |BlackBox name |Instances | +------+--------------------+----------+ |1 |ila_0 | 3| |2 |axi_stream_fifo | 2| |3 |ila_1 | 5| |4 |clk_ttc | 1| |5 |mgt11g2_tx_rx_cfpga | 2| |6 |MGT_TX_RX_6G4 | 1| |7 |efex_aurora_hub2 | 2| |8 |mgt_axi_fifo | 8| |9 |fifo_40M_160M | 3| |10 |temac_gbe_v9_0 | 1| |11 |mac_fifo_axi4 | 1| +------+--------------------+----------+ Report Cell Usage: +------+---------------------------+------+ | |Cell |Count | +------+---------------------------+------+ |1 |MGT_TX_RX_6G4_bbox | 1| |2 |axi_stream_fifo_bbox | 2| |4 |clk_ttc_bbox | 1| |5 |efex_aurora_hub2_bbox | 1| |6 |efex_aurora_hub2_bbox_30 | 1| |7 |fifo_40M_160M_bbox | 3| |10 |ila_0_bbox | 3| |13 |ila_1_bbox | 5| |18 |mac_fifo_axi4_bbox | 1| |19 |mgt11g2_tx_rx_cfpga_bbox | 1| |20 |mgt11g2_tx_rx_cfpga_bbox_4 | 1| |21 |mgt_axi_fifo_bbox | 8| |29 |temac_gbe_v9_0_bbox | 1| |30 |BUFG | 13| |31 |BUFH | 10| |32 |CARRY4 | 3390| |33 |GTHE2_COMMON | 7| |34 |IBUFDS_GTE2 | 5| |35 |ICAPE2 | 1| |36 |IDELAYCTRL | 1| |37 |LUT1 | 683| |38 |LUT2 | 3277| |39 |LUT3 | 2841| |40 |LUT4 | 4810| |41 |LUT5 | 5460| |42 |LUT6 | 13433| |43 |MMCME2_BASE | 1| |44 |MUXF7 | 569| |45 |MUXF8 | 7| |46 |RAM16X1D | 1300| |47 |RAM64X1D | 40| |48 |RAMB18E1 | 16| |49 |RAMB36E1 | 314| |59 |SRL16 | 1| |60 |SRL16E | 398| |61 |SRLC32E | 217| |62 |STARTUPE2 | 1| |63 |XADC | 1| |64 |FDCE | 152| |65 |FDPE | 63| |66 |FDRE | 49490| |67 |FDSE | 1351| |68 |IBUF | 112| |69 |IBUFGDS | 1| |70 |IOBUF | 1| |71 |OBUF | 267| |72 |OBUFDS | 16| +------+---------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:03:09 ; elapsed = 00:03:38 . Memory (MB): peak = 3249.973 ; gain = 1241.539 ; free physical = 3193 ; free virtual = 10734 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 128 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:03:02 ; elapsed = 00:03:33 . Memory (MB): peak = 3253.887 ; gain = 1085.797 ; free physical = 5312 ; free virtual = 12853 Synthesis Optimization Complete : Time (s): cpu = 00:03:11 ; elapsed = 00:03:43 . Memory (MB): peak = 3253.887 ; gain = 1245.453 ; free physical = 5323 ; free virtual = 12849 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.62 . Memory (MB): peak = 3253.887 ; gain = 0.000 ; free physical = 5320 ; free virtual = 12847 INFO: [Netlist 29-17] Analyzing 5658 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-140] Inserted 2 IBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3378.566 ; gain = 0.000 ; free physical = 5183 ; free virtual = 12722 INFO: [Project 1-111] Unisim Transformation Summary: A total of 1360 instances were transformed. IBUFGDS => IBUFDS: 1 instance IOBUF => IOBUF (IBUF, OBUFT): 1 instance MMCME2_BASE => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 16 instances RAM16X1D => RAM32X1D (RAMD32(x2)): 1300 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 40 instances SRL16 => SRL16E: 1 instance Synth Design complete | Checksum: 23434c8c INFO: [Common 17-83] Releasing license: Synthesis 1241 Infos, 490 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:03:30 ; elapsed = 00:04:03 . Memory (MB): peak = 3378.566 ; gain = 1725.848 ; free physical = 5183 ; free virtual = 12722 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 4735.094; main = 2639.803; forked = 2340.331 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 7095.680; main = 3378.570; forked = 3845.703 Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3378.566 ; gain = 0.000 ; free physical = 5063 ; free virtual = 12719 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_control/efex_control.runs/synth_1/top_efex_control.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3378.566 ; gain = 0.000 ; free physical = 5133 ; free virtual = 12715 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_control_utilization_synth.rpt -pb top_efex_control_utilization_synth.pb source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-synthesis.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_control... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_control clean. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_control-v1.7.3-EA29254... INFO: [Hog:Msg-0] All done. INFO: [Common 17-206] Exiting Vivado at Mon Nov 10 19:38:26 2025...