*** Running vivado with args -log ClockWizard.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ClockWizard.tcl ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Mon Nov 10 21:22:41 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source ClockWizard.tcl -notrace INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ClockWizard Command: synth_design -top ClockWizard -part xc7vx550tffg1927-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 4596 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2400.031 ; gain = 427.797 ; free physical = 22746 ; free virtual = 43918 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'ClockWizard' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.v:68] INFO: [Synth 8-6157] synthesizing module 'ClockWizard_clk_wiz' [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_clk_wiz.v:68] INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:75840] INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:75840] INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:84588] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 35.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 24.938000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 7.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT1_DIVIDE bound to: 35 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.114000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 35 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:84588] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:2676] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/opt/Xilinx/Vivado/2024.2/scripts/rt/data/unisim_comp.v:2676] INFO: [Synth 8-6155] done synthesizing module 'ClockWizard_clk_wiz' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_clk_wiz.v:68] INFO: [Synth 8-6155] done synthesizing module 'ClockWizard' (0#1) [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.v:68] WARNING: [Synth 8-3301] Unused top level parameter/generic TAU_ALGO_VERSION WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_DATE WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_TIME WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_VER WARNING: [Synth 8-3301] Unused top level parameter/generic GLOBAL_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic HOG_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_VER WARNING: [Synth 8-3301] Unused top level parameter/generic CON_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic XML_VER WARNING: [Synth 8-3301] Unused top level parameter/generic XML_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic TOB_RDOUT_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic TOB_RDOUT_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic ALGOLIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic ALGOLIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic INFRASTRUCTURE_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic INFRASTRUCTURE_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPS_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_VER WARNING: [Synth 8-3301] Unused top level parameter/generic IPBUS_LIB_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic USR_IP_VER WARNING: [Synth 8-3301] Unused top level parameter/generic USR_IP_SHA WARNING: [Synth 8-3301] Unused top level parameter/generic FLAVOUR --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2475.000 ; gain = 502.766 ; free physical = 22668 ; free virtual = 43841 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2489.844 ; gain = 517.609 ; free physical = 22668 ; free virtual = 43840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2489.844 ; gain = 517.609 ; free physical = 22668 ; free virtual = 43840 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2495.781 ; gain = 0.000 ; free physical = 22664 ; free virtual = 43837 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_ooc.xdc] for cell 'inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ClockWizard_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ClockWizard_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.2/efex_hi_processor.2.runs/ClockWizard_synth_1/dont_touch.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.2/efex_hi_processor.2.runs/ClockWizard_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2565.750 ; gain = 0.000 ; free physical = 22684 ; free virtual = 43857 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2565.750 ; gain = 0.000 ; free physical = 22684 ; free virtual = 43857 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2565.750 ; gain = 593.516 ; free physical = 22727 ; free virtual = 43900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7vx550tffg1927-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2573.754 ; gain = 601.520 ; free physical = 22727 ; free virtual = 43900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property keep_hierarchy = soft for inst. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc, line 53). Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.2/efex_hi_processor.2.runs/ClockWizard_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2573.754 ; gain = 601.520 ; free physical = 22727 ; free virtual = 43900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2573.754 ; gain = 601.520 ; free physical = 22723 ; free virtual = 43897 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 2880 (col length:200) BRAMs: 2360 (col length: RAMB18 200 RAMB36 100) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2573.754 ; gain = 601.520 ; free physical = 22731 ; free virtual = 43904 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2646.754 ; gain = 674.520 ; free physical = 22670 ; free virtual = 43844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2646.754 ; gain = 674.520 ; free physical = 22670 ; free virtual = 43844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2655.770 ; gain = 683.535 ; free physical = 22662 ; free virtual = 43836 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |BUFG | 5| |2 |MMCME2_ADV | 1| |3 |IBUFDS | 1| +------+-----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.582 ; gain = 845.348 ; free physical = 22536 ; free virtual = 43710 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2817.582 ; gain = 769.441 ; free physical = 22529 ; free virtual = 43703 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2817.590 ; gain = 845.348 ; free physical = 22529 ; free virtual = 43703 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.590 ; gain = 0.000 ; free physical = 22532 ; free virtual = 43706 INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.590 ; gain = 0.000 ; free physical = 22705 ; free virtual = 43879 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: af86ab6a INFO: [Common 17-83] Releasing license: Synthesis 31 Infos, 27 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 2817.590 ; gain = 1318.363 ; free physical = 22705 ; free virtual = 43879 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2243.034; main = 2019.669; forked = 277.398 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3702.582; main = 2817.586; forked = 908.809 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.594 ; gain = 0.000 ; free physical = 22705 ; free virtual = 43879 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.2/efex_hi_processor.2.runs/ClockWizard_synth_1/ClockWizard.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ClockWizard, cache-ID = 96d76e88a27dbc33 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.621 ; gain = 0.000 ; free physical = 22694 ; free virtual = 43868 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.2/efex_hi_processor.2.runs/ClockWizard_synth_1/ClockWizard.dcp' has been generated. INFO: [Vivado 12-24828] Executing command : report_utilization -file ClockWizard_utilization_synth.rpt -pb ClockWizard_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Mon Nov 10 21:23:22 2025...