*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Mon Nov 10 23:16:05 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2932.211 ; gain = 7.000 ; free physical = 25422 ; free virtual = 45561 INFO: [Netlist 29-17] Analyzing 29749 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'FIFO_209b_512'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] get_clocks: Time (s): cpu = 00:00:30 ; elapsed = 00:00:14 . Memory (MB): peak = 4756.207 ; gain = 1127.625 ; free physical = 23771 ; free virtual = 43910 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:54] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[15].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay2'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga3.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga3.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1714] 112 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5480.262 ; gain = 0.000 ; free physical = 23057 ; free virtual = 43197 INFO: [Project 1-111] Unisim Transformation Summary: A total of 66 instances were transformed. OBUFDS => OBUFDS: 66 instances 33 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:51 ; elapsed = 00:02:03 . Memory (MB): peak = 5480.262 ; gain = 3981.066 ; free physical = 23057 ; free virtual = 43197 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5488.266 ; gain = 0.000 ; free physical = 23050 ; free virtual = 43190 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 112ad71f4 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 5645.266 ; gain = 157.000 ; free physical = 22855 ; free virtual = 42995 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 112ad71f4 Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.49 . Memory (MB): peak = 6001.031 ; gain = 0.000 ; free physical = 22510 ; free virtual = 42650 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 112ad71f4 Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.64 . Memory (MB): peak = 6001.031 ; gain = 0.000 ; free physical = 22510 ; free virtual = 42650 Phase 1 Initialization | Checksum: 112ad71f4 Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.7 . Memory (MB): peak = 6001.031 ; gain = 0.000 ; free physical = 22510 ; free virtual = 42650 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 112ad71f4 Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6001.031 ; gain = 0.000 ; free physical = 22500 ; free virtual = 42640 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 112ad71f4 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 6193.031 ; gain = 192.000 ; free physical = 22358 ; free virtual = 42499 Phase 2 Timer Update And Timing Data Collection | Checksum: 112ad71f4 Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 6193.031 ; gain = 192.000 ; free physical = 22358 ; free virtual = 42499 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 4 inverters resulting in an inversion of 31 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1ba4a5bde Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 6193.031 ; gain = 192.000 ; free physical = 22365 ; free virtual = 42506 Retarget | Checksum: 1ba4a5bde INFO: [Opt 31-389] Phase Retarget created 159 cells and removed 538 cells INFO: [Opt 31-1021] In phase Retarget, 225 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1541c1636 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 6193.031 ; gain = 192.000 ; free physical = 22365 ; free virtual = 42505 Constant propagation | Checksum: 1541c1636 INFO: [Opt 31-389] Phase Constant propagation created 38 cells and removed 177 cells INFO: [Opt 31-1021] In phase Constant propagation, 157 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6193.031 ; gain = 0.000 ; free physical = 22364 ; free virtual = 42504 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 6193.031 ; gain = 0.000 ; free physical = 22363 ; free virtual = 42504 Phase 5 Sweep | Checksum: e1c0dffe Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 6193.031 ; gain = 192.000 ; free physical = 22361 ; free virtual = 42502 Sweep | Checksum: e1c0dffe INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3377 cells INFO: [Opt 31-1021] In phase Sweep, 900 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 6 BUFG optimization | Checksum: f2a092c4 Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22360 ; free virtual = 42501 BUFG optimization | Checksum: f2a092c4 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: f2a092c4 Time (s): cpu = 00:00:33 ; elapsed = 00:00:31 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22360 ; free virtual = 42500 Shift Register Optimization | Checksum: f2a092c4 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1089c0b1f Time (s): cpu = 00:00:35 ; elapsed = 00:00:32 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22360 ; free virtual = 42500 Post Processing Netlist | Checksum: 1089c0b1f INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 300 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 18d0bf620 Time (s): cpu = 00:00:43 ; elapsed = 00:00:40 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22358 ; free virtual = 42499 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.57 . Memory (MB): peak = 6225.047 ; gain = 0.000 ; free physical = 22358 ; free virtual = 42498 Phase 9.2 Verifying Netlist Connectivity | Checksum: 18d0bf620 Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22358 ; free virtual = 42498 Phase 9 Finalization | Checksum: 18d0bf620 Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22358 ; free virtual = 42498 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 159 | 538 | 225 | | Constant propagation | 38 | 177 | 157 | | Sweep | 0 | 3377 | 900 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 300 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 18d0bf620 Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 6225.047 ; gain = 224.016 ; free physical = 22358 ; free virtual = 42498 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 788 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 97 newly gated: 186 Total Ports: 1576 Ending PowerOpt Patch Enables Task | Checksum: 1689e2b16 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19228 ; free virtual = 39369 Ending Power Optimization Task | Checksum: 1689e2b16 Time (s): cpu = 00:02:53 ; elapsed = 00:02:18 . Memory (MB): peak = 9443.879 ; gain = 3218.832 ; free physical = 19229 ; free virtual = 39370 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 29d785a9c Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19205 ; free virtual = 39347 Ending Final Cleanup Task | Checksum: 29d785a9c Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19205 ; free virtual = 39347 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19205 ; free virtual = 39347 Ending Netlist Obfuscation Task | Checksum: 29d785a9c Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19205 ; free virtual = 39347 INFO: [Common 17-83] Releasing license: Implementation 72 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:42 ; elapsed = 00:04:06 . Memory (MB): peak = 9443.879 ; gain = 3963.617 ; free physical = 19205 ; free virtual = 39346 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.3/efex_hi_processor.3.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19189 ; free virtual = 39331 generate_parallel_reports: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19189 ; free virtual = 39331 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.45 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39299 Wrote PlaceDB: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.12 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39301 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39301 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.57 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39301 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39301 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39303 Write Physdb Complete: Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.71 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18793 ; free virtual = 39303 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.3/efex_hi_processor.3.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18954 ; free virtual = 39176 Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19052 ; free virtual = 39274 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a1aecc7f Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19054 ; free virtual = 39277 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19054 ; free virtual = 39277 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 111596df5 Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19075 ; free virtual = 39297 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: c3a60bca Time (s): cpu = 00:02:18 ; elapsed = 00:02:19 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19033 ; free virtual = 39256 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: c3a60bca Time (s): cpu = 00:02:19 ; elapsed = 00:02:20 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19032 ; free virtual = 39255 Phase 1 Placer Initialization | Checksum: c3a60bca Time (s): cpu = 00:02:20 ; elapsed = 00:02:21 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19027 ; free virtual = 39251 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1384f2ea2 Time (s): cpu = 00:02:46 ; elapsed = 00:02:47 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19036 ; free virtual = 39260 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 10151e325 Time (s): cpu = 00:03:06 ; elapsed = 00:03:07 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19039 ; free virtual = 39263 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 172286858 Time (s): cpu = 00:03:07 ; elapsed = 00:03:08 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19039 ; free virtual = 39263 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 1431d12f3 Time (s): cpu = 00:06:23 ; elapsed = 00:06:24 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19041 ; free virtual = 39268 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: df678598 Time (s): cpu = 00:06:48 ; elapsed = 00:06:50 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19037 ; free virtual = 39264 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 40 LUTNM shape to break, 14085 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 35, two critical 5, total 40, new lutff created 5 INFO: [Physopt 32-1138] End 1 Pass. Optimized 6784 nets or LUTs. Breaked 40 LUTs, combined 6744 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-1408] Pass 1. Identified 21 candidate nets for high-fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg_n_1_[10]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 67 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/IN_Load. Replicated 77 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start. Replicated 28 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/SR[0]. Replicated 17 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 8 times. INFO: [Physopt 32-232] Optimized 21 nets. Created 305 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 21 nets or cells. Created 305 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19035 ; free virtual = 39263 INFO: [Physopt 32-76] Pass 1. Identified 38 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[14]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[0]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1046[0]. Replicated 7 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1046[2]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[10]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[9]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[12]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[14]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[7]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1046[5]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1066[5]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1067[2]. Replicated 6 times. INFO: [Physopt 32-232] Optimized 28 nets. Created 233 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 28 nets or cells. Created 233 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.73 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39267 INFO: [Physopt 32-46] Identified 14 candidate nets for critical-cell optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[2]_rep_n_1. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[8]_rep_n_1. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[7]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[2]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[0]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[4]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[9]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[3]. Replicated 1 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[5]. Replicated 1 times. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[1]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[1] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[6] was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly[8] was not replicated. INFO: [Physopt 32-232] Optimized 9 nets. Created 9 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 9 nets or cells. Created 9 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19041 ; free virtual = 39268 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1402] Pass 1: Identified 31 candidate cells for Shift Register optimization. INFO: [Physopt 32-775] End 1 Pass. Optimized 15 nets or cells. Created 19 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19043 ; free virtual = 39270 INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19042 ; free virtual = 39269 INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19042 ; free virtual = 39269 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 40 | 6744 | 6784 | 0 | 1 | 00:00:08 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 305 | 0 | 21 | 0 | 1 | 00:00:10 | | Fanout | 233 | 0 | 28 | 0 | 1 | 00:00:04 | | Critical Cell | 9 | 0 | 9 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 19 | 0 | 15 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 606 | 6744 | 6857 | 0 | 12 | 00:00:23 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: e3f26272 Time (s): cpu = 00:07:39 ; elapsed = 00:07:42 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19043 ; free virtual = 39271 Phase 2.5 Global Place Phase2 | Checksum: 205b9ca9b Time (s): cpu = 00:07:51 ; elapsed = 00:07:53 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39268 Phase 2 Global Placement | Checksum: 205b9ca9b Time (s): cpu = 00:07:51 ; elapsed = 00:07:53 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39268 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ace3ccd2 Time (s): cpu = 00:08:17 ; elapsed = 00:08:19 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39268 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2708c7648 Time (s): cpu = 00:09:16 ; elapsed = 00:09:18 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19041 ; free virtual = 39270 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2686c860e Time (s): cpu = 00:09:20 ; elapsed = 00:09:22 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39269 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 22382bc5f Time (s): cpu = 00:09:21 ; elapsed = 00:09:23 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39269 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 226448968 Time (s): cpu = 00:10:22 ; elapsed = 00:10:25 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19042 ; free virtual = 39271 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 22d766e7b Time (s): cpu = 00:12:03 ; elapsed = 00:12:06 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19044 ; free virtual = 39274 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 216410a3e Time (s): cpu = 00:12:16 ; elapsed = 00:12:19 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19041 ; free virtual = 39272 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1e14d7bb6 Time (s): cpu = 00:12:22 ; elapsed = 00:12:24 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19040 ; free virtual = 39271 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 26b261bed Time (s): cpu = 00:13:55 ; elapsed = 00:13:58 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19809 ; free virtual = 40041 Phase 3 Detail Placement | Checksum: 26b261bed Time (s): cpu = 00:13:57 ; elapsed = 00:14:00 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19809 ; free virtual = 40041 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 25a4c376e Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.460 | TNS=-12.057 | Phase 1 Physical Synthesis Initialization | Checksum: 2497bac19 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19722 ; free virtual = 39954 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 29d3ead83 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19726 ; free virtual = 39958 Phase 4.1.1.1 BUFG Insertion | Checksum: 25a4c376e Time (s): cpu = 00:15:54 ; elapsed = 00:15:58 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19726 ; free virtual = 39958 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.058. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d6fba2ee Time (s): cpu = 00:18:03 ; elapsed = 00:18:08 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19727 ; free virtual = 39961 Time (s): cpu = 00:18:03 ; elapsed = 00:18:08 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19727 ; free virtual = 39961 Phase 4.1 Post Commit Optimization | Checksum: 1d6fba2ee Time (s): cpu = 00:18:06 ; elapsed = 00:18:11 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19727 ; free virtual = 39961 Post Placement Optimization Initialization | Checksum: 26a925145 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.442 | TNS=-11.184 | Phase 1 Physical Synthesis Initialization | Checksum: 22a1bd5b2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19453 ; free virtual = 39688 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 2cce49dc1 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19453 ; free virtual = 39688 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.064. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 1487f6e49 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.064 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 197844332 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19452 ; free virtual = 39690 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 23d694d45 Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19452 ; free virtual = 39690 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.071. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2208e554e Time (s): cpu = 00:26:46 ; elapsed = 00:26:53 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19447 ; free virtual = 39685 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 16x16| 8x8| |___________|___________________|___________________| | South| 16x16| 8x8| |___________|___________________|___________________| | East| 16x16| 4x4| |___________|___________________|___________________| | West| 8x8| 8x8| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 2208e554e Time (s): cpu = 00:26:49 ; elapsed = 00:26:55 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19446 ; free virtual = 39684 Phase 4.3 Placer Reporting | Checksum: 2208e554e Time (s): cpu = 00:26:51 ; elapsed = 00:26:58 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19446 ; free virtual = 39684 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19446 ; free virtual = 39684 Time (s): cpu = 00:26:52 ; elapsed = 00:26:58 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19446 ; free virtual = 39684 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c02c1ea6 Time (s): cpu = 00:26:54 ; elapsed = 00:27:00 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19446 ; free virtual = 39684 Ending Placer Task | Checksum: fb0ddb86 Time (s): cpu = 00:26:56 ; elapsed = 00:27:03 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19449 ; free virtual = 39687 197 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:27:16 ; elapsed = 00:27:22 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19449 ; free virtual = 39687 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.63 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19438 ; free virtual = 39677 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:01 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19403 ; free virtual = 39644 generate_parallel_reports: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19403 ; free virtual = 39643 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.76 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19056 ; free virtual = 39681 Wrote PlaceDB: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18743 ; free virtual = 39665 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18743 ; free virtual = 39665 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.55 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18743 ; free virtual = 39665 Wrote Netlist Cache: Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.33 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18712 ; free virtual = 39664 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18712 ; free virtual = 39666 Write Physdb Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18712 ; free virtual = 39666 report_design_analysis: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18701 ; free virtual = 39657 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.3/efex_hi_processor.3.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:16 ; elapsed = 00:01:20 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19306 ; free virtual = 39660 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Starting Initial Update Timing Task Time (s): cpu = 00:01:08 ; elapsed = 00:01:08 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19319 ; free virtual = 39674 INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.071 | TNS= 0.000 | INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 209 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:10 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19319 ; free virtual = 39674 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.72 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18934 ; free virtual = 39674 Wrote PlaceDB: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18642 ; free virtual = 39678 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18642 ; free virtual = 39678 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.56 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18642 ; free virtual = 39679 Wrote Netlist Cache: Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.33 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18607 ; free virtual = 39674 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18607 ; free virtual = 39675 Write Physdb Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 18607 ; free virtual = 39675 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.3/efex_hi_processor.3.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:51 . Memory (MB): peak = 9443.879 ; gain = 0.000 ; free physical = 19178 ; free virtual = 39647 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: 6e1ab1df ConstDB: 0 ShapeSum: 39ce7814 RouteDB: 5324b193 Post Restoration Checksum: NetGraph: 87343efc | NumContArr: bc687695 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2c8eeaacb Time (s): cpu = 00:02:01 ; elapsed = 00:02:02 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 19165 ; free virtual = 39634 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2c8eeaacb Time (s): cpu = 00:02:04 ; elapsed = 00:02:04 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 19165 ; free virtual = 39634 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2c8eeaacb Time (s): cpu = 00:02:05 ; elapsed = 00:02:06 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 19165 ; free virtual = 39634 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2763f000f Time (s): cpu = 00:04:05 ; elapsed = 00:04:06 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18969 ; free virtual = 39440 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.053 | TNS=-0.103 | WHS=-0.493 | THS=-11279.287| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 1f24eb7df Time (s): cpu = 00:05:28 ; elapsed = 00:05:29 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18948 ; free virtual = 39419 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.053 | TNS=-0.101 | WHS=-0.516 | THS=-3187.322| Phase 2.4 Update Timing for Bus Skew | Checksum: 2006b2f39 Time (s): cpu = 00:05:29 ; elapsed = 00:05:30 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18948 ; free virtual = 39419 Router Utilization Summary Global Vertical Routing Utilization = 9.6353e-05 % Global Horizontal Routing Utilization = 0.000117962 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 424490 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 424488 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 25756276c Time (s): cpu = 00:05:35 ; elapsed = 00:05:36 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18924 ; free virtual = 39395 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 25756276c Time (s): cpu = 00:05:35 ; elapsed = 00:05:36 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18924 ; free virtual = 39395 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 233f64730 Time (s): cpu = 00:07:48 ; elapsed = 00:07:50 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18982 ; free virtual = 39405 Phase 4 Initial Routing | Checksum: 233f64730 Time (s): cpu = 00:07:50 ; elapsed = 00:07:51 . Memory (MB): peak = 9451.879 ; gain = 8.000 ; free physical = 18982 ; free virtual = 39405 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 37098 Number of Nodes with overlaps = 3041 Number of Nodes with overlaps = 681 Number of Nodes with overlaps = 162 Number of Nodes with overlaps = 51 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.157 | TNS=-0.407 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 31c79c1ca Time (s): cpu = 00:15:38 ; elapsed = 00:15:41 . Memory (MB): peak = 9650.496 ; gain = 206.617 ; free physical = 18681 ; free virtual = 39108 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 1866 Number of Nodes with overlaps = 405 Number of Nodes with overlaps = 148 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.016 | TNS=-0.016 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 243b62b4c Time (s): cpu = 00:17:13 ; elapsed = 00:17:15 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18652 ; free virtual = 39079 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 1181 Number of Nodes with overlaps = 209 Number of Nodes with overlaps = 90 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.016 | TNS=-0.016 | WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 278faad69 Time (s): cpu = 00:18:26 ; elapsed = 00:18:28 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18668 ; free virtual = 39096 Phase 5 Rip-up And Reroute | Checksum: 278faad69 Time (s): cpu = 00:18:27 ; elapsed = 00:18:29 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18670 ; free virtual = 39098 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 27acfbe72 Time (s): cpu = 00:18:53 ; elapsed = 00:18:55 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18669 ; free virtual = 39098 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.016 | TNS=-0.016 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 6.1 Delay CleanUp | Checksum: 247512e07 Time (s): cpu = 00:18:57 ; elapsed = 00:18:59 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18670 ; free virtual = 39099 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 247512e07 Time (s): cpu = 00:18:58 ; elapsed = 00:19:00 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18668 ; free virtual = 39097 Phase 6 Delay and Skew Optimization | Checksum: 247512e07 Time (s): cpu = 00:18:59 ; elapsed = 00:19:01 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18668 ; free virtual = 39097 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.016 | TNS=-0.016 | WHS=0.008 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 1ffed41ea Time (s): cpu = 00:19:28 ; elapsed = 00:19:30 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18671 ; free virtual = 39100 Phase 7 Post Hold Fix | Checksum: 1ffed41ea Time (s): cpu = 00:19:29 ; elapsed = 00:19:31 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18670 ; free virtual = 39099 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 2add15da1 Time (s): cpu = 00:20:09 ; elapsed = 00:20:12 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18667 ; free virtual = 39096 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.016 | TNS=-0.016 | WHS=0.008 | THS=0.000 | Phase 8 Timing Verification | Checksum: 2add15da1 Time (s): cpu = 00:20:10 ; elapsed = 00:20:13 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18667 ; free virtual = 39096 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 27.2606 % Global Horizontal Routing Utilization = 27.246 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 8x8 Area, Max Cong = 85.7123%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X96Y252 -> INT_R_X103Y259 South Dir 2x2 Area, Max Cong = 92.7928%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X56Y322 -> INT_R_X57Y323 INT_L_X46Y306 -> INT_R_X47Y307 INT_L_X46Y304 -> INT_R_X47Y305 INT_L_X42Y302 -> INT_R_X43Y303 INT_L_X44Y302 -> INT_R_X45Y303 East Dir 4x4 Area, Max Cong = 86.9485%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X52Y360 -> INT_R_X55Y363 INT_L_X40Y356 -> INT_R_X43Y359 West Dir 4x4 Area, Max Cong = 85.6618%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X48Y300 -> INT_R_X51Y303 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 2 Effective congestion level: 4 Aspect Ratio: 0.833333 Sparse Ratio: 1 Direction: South ---------------- Congested clusters found at Level 1 Effective congestion level: 3 Aspect Ratio: 1 Sparse Ratio: 0.6875 Direction: East ---------------- Congested clusters found at Level 2 Effective congestion level: 4 Aspect Ratio: 0.5 Sparse Ratio: 0.5625 Direction: West ---------------- Congested clusters found at Level 2 Effective congestion level: 3 Aspect Ratio: 0.5 Sparse Ratio: 0.5 Phase 9 Route finalize | Checksum: 2add15da1 Time (s): cpu = 00:20:12 ; elapsed = 00:20:15 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18670 ; free virtual = 39099 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 2add15da1 Time (s): cpu = 00:20:13 ; elapsed = 00:20:16 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18669 ; free virtual = 39098 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 24ea8beb5 Time (s): cpu = 00:20:40 ; elapsed = 00:20:43 . Memory (MB): peak = 9666.863 ; gain = 222.984 ; free physical = 18664 ; free virtual = 39094 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9666.863 ; gain = 0.000 ; free physical = 18662 ; free virtual = 39091 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.171. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 660f1024 Time (s): cpu = 00:03:42 ; elapsed = 00:03:44 . Memory (MB): peak = 10291.395 ; gain = 624.531 ; free physical = 17988 ; free virtual = 38419 Phase 12 Incr Placement Change | Checksum: 660f1024 Time (s): cpu = 00:24:31 ; elapsed = 00:24:35 . Memory (MB): peak = 10291.395 ; gain = 847.516 ; free physical = 17988 ; free virtual = 38419 Phase 13 Build RT Design Checksum: PlaceDB: 4c814ec3 ConstDB: 0 ShapeSum: a6868b0 RouteDB: f2558b1 Post Restoration Checksum: NetGraph: ba769ed | NumContArr: 665a1b75 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 13 Build RT Design | Checksum: 1f7537a9c Time (s): cpu = 00:25:53 ; elapsed = 00:25:57 . Memory (MB): peak = 10291.395 ; gain = 847.516 ; free physical = 17986 ; free virtual = 38418 Phase 14 Router Initialization Phase 14.1 Fix Topology Constraints Phase 14.1 Fix Topology Constraints | Checksum: 1f7537a9c Time (s): cpu = 00:25:57 ; elapsed = 00:26:01 . Memory (MB): peak = 10291.395 ; gain = 847.516 ; free physical = 17986 ; free virtual = 38418 Phase 14.2 Pre Route Cleanup Phase 14.2 Pre Route Cleanup | Checksum: 346712f8b Time (s): cpu = 00:26:00 ; elapsed = 00:26:03 . Memory (MB): peak = 10291.395 ; gain = 847.516 ; free physical = 17986 ; free virtual = 38418 Number of Nodes with overlaps = 0 Phase 14.3 Update Timing Phase 14.3 Update Timing | Checksum: 24404e8ce Time (s): cpu = 00:28:09 ; elapsed = 00:28:13 . Memory (MB): peak = 10291.395 ; gain = 847.516 ; free physical = 17978 ; free virtual = 38411 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.493 | THS=-11214.942| Phase 14.4 Update Timing for Bus Skew Phase 14.4.1 Update Timing Phase 14.4.1 Update Timing | Checksum: 22e55c225 Time (s): cpu = 00:29:22 ; elapsed = 00:29:26 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17962 ; free virtual = 38397 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.096 | TNS=0.000 | WHS=-0.231 | THS=-2.350 | Phase 14.4 Update Timing for Bus Skew | Checksum: 1a199d79f Time (s): cpu = 00:29:23 ; elapsed = 00:29:27 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17969 ; free virtual = 38404 Router Utilization Summary Global Vertical Routing Utilization = 27.2064 % Global Horizontal Routing Utilization = 27.2288 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 449 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 294 Number of Partially Routed Nets = 155 Number of Node Overlaps = 0 Phase 14 Router Initialization | Checksum: 1ee2d56ae Time (s): cpu = 00:29:29 ; elapsed = 00:29:33 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17969 ; free virtual = 38404 Phase 15 Global Routing Phase 15 Global Routing | Checksum: 1ee2d56ae Time (s): cpu = 00:29:29 ; elapsed = 00:29:34 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17969 ; free virtual = 38404 Phase 16 Initial Routing Phase 16.1 Initial Net Routing Pass Phase 16.1 Initial Net Routing Pass | Checksum: 2dc8bc893 Time (s): cpu = 00:29:37 ; elapsed = 00:29:41 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17972 ; free virtual = 38407 Phase 16 Initial Routing | Checksum: 2dc8bc893 Time (s): cpu = 00:29:38 ; elapsed = 00:29:43 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17972 ; free virtual = 38407 Phase 17 Rip-up And Reroute Phase 17.1 Global Iteration 0 Number of Nodes with overlaps = 1373 Number of Nodes with overlaps = 346 Number of Nodes with overlaps = 190 Number of Nodes with overlaps = 98 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.003 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 17.1 Global Iteration 0 | Checksum: 258f30d33 Time (s): cpu = 00:31:48 ; elapsed = 00:31:52 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17966 ; free virtual = 38401 Phase 17 Rip-up And Reroute | Checksum: 258f30d33 Time (s): cpu = 00:31:48 ; elapsed = 00:31:53 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17966 ; free virtual = 38401 Phase 18 Delay and Skew Optimization Phase 18.1 Delay CleanUp Phase 18.1.1 Update Timing Phase 18.1.1 Update Timing | Checksum: 20fdc2e7b Time (s): cpu = 00:32:16 ; elapsed = 00:32:20 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17970 ; free virtual = 38406 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.016 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18.1 Delay CleanUp | Checksum: 25dfa85c0 Time (s): cpu = 00:32:17 ; elapsed = 00:32:21 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17970 ; free virtual = 38406 Phase 18.2 Clock Skew Optimization Phase 18.2 Clock Skew Optimization | Checksum: 25dfa85c0 Time (s): cpu = 00:32:17 ; elapsed = 00:32:22 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17972 ; free virtual = 38408 Phase 18 Delay and Skew Optimization | Checksum: 25dfa85c0 Time (s): cpu = 00:32:18 ; elapsed = 00:32:23 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17971 ; free virtual = 38407 Phase 19 Post Hold Fix Phase 19.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.016 | TNS=0.000 | WHS=0.008 | THS=0.000 | Phase 19.1 Hold Fix Iter | Checksum: 2a7002035 Time (s): cpu = 00:32:48 ; elapsed = 00:32:53 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17966 ; free virtual = 38402 Phase 19 Post Hold Fix | Checksum: 2a7002035 Time (s): cpu = 00:32:49 ; elapsed = 00:32:54 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17965 ; free virtual = 38402 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 260cf058b Time (s): cpu = 00:33:29 ; elapsed = 00:33:34 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17964 ; free virtual = 38400 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.016 | TNS=0.000 | WHS=0.008 | THS=0.000 | Phase 20 Timing Verification | Checksum: 260cf058b Time (s): cpu = 00:33:30 ; elapsed = 00:33:35 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17966 ; free virtual = 38402 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 27.249 % Global Horizontal Routing Utilization = 27.2439 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 21 Route finalize | Checksum: 260cf058b Time (s): cpu = 00:33:32 ; elapsed = 00:33:37 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17964 ; free virtual = 38400 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 260cf058b Time (s): cpu = 00:33:34 ; elapsed = 00:33:38 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17966 ; free virtual = 38403 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 18ea0b920 Time (s): cpu = 00:34:00 ; elapsed = 00:34:04 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17964 ; free virtual = 38400 Phase 24 Post Process Routing Phase 24 Post Process Routing | Checksum: 18ea0b920 Time (s): cpu = 00:34:01 ; elapsed = 00:34:06 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17963 ; free virtual = 38400 Phase 25 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.017 | TNS=0.000 | WHS=0.009 | THS=0.000 | Phase 25 Post Router Timing | Checksum: 1347ac940 Time (s): cpu = 00:35:32 ; elapsed = 00:35:36 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17963 ; free virtual = 38400 INFO: [Route 35-61] The design met the timing requirement. Total Elapsed time in route_design: 2136.73 secs Phase 26 Post-Route Event Processing Phase 26 Post-Route Event Processing | Checksum: 1a7d9e89d Time (s): cpu = 00:35:35 ; elapsed = 00:35:40 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17963 ; free virtual = 38400 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 1a7d9e89d Time (s): cpu = 00:35:41 ; elapsed = 00:35:45 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17961 ; free virtual = 38398 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 233 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:35:44 ; elapsed = 00:35:49 . Memory (MB): peak = 10317.395 ; gain = 873.516 ; free physical = 17968 ; free virtual = 38406 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx Command: report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.3/efex_hi_processor.3.runs/impl_1/top_efex_processor_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 10317.395 ; gain = 0.000 ; free physical = 17949 ; free virtual = 38391 INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx Command: report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.3/efex_hi_processor.3.runs/impl_1/top_efex_processor_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:42 ; elapsed = 00:02:44 . Memory (MB): peak = 10317.395 ; gain = 0.000 ; free physical = 17943 ; free virtual = 38387 INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_processor_timing_summary_routed.rpt -pb top_efex_processor_timing_summary_routed.pb -rpx top_efex_processor_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 10317.395 ; gain = 0.000 ; free physical = 17841 ; free virtual = 38372 INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_processor_timing_summary_routed_1.rpt -pb top_efex_processor_timing_summary_routed_1.pb -rpx top_efex_processor_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 10317.395 ; gain = 0.000 ; free physical = 17839 ; free virtual = 38372 INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_processor_route_status.rpt -pb top_efex_processor_route_status.pb INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_processor_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_processor_bus_skew_routed.rpt -pb top_efex_processor_bus_skew_routed.pb -rpx top_efex_processor_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx Command: report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 252 Infos, 9 Warnings, 3 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:15 ; elapsed = 00:00:56 . Memory (MB): peak = 10445.395 ; gain = 128.000 ; free physical = 17737 ; free virtual = 38291 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_processor_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 10445.395 ; gain = 0.000 ; free physical = 17742 ; free virtual = 38296 generate_parallel_reports: Time (s): cpu = 00:07:23 ; elapsed = 00:07:09 . Memory (MB): peak = 10445.395 ; gain = 128.000 ; free physical = 17742 ; free virtual = 38296 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_hi_processor.3... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_hi_processor.3 clean. WARNING: [Hog:GetLinkedFile-0] ./list/efex_processor.ipb is a broken link, because the linked file: /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.3/efex_processor.1/list/efex_processor.ipb does not exist. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_hi_processor.3 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_hi_processor.3 clean. WARNING: [Hog:GetLinkedFile-0] ./list/efex_processor.ipb is a broken link, because the linked file: /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.3/efex_processor.1/list/efex_processor.ipb does not exist. INFO: [Hog:Msg-0] The git SHA value ea29254 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_hi_processor.3... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_hi_processor.3 clean. WARNING: [Hog:GetLinkedFile-0] ./list/efex_processor.ipb is a broken link, because the linked file: /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.3/efex_processor.1/list/efex_processor.ipb does not exist. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_hi_processor.3-v1.7.3-EA29254... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 10445.395 ; gain = 0.000 ; free physical = 17696 ; free virtual = 38258