*** Running vivado with args -log top_efex_processor.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_efex_processor.tcl -notrace ****** Vivado v2024.2 (64-bit) **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024 **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 **** Start of session at: Tue Nov 11 00:06:45 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. source top_efex_processor.tcl -notrace Command: link_design -top top_efex_processor -part xc7vx550tffg1927-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7vx550tffg1927-2 INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/AlgoParameterRAM/AlgoParameterRAM.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/HADRON_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Algorithm/Mult/Mult.dcp' for cell 'DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.dcp' for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[0].quad/MGT_GT0/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/mgt_playback_ram/mgt_playback_ram.dcp' for cell 'MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_GT3/playback_ram/PLAYBACK_RAM' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_252b_512/DPR_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U3_XTOB_DRP' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.dcp' for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/DPR_36b_1024/DPR_36b_1024.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U3_DPRAM_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.dcp' for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.dcp' for cell 'clock_resources/Inputclk40M' INFO: [Project 1-454] Reading design checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.dcp' for cell 'clock_resources/clk40_gen' Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2934.762 ; gain = 10.000 ; free physical = 22373 ; free virtual = 43660 INFO: [Netlist 29-17] Analyzing 29676 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.2 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. clock_resources/clk40_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clock_resources/clk40_gen/clk40' is not directly connected to top level port. 'IBUF_LOW_PWR' is ignored for synthesis but preserved for implementation. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[0].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[10].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[11].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[12].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[13].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[14].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[15].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[16].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[17].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[18].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[19].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[1].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[20].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[21].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[22].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[23].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[24].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[25].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[26].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[27].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[28].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[29].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[2].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[30].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[31].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[32].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[33].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[34].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[35].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[36].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[37].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[38].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[39].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[3].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[40].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[41].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[42].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[43].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[44].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[45].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[46].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[47].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[48].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[4].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[5].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[6].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[7].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[8].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_36b_512/FIFO_36b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/GEN_CHANNEL[9].U4_FIFO_RAW_Data/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'FIFO_209b_512'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_209b_512/FIFO_209b_512.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1_board.xdc] for cell 'clock_resources/clk40_gen/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc:54] get_clocks: Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 4755.977 ; gain = 1122.625 ; free physical = 20738 ; free virtual = 42026 Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/clk_wiz_1/clk_wiz_1.xdc] for cell 'clock_resources/clk40_gen/inst' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay/io_delay.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard_board.xdc] for cell 'clock_resources/Inputclk40M/inst' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc:54] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/ClockWizard/ClockWizard.xdc] for cell 'clock_resources/Inputclk40M/inst' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'io_delay2'. The XDC file /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/io_delay2/io_delay2.xdc will not be read for any cell of this module. Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[0].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[10].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[11].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[12].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[13].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[14].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[16].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[17].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[18].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[19].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[1].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[5].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[6].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[7].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[8].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xdc] for cell 'MGT_IF.MGT_TX_RX/MGT_GEN[9].mgt_1quad_Rx_Tx/QUAD_ENABLED.mgt/min_latency_1_quad_rx_tx_support_i/min_latency_1_quad_rx_tx_init_i/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] INFO: [Timing 38-2] Deriving generated clocks [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc:3] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/clocks.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_golden_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_usr_common.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_xdc.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/improve_timing.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/bitstream.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Algorithm/xdc/algo.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Readout/xdc/readout.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga4.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/golden_fpga4.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga4.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/mgt_fpga4.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga4.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/proc_fpga4.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga4.xdc] Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/Infrastructure/xdc/merger_fpga4.xdc] Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U0_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_47b_512/FIFO_47b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U6_FIFO_BCN_L1A/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_33b_8192/FIFO_33b_8192_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_54b_512/FIFO_54b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U1_RAW_readout/U5_FIFO_link_err/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[0].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[2].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[3].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[4].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[5].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[6].U5_XTOBs_FIFO/U0' Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' Finished Parsing XDC File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Readout/FIFO_252b_512/FIFO_252b_512_clocks.xdc] for cell 'READOUT_IF.Readout_block/U0_TOBs_readout/U3_XTOBs_tau_sorting/GEN_XTOB_RAM[7].U5_XTOBs_FIFO/U0' WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U1_RAW_readout/U8_RAW_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: READOUT_IF.Readout_block/U0_TOBs_readout/U7_Link_output_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: AMD recommends that you remove these modules. 2) AMD IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] INFO: [Project 1-1714] 112 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 5480.031 ; gain = 0.000 ; free physical = 20040 ; free virtual = 41330 INFO: [Project 1-111] Unisim Transformation Summary: A total of 66 instances were transformed. OBUFDS => OBUFDS: 66 instances 33 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:54 ; elapsed = 00:02:07 . Memory (MB): peak = 5480.031 ; gain = 3980.840 ; free physical = 20040 ; free virtual = 41330 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/pre-implementation.tcl INFO: [Hog:Msg-0] Disabling multithreading to assure deterministic bitfile INFO: [Hog:ResetRepoFiles-0] Found ./Projects/hog_reset_files, opening it... INFO: [Hog:ResetRepoFiles-0] Found the following files/wild cards to restore if modified: *.bd... INFO: [Hog:ResetRepoFiles-0] No modified *.bd files found. INFO: [Hog:Msg-0] All done Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. Parsing TCL File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] from IP /builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/min_latency_1_quad_rx_tx.xci Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7vx550t. * **************************************************************************************** Finished Sourcing Tcl File [/builds/atlas-l1calo-efex/eFEXFirmware/IP/Infrastructure_process/Min_Latency_F1_MGT_212_11g2_TX_RX/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 5488.035 ; gain = 0.000 ; free physical = 20043 ; free virtual = 41332 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 23743fe8c Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 5649.035 ; gain = 161.000 ; free physical = 19847 ; free virtual = 41137 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 23743fe8c Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.51 . Memory (MB): peak = 6004.801 ; gain = 0.000 ; free physical = 19499 ; free virtual = 40789 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 23743fe8c Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.66 . Memory (MB): peak = 6004.801 ; gain = 0.000 ; free physical = 19499 ; free virtual = 40789 Phase 1 Initialization | Checksum: 23743fe8c Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.7 . Memory (MB): peak = 6004.801 ; gain = 0.000 ; free physical = 19499 ; free virtual = 40789 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 23743fe8c Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6004.801 ; gain = 0.000 ; free physical = 19484 ; free virtual = 40774 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 23743fe8c Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 6196.801 ; gain = 192.000 ; free physical = 19351 ; free virtual = 40640 Phase 2 Timer Update And Timing Data Collection | Checksum: 23743fe8c Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 6196.801 ; gain = 192.000 ; free physical = 19350 ; free virtual = 40640 Phase 3 Retarget INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 INFO: [Opt 31-1566] Pulled 4 inverters resulting in an inversion of 31 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1bca2b1ec Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 6196.801 ; gain = 192.000 ; free physical = 19349 ; free virtual = 40639 Retarget | Checksum: 1bca2b1ec INFO: [Opt 31-389] Phase Retarget created 159 cells and removed 538 cells INFO: [Opt 31-1021] In phase Retarget, 225 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 257f4cd86 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 6196.801 ; gain = 192.000 ; free physical = 19349 ; free virtual = 40638 Constant propagation | Checksum: 257f4cd86 INFO: [Opt 31-389] Phase Constant propagation created 38 cells and removed 177 cells INFO: [Opt 31-1021] In phase Constant propagation, 157 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 5 Sweep INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6196.801 ; gain = 0.000 ; free physical = 19348 ; free virtual = 40638 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6196.801 ; gain = 0.000 ; free physical = 19347 ; free virtual = 40637 Phase 5 Sweep | Checksum: 1be3ce2c7 Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 6196.801 ; gain = 192.000 ; free physical = 19346 ; free virtual = 40636 Sweep | Checksum: 1be3ce2c7 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3441 cells INFO: [Opt 31-1021] In phase Sweep, 900 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 6 BUFG optimization INFO: [Opt 31-274] Optimized connectivity to 1 cascaded buffer cells Phase 6 BUFG optimization | Checksum: 1db43fa04 Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19348 ; free virtual = 40638 BUFG optimization | Checksum: 1db43fa04 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 1 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1db43fa04 Time (s): cpu = 00:00:35 ; elapsed = 00:00:32 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19349 ; free virtual = 40639 Shift Register Optimization | Checksum: 1db43fa04 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1e7353fda Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19348 ; free virtual = 40638 Post Processing Netlist | Checksum: 1e7353fda INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 300 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2d93a0849 Time (s): cpu = 00:00:45 ; elapsed = 00:00:42 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19354 ; free virtual = 40644 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.6 . Memory (MB): peak = 6228.816 ; gain = 0.000 ; free physical = 19355 ; free virtual = 40645 Phase 9.2 Verifying Netlist Connectivity | Checksum: 2d93a0849 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19355 ; free virtual = 40645 Phase 9 Finalization | Checksum: 2d93a0849 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19355 ; free virtual = 40645 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 159 | 538 | 225 | | Constant propagation | 38 | 177 | 157 | | Sweep | 0 | 3441 | 900 | | BUFG optimization | 1 | 1 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 300 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 2d93a0849 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 6228.816 ; gain = 224.016 ; free physical = 19355 ; free virtual = 40645 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Power 33-23] Power model is not available for STARTUPE2_inst INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 16 BRAM(s) out of a total of 788 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 114 WE to EN ports Number of BRAM Ports augmented: 97 newly gated: 186 Total Ports: 1576 Ending PowerOpt Patch Enables Task | Checksum: 1d4444ce1 Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16259 ; free virtual = 37550 Ending Power Optimization Task | Checksum: 1d4444ce1 Time (s): cpu = 00:02:28 ; elapsed = 00:01:56 . Memory (MB): peak = 9370.219 ; gain = 3141.402 ; free physical = 16262 ; free virtual = 37552 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 24b686608 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16244 ; free virtual = 37535 Ending Final Cleanup Task | Checksum: 24b686608 Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16244 ; free virtual = 37535 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16244 ; free virtual = 37535 Ending Netlist Obfuscation Task | Checksum: 24b686608 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16244 ; free virtual = 37535 INFO: [Common 17-83] Releasing license: Implementation 72 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:04:22 ; elapsed = 00:03:49 . Memory (MB): peak = 9370.219 ; gain = 3890.188 ; free physical = 16244 ; free virtual = 37535 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx Command: report_drc -file top_efex_processor_drc_opted.rpt -pb top_efex_processor_drc_opted.pb -rpx top_efex_processor_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.4/efex_hi_processor.4.runs/impl_1/top_efex_processor_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16234 ; free virtual = 37525 generate_parallel_reports: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16234 ; free virtual = 37525 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.47 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15836 ; free virtual = 37493 Wrote PlaceDB: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15836 ; free virtual = 37495 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15836 ; free virtual = 37495 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.6 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15836 ; free virtual = 37496 Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15836 ; free virtual = 37496 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15829 ; free virtual = 37489 Write Physdb Complete: Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.72 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15829 ; free virtual = 37489 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.4/efex_hi_processor.4.runs/impl_1/top_efex_processor_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:53 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16083 ; free virtual = 37455 Command: place_design -directive ExtraPostPlacementOpt Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Common 17-83] Releasing license: Implementation INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'ExtraPostPlacementOpt' directive. Running DRC as a precondition to command place_design INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16106 ; free virtual = 37478 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 21b6dc10c Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16106 ; free virtual = 37478 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16106 ; free virtual = 37478 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 18d231bcc Time (s): cpu = 00:01:17 ; elapsed = 00:01:17 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16131 ; free virtual = 37504 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 201aeff4a Time (s): cpu = 00:02:30 ; elapsed = 00:02:31 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16105 ; free virtual = 37478 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 201aeff4a Time (s): cpu = 00:02:31 ; elapsed = 00:02:32 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16102 ; free virtual = 37476 Phase 1 Placer Initialization | Checksum: 201aeff4a Time (s): cpu = 00:02:32 ; elapsed = 00:02:32 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16102 ; free virtual = 37475 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1dea45ead Time (s): cpu = 00:02:59 ; elapsed = 00:02:59 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16095 ; free virtual = 37468 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19493654b Time (s): cpu = 00:03:20 ; elapsed = 00:03:21 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16100 ; free virtual = 37474 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f5be2cd4 Time (s): cpu = 00:03:21 ; elapsed = 00:03:22 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16100 ; free virtual = 37474 Phase 2.4 Global Place Phase1 Phase 2.4 Global Place Phase1 | Checksum: 18c8bba2a Time (s): cpu = 00:07:04 ; elapsed = 00:07:06 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16095 ; free virtual = 37471 Phase 2.5 Global Place Phase2 Phase 2.5.1 UpdateTiming Before Physical Synthesis Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 1d6adf230 Time (s): cpu = 00:07:30 ; elapsed = 00:07:32 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16093 ; free virtual = 37470 Phase 2.5.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 121 LUTNM shape to break, 13070 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 56, two critical 65, total 121, new lutff created 10 INFO: [Physopt 32-1138] End 1 Pass. Optimized 4845 nets or LUTs. Breaked 121 LUTs, combined 4724 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-1408] Pass 1. Identified 21 candidate nets for high-fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg_n_1_[10]. Replicated 11 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/INPUT_STAGE/IN_Load. Replicated 73 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/LOAD_GENERATOR/OUT_Load200_reg_0. Replicated 66 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[5].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/OUT_TOB_Start. Replicated 33 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/RATE_MONITOR/eta_for[4].phi_for[0].CNT_TAU/SR[0]. Replicated 18 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[1]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].AGLO_CORE_EG/SEED_FINDER/data_in[2]. Replicated 8 times. INFO: [Physopt 32-232] Optimized 21 nets. Created 318 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 21 nets or cells. Created 318 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16097 ; free virtual = 37474 INFO: [Physopt 32-76] Pass 1. Identified 144 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[5]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[7]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[9]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[0]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[4]. Replicated 7 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[2]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[6]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[10]. Replicated 7 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[1]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[11]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[5]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[12]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[14]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[10]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[8]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[4]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[9]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[3]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[13]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[6]. Replicated 5 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[0]. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/enb. Replicated 9 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[6]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[11]. Replicated 8 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[6]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[11]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[12]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[3]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[1]. Replicated 3 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[12]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1088[7]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1068[0]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[15]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[12]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[0]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[7]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[2]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[8]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1034[8]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1069[12]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1089[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[12]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1100[2]. Replicated 3 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1102[2]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[9]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[14]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[3]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1034[0]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[10]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1099[8]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[6]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1034[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1099[6]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[9]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[0]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[4]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[11]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1089[2]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[9]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1068[13]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[11]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1099[4]. Replicated 5 times. INFO: [Physopt 32-81] Processed net READOUT_IF.Readout_block/U1_RAW_readout/addrb[4]. Replicated 9 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1099[10]. Replicated 4 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1078[5]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1067[12]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[1]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[8]. Replicated 7 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1069[15]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[4]. Replicated 3 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1090[8]. Replicated 6 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1034[1]. Replicated 8 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1025[10]. Replicated 5 times. INFO: [Physopt 32-81] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/DATA_SHIFT_REGISTER/O1077[7]. Replicated 7 times. INFO: [Common 17-14] Message 'Physopt 32-81' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Physopt 32-232] Optimized 142 nets. Created 913 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 142 nets or cells. Created 913 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.82 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16093 ; free virtual = 37470 INFO: [Physopt 32-46] Identified 26 candidate nets for critical-cell optimization. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[9]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[0]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[6]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[2]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[7]_rep_n_1 was not replicated. INFO: [Physopt 32-571] Net READOUT_IF.Readout_block/U1_RAW_readout/DPR_wr_addr_i_1dly_reg[4]_rep_n_1 was not replicated. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-457] Pass 1. Identified 27 candidate cells for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/WS_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[0].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[3].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[4].TAU_ALGO.AGLO_CORE_TAU/Jet_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[1].AGLO_CORE_EG/RETA_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[6].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[2].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[2].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[0].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 27 nets or cells. Created 648 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16092 ; free virtual = 37469 INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1402] Pass 1: Identified 109 candidate cells for Shift Register optimization. INFO: [Physopt 32-775] End 1 Pass. Optimized 64 nets or cells. Created 110 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37474 INFO: [Physopt 32-527] Pass 1: Identified 2 candidate cells for BRAM register optimization INFO: [Physopt 32-666] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. No change. INFO: [Physopt 32-666] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/IPBUS_ALGO_PARAMETER_RAM/ALGO_PARAMETER_RAM/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram. No change. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.21 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37474 INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16095 ; free virtual = 37473 INFO: [Physopt 32-68] No nets found for critical-cell optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37473 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 121 | 4724 | 4845 | 0 | 1 | 00:00:07 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 318 | 0 | 21 | 0 | 1 | 00:00:10 | | Fanout | 913 | 0 | 142 | 0 | 1 | 00:00:13 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 648 | 0 | 27 | 0 | 1 | 00:00:01 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 110 | 0 | 64 | 0 | 1 | 00:00:01 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:01 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 2110 | 4724 | 5099 | 0 | 12 | 00:00:33 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.5.2 Physical Synthesis In Placer | Checksum: 299a799a7 Time (s): cpu = 00:08:33 ; elapsed = 00:08:36 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16082 ; free virtual = 37459 Phase 2.5 Global Place Phase2 | Checksum: 1ffb7a665 Time (s): cpu = 00:08:46 ; elapsed = 00:08:48 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16091 ; free virtual = 37468 Phase 2 Global Placement | Checksum: 1ffb7a665 Time (s): cpu = 00:08:46 ; elapsed = 00:08:49 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16091 ; free virtual = 37468 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1fc7e104a Time (s): cpu = 00:09:13 ; elapsed = 00:09:16 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16098 ; free virtual = 37476 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2595a00dd Time (s): cpu = 00:10:16 ; elapsed = 00:10:19 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16108 ; free virtual = 37486 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1fffb28b0 Time (s): cpu = 00:10:20 ; elapsed = 00:10:23 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16108 ; free virtual = 37486 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 2510e00e7 Time (s): cpu = 00:10:21 ; elapsed = 00:10:24 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16107 ; free virtual = 37486 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 20c5f9d0a Time (s): cpu = 00:11:29 ; elapsed = 00:11:32 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37475 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 24fa20740 Time (s): cpu = 00:13:21 ; elapsed = 00:13:24 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16098 ; free virtual = 37478 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 2426806df Time (s): cpu = 00:13:35 ; elapsed = 00:13:38 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16093 ; free virtual = 37473 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1f1d31641 Time (s): cpu = 00:13:40 ; elapsed = 00:13:44 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16101 ; free virtual = 37480 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 27d389bd2 Time (s): cpu = 00:15:20 ; elapsed = 00:15:24 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16084 ; free virtual = 37465 Phase 3 Detail Placement | Checksum: 27d389bd2 Time (s): cpu = 00:15:23 ; elapsed = 00:15:27 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16082 ; free virtual = 37462 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 245fdd466 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.560 | TNS=-38.232 | Phase 1 Physical Synthesis Initialization | Checksum: 238ea177a Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16092 ; free virtual = 37474 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 28d5e264e Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16093 ; free virtual = 37476 Phase 4.1.1.1 BUFG Insertion | Checksum: 245fdd466 Time (s): cpu = 00:17:25 ; elapsed = 00:17:30 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16092 ; free virtual = 37475 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.073. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 21febdb19 Time (s): cpu = 00:19:09 ; elapsed = 00:19:15 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16102 ; free virtual = 37485 Time (s): cpu = 00:19:09 ; elapsed = 00:19:15 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16102 ; free virtual = 37485 Phase 4.1 Post Commit Optimization | Checksum: 21febdb19 Time (s): cpu = 00:19:12 ; elapsed = 00:19:17 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16105 ; free virtual = 37488 Post Placement Optimization Initialization | Checksum: 25eae87da Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.871 | TNS=-48.295 | Phase 1 Physical Synthesis Initialization | Checksum: 253849c74 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16080 ; free virtual = 37467 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 28b7454c8 Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16078 ; free virtual = 37465 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.274. For the most accurate timing information please run report_timing. Post Placement Optimization Initialization | Checksum: 238438744 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.274 | TNS=-20.285 | Phase 1 Physical Synthesis Initialization | Checksum: 23fb82135 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16099 ; free virtual = 37488 INFO: [Place 46-33] Processed net clock_resources/clocks/rsto_ipb_ctrl, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ShiftTowers[6][9][Layer0][0][15]_i_1_n_1, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 2 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 2a0e7815e Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16099 ; free virtual = 37488 INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.274. For the most accurate timing information please run report_timing. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 25d5fbd58 Time (s): cpu = 00:32:11 ; elapsed = 00:32:21 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37486 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 32x32| 8x8| |___________|___________________|___________________| | South| 32x32| 8x8| |___________|___________________|___________________| | East| 16x16| 4x4| |___________|___________________|___________________| | West| 16x16| 4x4| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 25d5fbd58 Time (s): cpu = 00:32:14 ; elapsed = 00:32:24 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37486 Phase 4.3 Placer Reporting | Checksum: 25d5fbd58 Time (s): cpu = 00:32:17 ; elapsed = 00:32:26 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16095 ; free virtual = 37485 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16095 ; free virtual = 37485 Time (s): cpu = 00:32:17 ; elapsed = 00:32:26 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16095 ; free virtual = 37485 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 238a069eb Time (s): cpu = 00:32:20 ; elapsed = 00:32:29 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16093 ; free virtual = 37483 Ending Placer Task | Checksum: 1f4349f40 Time (s): cpu = 00:32:22 ; elapsed = 00:32:31 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37486 271 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:32:43 ; elapsed = 00:32:53 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16096 ; free virtual = 37486 INFO: [Vivado 12-24828] Executing command : report_io -file top_efex_processor_io_placed.rpt report_io: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.65 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16067 ; free virtual = 37457 INFO: [Vivado 12-24828] Executing command : report_utilization -file top_efex_processor_utilization_placed.rpt -pb top_efex_processor_utilization_placed.pb INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_efex_processor_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:01 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16058 ; free virtual = 37450 generate_parallel_reports: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 16057 ; free virtual = 37450 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.79 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15688 ; free virtual = 37467 Wrote PlaceDB: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15402 ; free virtual = 37478 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15402 ; free virtual = 37478 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.56 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15402 ; free virtual = 37479 Wrote Netlist Cache: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.35 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15370 ; free virtual = 37478 Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15370 ; free virtual = 37480 Write Physdb Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15370 ; free virtual = 37480 report_design_analysis: Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15346 ; free virtual = 37457 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.4/efex_hi_processor.4.runs/impl_1/top_efex_processor_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:20 ; elapsed = 00:01:24 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15901 ; free virtual = 37410 Command: phys_opt_design -directive AlternateFlowWithRetiming Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: AlternateFlowWithRetiming Starting Initial Update Timing Task Time (s): cpu = 00:01:13 ; elapsed = 00:01:13 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15951 ; free virtual = 37460 INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 74.81s | WALL: 74.93s Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15951 ; free virtual = 37460 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.274 | TNS=-17.422 | Phase 1 Physical Synthesis Initialization | Checksum: 1b1483fc3 Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15957 ; free virtual = 37466 INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.274 | TNS=-17.422 | Phase 2 DSP Register Optimization INFO: [Physopt 32-457] Pass 1. Identified 1 candidate cell for DSP register optimization. INFO: [Physopt 32-665] Processed cell DATA_PATH_IF.data_path_Module/algorithm_block/TOP_ALGO_MODULE/ALGO_GENERATION[7].TAU_ALGO.AGLO_CORE_TAU/Frac_MULTIPLIER/MULT_FOR[1].SPEED.MULTIPLIER/U0/i_mult/gDSP.gDSP_only.iDSP/inferred_dsp.use_p_reg.p_reg_reg. 24 registers were pushed out. INFO: [Physopt 32-775] End 2 Pass. Optimized 1 net or cell. Created 24 new cells, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.274 | TNS=-17.422 | Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15958 ; free virtual = 37467 Phase 2 DSP Register Optimization | Checksum: 1adf4805a Time (s): cpu = 00:00:55 ; elapsed = 00:00:55 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15958 ; free virtual = 37467 Phase 3 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.274 | TNS=-17.422 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[219]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3][219] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[219]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.241 | TNS=-17.147 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[201]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3][201] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[201]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.241 | TNS=-16.906 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[216]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3][216] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[216]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.241 | TNS=-16.664 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[223]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3][223] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[223]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.241 | TNS=-16.423 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[225]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3][225] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[225]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.241 | TNS=-16.182 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[3]__0[229]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[3][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[3][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[3][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.238 | TNS=-13.330 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[7]__0[232]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[7][232] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[7]__0[232]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.216 | TNS=-13.092 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[215]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4][215] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[215]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.216 | TNS=-13.038 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[216]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4][216] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[216]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.196 | TNS=-12.984 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[194]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2][194] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[194]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.196 | TNS=-12.788 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[199]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2][199] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[199]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.196 | TNS=-12.591 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[203]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2][203] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[203]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.196 | TNS=-12.395 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[210]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2][210] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[210]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.191 | TNS=-12.199 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[212]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4][212] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[212]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.172 | TNS=-12.170 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[230]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4][230] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[230]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.165 | TNS=-11.997 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/RAW_data_FIFO_flags_i[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U1_RAW_readout/FIFO_RAW_Data_empty_tmp_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U1_RAW_readout/FIFO_RAW_Data_empty_tmp_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/FIFO_RAW_Data_empty_tmp_i_5_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.162 | TNS=-11.832 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[212]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[4][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[4][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[4][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.155 | TNS=-10.752 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[2]__0[209]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[2][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[2][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i[2][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.140 | TNS=-9.979 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[0]_325[196]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[0][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[0][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[0][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.135 | TNS=-7.258 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/in15[31]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/mgt_disable_i_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/mgt_disable_i_i_1_comp. INFO: [Physopt 32-735] Processed net MGT_IF.MGT_ipb/QUAD_FOR[9].quad/MGT_QUAD_Control/reg_reg[0][6]_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.131 | TNS=-7.122 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[2]_323[214]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[2][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[2][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[2][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.129 | TNS=-5.031 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[227]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4][227] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[227]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.129 | TNS=-4.902 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[229]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4][229] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[229]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.129 | TNS=-4.773 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[237]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4][237] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[237]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.129 | TNS=-4.643 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[239]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4][239] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[239]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.122 | TNS=-4.611 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_xtob_data_tidemark/Q[1]. Re-placed instance READOUT_IF.Readout_block/U0_xtob_data_tidemark/tide_mark_block.tide_mark_reg[1] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_xtob_data_tidemark/Q[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.122 | TNS=-4.489 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_xtob_data_tidemark/Q[7]. Re-placed instance READOUT_IF.Readout_block/U0_xtob_data_tidemark/tide_mark_block.tide_mark_reg[7] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_xtob_data_tidemark/Q[7]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.122 | TNS=-4.366 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_xtob_data_tidemark/Q[8]. Re-placed instance READOUT_IF.Readout_block/U0_xtob_data_tidemark/tide_mark_block.tide_mark_reg[8] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_xtob_data_tidemark/Q[8]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.118 | TNS=-4.244 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OUT_Write_reg_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/OUT_Write0. Critical path length was reduced through logic transformation on cell DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/OUT_Write_i_1__8_comp. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_8__10_0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.109 | TNS=-4.221 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[209]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5][209] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[209]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.109 | TNS=-4.185 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[215]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5][215] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[215]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.109 | TNS=-4.149 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[223]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5][223] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[223]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.109 | TNS=-4.113 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[227]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5][227] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[227]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.102 | TNS=-4.077 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[0]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.102 | TNS=-3.975 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[1]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.102 | TNS=-3.872 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[2]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.102 | TNS=-3.770 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[3]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]_0[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.100 | TNS=-3.668 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_1_[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1__5. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 34 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_1[0]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.099 | TNS=-3.642 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_1_[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress0. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress[2]_i_2__0 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.097 | TNS=-3.615 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[239]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[4][191]_i_1_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_valid_i[0][4]_i_1_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[4][239]_i_1_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/FSM_onehot_current_state_reg[3]_rep__4_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.097 | TNS=-3.615 | Netlist sorting complete. Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.33 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15952 ; free virtual = 37462 Phase 3 Critical Path Optimization | Checksum: 2026e5135 Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15952 ; free virtual = 37462 Phase 4 Critical Path Optimization INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.097 | TNS=-3.615 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[4]_321[239]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[4][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[4][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[4][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.094 | TNS=-3.007 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_1_[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_8__10_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_8__10_0. Critical path length was reduced through logic transformation on cell DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_2__12_comp_1. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_4__10_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.088 | TNS=-2.947 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_2/ReadAddress_reg_n_1_[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_2/ReadAddress0. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_2__7 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_2/ReadAddress0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.088 | TNS=-2.892 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i_reg[5]_320[212]. Optimizations did not improve timing on the net. INFO: [Physopt 32-710] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][239]_i_1_n_1. Critical path length was reduced through logic transformation on cell READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][239]_i_1_comp. INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_eg_i[5][191]_i_1_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.087 | TNS=-1.983 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_1_[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1__5. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1_carry_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_1[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_8. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/OUT_Data[0]_i_2__10 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_8. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.084 | TNS=-1.959 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_1_[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress0. Rewiring did not optimize the net. INFO: [Physopt 32-601] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress0. Net driver DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress[2]_i_2__0 was replaced. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/stage_gen[0].ifAll.sorter_gen[0].PAR_SORTER/FastFifo_1/ReadAddress0. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.083 | TNS=-1.874 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/RAW_rdout_fifo_rd_en_i[48]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/RAW_rdout_fifo_rd_en_i[48]_i_5_n_1. Re-placed instance READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/RAW_rdout_fifo_rd_en_i[48]_i_5 INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U7_rd_RAW_mux_fsm/RAW_rdout_fifo_rd_en_i[48]_i_5_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.079 | TNS=-1.791 | INFO: [Physopt 32-608] Optimized 1 net. Swapped 16 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_2/ReadAddress[2]_i_5__10_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.075 | TNS=-1.539 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/S[0]. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 23 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/OUT_Data[8]_i_2__10_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.074 | TNS=-1.537 | INFO: [Physopt 32-134] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_7. Rewiring did not optimize the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 21 pins. INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg[2]_7. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.073 | TNS=-1.523 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_link_err/din[53]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_link_err/req_err_rd_raw_i_7_n_1. Re-placed instance READOUT_IF.Readout_block/U1_RAW_readout/U5_link_err/req_err_rd_raw_i_7 INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U1_RAW_readout/U5_link_err/req_err_rd_raw_i_7_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.071 | TNS=-1.472 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[1]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[1]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.071 | TNS=-1.401 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[2]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.071 | TNS=-1.330 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[3]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[3]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.071 | TNS=-1.258 | INFO: [Physopt 32-663] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[4]. Re-placed instance READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4] INFO: [Physopt 32-735] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U2_XTOBs_eg_sorting/GEN_XTOB_RAM[1].U5_XTOBs_FIFO/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[4]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.071 | TNS=-1.187 | INFO: [Physopt 32-702] Processed net sorted_eg_TOB_1[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net clock_resources/Inputclk40M/inst/clk280_ClockWizard. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/OUT_Data_reg[31]_0[2]. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/sorted_eg_TOB_inferred_i_30 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_eg/OUT_Data_reg[31]_0[2]. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.067 | TNS=-1.115 | INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/ReadAddress_reg_n_1_[2]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/OneOrTwo1__5. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/S[1]. Optimizations did not improve timing on the net. INFO: [Physopt 32-663] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/OUT_Data[11]_i_2__10_n_1. Re-placed instance DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/OUT_Data[11]_i_2__10 INFO: [Physopt 32-735] Processed net DATA_PATH_IF.data_path_Module/Sorting_Module/TopSorting_tau/stage_gen[2].ifFirst.sorter_gen0[1].PAR_SORTER/FastFifo_1/OUT_Data[11]_i_2__10_n_1. Optimization improves timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.067 | TNS=-1.101 | INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[15]. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[15]_i_5_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i_reg[15]_i_10_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[15]_i_16_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/TOBs_out_i[15]_i_1_n_1. Optimizations did not improve timing on the net. INFO: [Physopt 32-702] Processed net READOUT_IF.Readout_block/U0_TOBs_readout/U6_rd_mux_fsm/XTOB_tau_i_reg[4]__0[47]. Optimizations did not improve timing on the net. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.067 | TNS=-1.101 | Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15948 ; free virtual = 37458 Phase 4 Critical Path Optimization | Checksum: 115c1cd6e Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15948 ; free virtual = 37458 Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15948 ; free virtual = 37458 INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-0.067 | TNS=-1.101 | Summary of Physical Synthesis Optimizations ============================================ ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 24 | 0 | 1 | 0 | 1 | 00:00:05 | | Critical Path | 0.207 | 16.320 | 0 | 0 | 56 | 0 | 2 | 00:00:23 | | Total | 0.207 | 16.320 | 24 | 0 | 57 | 0 | 3 | 00:00:27 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15948 ; free virtual = 37457 Ending Physical Synthesis Task | Checksum: 1eb008747 Time (s): cpu = 00:01:22 ; elapsed = 00:01:22 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15951 ; free virtual = 37460 INFO: [Common 17-83] Releasing license: Implementation 507 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:02:36 ; elapsed = 00:02:37 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15951 ; free virtual = 37461 INFO: [Timing 38-480] Writing timing data to binary archive. Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.47 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15598 ; free virtual = 37468 Wrote PlaceDB: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15302 ; free virtual = 37469 Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15302 ; free virtual = 37469 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Wrote RouteStorage: Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.59 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15302 ; free virtual = 37469 Wrote Netlist Cache: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.34 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15270 ; free virtual = 37469 Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15270 ; free virtual = 37470 Write Physdb Complete: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15270 ; free virtual = 37470 report_design_analysis: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15251 ; free virtual = 37452 INFO: [Common 17-1381] The checkpoint '/builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.4/efex_hi_processor.4.runs/impl_1/top_efex_processor_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:02 ; elapsed = 00:01:06 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15777 ; free virtual = 37400 Command: route_design -directive Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7vx550t' INFO: [Common 17-1540] The version limit for your license is '2025.07' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for new releases. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'Explore'. Phase 1 Build RT Design Checksum: PlaceDB: 40ef855f ConstDB: 0 ShapeSum: fbdced90 RouteDB: 5324b193 Post Restoration Checksum: NetGraph: bd607682 | NumContArr: f2b0cfad | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 335633b69 Time (s): cpu = 00:02:13 ; elapsed = 00:02:13 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15834 ; free virtual = 37458 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 335633b69 Time (s): cpu = 00:02:15 ; elapsed = 00:02:16 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15834 ; free virtual = 37458 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 335633b69 Time (s): cpu = 00:02:17 ; elapsed = 00:02:18 . Memory (MB): peak = 9370.219 ; gain = 0.000 ; free physical = 15834 ; free virtual = 37458 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 3204c0b49 Time (s): cpu = 00:04:23 ; elapsed = 00:04:25 . Memory (MB): peak = 9378.219 ; gain = 8.000 ; free physical = 15826 ; free virtual = 37451 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.252 | TNS=-1.418 | WHS=-0.483 | THS=-11396.289| Phase 2.4 Update Timing for Bus Skew Phase 2.4.1 Update Timing Phase 2.4.1 Update Timing | Checksum: 246867675 Time (s): cpu = 00:05:51 ; elapsed = 00:05:52 . Memory (MB): peak = 9386.219 ; gain = 16.000 ; free physical = 15816 ; free virtual = 37442 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.252 | TNS=-1.306 | WHS=-0.456 | THS=-3132.778| Phase 2.4 Update Timing for Bus Skew | Checksum: 23f77d20f Time (s): cpu = 00:05:52 ; elapsed = 00:05:53 . Memory (MB): peak = 9386.219 ; gain = 16.000 ; free physical = 15816 ; free virtual = 37441 Router Utilization Summary Global Vertical Routing Utilization = 1.20441e-05 % Global Horizontal Routing Utilization = 8.84712e-05 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 428721 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 428719 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 2 Router Initialization | Checksum: 2f1b16ef5 Time (s): cpu = 00:05:58 ; elapsed = 00:05:59 . Memory (MB): peak = 9397.578 ; gain = 27.359 ; free physical = 15799 ; free virtual = 37425 Phase 3 Global Routing Phase 3 Global Routing | Checksum: 2f1b16ef5 Time (s): cpu = 00:05:59 ; elapsed = 00:06:00 . Memory (MB): peak = 9397.578 ; gain = 27.359 ; free physical = 15804 ; free virtual = 37429 Phase 4 Initial Routing Phase 4.1 Initial Net Routing Pass Phase 4.1 Initial Net Routing Pass | Checksum: 26761ced8 Time (s): cpu = 00:08:30 ; elapsed = 00:08:32 . Memory (MB): peak = 9397.578 ; gain = 27.359 ; free physical = 15829 ; free virtual = 37455 Phase 4 Initial Routing | Checksum: 26761ced8 Time (s): cpu = 00:08:32 ; elapsed = 00:08:33 . Memory (MB): peak = 9397.578 ; gain = 27.359 ; free physical = 15830 ; free virtual = 37456 Phase 5 Rip-up And Reroute Phase 5.1 Global Iteration 0 Number of Nodes with overlaps = 60530 Number of Nodes with overlaps = 6888 Number of Nodes with overlaps = 1705 Number of Nodes with overlaps = 518 Number of Nodes with overlaps = 139 Number of Nodes with overlaps = 63 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.250 | TNS=-6.078 | WHS=N/A | THS=N/A | Phase 5.1 Global Iteration 0 | Checksum: 23b457431 Time (s): cpu = 00:18:19 ; elapsed = 00:18:22 . Memory (MB): peak = 9678.430 ; gain = 308.211 ; free physical = 15530 ; free virtual = 37163 Phase 5.2 Global Iteration 1 Number of Nodes with overlaps = 1556 Number of Nodes with overlaps = 487 Number of Nodes with overlaps = 126 Number of Nodes with overlaps = 69 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.154 | TNS=-0.867 | WHS=N/A | THS=N/A | Phase 5.2 Global Iteration 1 | Checksum: 2bf763923 Time (s): cpu = 00:21:09 ; elapsed = 00:21:12 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15495 ; free virtual = 37130 Phase 5.3 Global Iteration 2 Number of Nodes with overlaps = 2285 Number of Nodes with overlaps = 453 Number of Nodes with overlaps = 251 Number of Nodes with overlaps = 122 Number of Nodes with overlaps = 78 Number of Nodes with overlaps = 29 Number of Nodes with overlaps = 18 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.101 | TNS=-0.552 | WHS=N/A | THS=N/A | Phase 5.3 Global Iteration 2 | Checksum: 1fc4b067e Time (s): cpu = 00:24:27 ; elapsed = 00:24:31 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15497 ; free virtual = 37134 Phase 5.4 Global Iteration 3 Number of Nodes with overlaps = 1732 Number of Nodes with overlaps = 582 Number of Nodes with overlaps = 245 Number of Nodes with overlaps = 122 Number of Nodes with overlaps = 109 Number of Nodes with overlaps = 53 Number of Nodes with overlaps = 26 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.220 | TNS=-0.891 | WHS=N/A | THS=N/A | Phase 5.4 Global Iteration 3 | Checksum: 2a6be7f8f Time (s): cpu = 00:27:59 ; elapsed = 00:28:03 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15511 ; free virtual = 37150 Phase 5 Rip-up And Reroute | Checksum: 2a6be7f8f Time (s): cpu = 00:28:00 ; elapsed = 00:28:04 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15511 ; free virtual = 37150 Phase 6 Delay and Skew Optimization Phase 6.1 Delay CleanUp Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 27ef70b55 Time (s): cpu = 00:28:28 ; elapsed = 00:28:32 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15494 ; free virtual = 37133 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.035 | TNS=-0.045 | WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 6.1 Delay CleanUp | Checksum: 34120ab7d Time (s): cpu = 00:28:33 ; elapsed = 00:28:37 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15495 ; free virtual = 37133 Phase 6.2 Clock Skew Optimization Phase 6.2 Clock Skew Optimization | Checksum: 34120ab7d Time (s): cpu = 00:28:34 ; elapsed = 00:28:38 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15494 ; free virtual = 37133 Phase 6 Delay and Skew Optimization | Checksum: 34120ab7d Time (s): cpu = 00:28:35 ; elapsed = 00:28:39 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15492 ; free virtual = 37131 Phase 7 Post Hold Fix Phase 7.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.041 | TNS=-0.051 | WHS=0.026 | THS=0.000 | Phase 7.1 Hold Fix Iter | Checksum: 34f6b15fb Time (s): cpu = 00:29:06 ; elapsed = 00:29:10 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15493 ; free virtual = 37132 Phase 7 Post Hold Fix | Checksum: 34f6b15fb Time (s): cpu = 00:29:07 ; elapsed = 00:29:11 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15496 ; free virtual = 37135 Phase 8 Timing Verification Phase 8.1 Update Timing Phase 8.1 Update Timing | Checksum: 2636f35c1 Time (s): cpu = 00:29:50 ; elapsed = 00:29:54 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15491 ; free virtual = 37130 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.041 | TNS=-0.051 | WHS=0.026 | THS=0.000 | Phase 8 Timing Verification | Checksum: 2636f35c1 Time (s): cpu = 00:29:51 ; elapsed = 00:29:55 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15490 ; free virtual = 37129 Phase 9 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 28.1873 % Global Horizontal Routing Utilization = 28.2939 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 4x4 Area, Max Cong = 88.964%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X84Y292 -> INT_R_X87Y295 INT_L_X76Y288 -> INT_R_X79Y291 INT_L_X80Y288 -> INT_R_X83Y291 INT_L_X76Y284 -> INT_R_X79Y287 INT_L_X92Y272 -> INT_R_X95Y275 South Dir 2x2 Area, Max Cong = 89.8649%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X28Y330 -> INT_R_X29Y331 INT_L_X32Y328 -> INT_R_X33Y329 INT_L_X28Y324 -> INT_R_X29Y325 INT_L_X32Y324 -> INT_R_X33Y325 INT_L_X74Y242 -> INT_R_X75Y243 East Dir 16x16 Area, Max Cong = 85.2653%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X16Y324 -> INT_R_X31Y339 West Dir 8x8 Area, Max Cong = 88.511%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X24Y332 -> INT_R_X31Y339 INT_L_X104Y324 -> INT_R_X111Y331 INT_L_X112Y324 -> INT_R_X119Y331 INT_L_X104Y316 -> INT_R_X111Y323 INT_L_X112Y316 -> INT_R_X119Y323 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 1 Effective congestion level: 3 Aspect Ratio: 0.666667 Sparse Ratio: 3.5 Direction: South ---------------- Congested clusters found at Level 1 Effective congestion level: 2 Aspect Ratio: 0.666667 Sparse Ratio: 1 Direction: East ---------------- Congested clusters found at Level 4 Effective congestion level: 4 Aspect Ratio: 1 Sparse Ratio: 1 Direction: West ---------------- Congested clusters found at Level 2 Effective congestion level: 4 Aspect Ratio: 0.714286 Sparse Ratio: 1.5625 Phase 9 Route finalize | Checksum: 2636f35c1 Time (s): cpu = 00:29:53 ; elapsed = 00:29:58 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15489 ; free virtual = 37129 Phase 10 Verifying routed nets Verification completed successfully Phase 10 Verifying routed nets | Checksum: 2636f35c1 Time (s): cpu = 00:29:55 ; elapsed = 00:29:59 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15489 ; free virtual = 37128 Phase 11 Depositing Routes Phase 11 Depositing Routes | Checksum: 209ba43c8 Time (s): cpu = 00:30:23 ; elapsed = 00:30:27 . Memory (MB): peak = 9694.797 ; gain = 324.578 ; free physical = 15488 ; free virtual = 37128 Phase 12 Incr Placement Change Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9694.797 ; gain = 0.000 ; free physical = 15488 ; free virtual = 37128 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.071. For the most accurate timing information please run report_timing. Ending IncrPlace Task | Checksum: 335d0a44 Time (s): cpu = 00:04:27 ; elapsed = 00:04:29 . Memory (MB): peak = 10318.695 ; gain = 623.898 ; free physical = 14864 ; free virtual = 36506 Phase 12 Incr Placement Change | Checksum: 335d0a44 Time (s): cpu = 00:34:59 ; elapsed = 00:35:05 . Memory (MB): peak = 10318.695 ; gain = 948.477 ; free physical = 14864 ; free virtual = 36505 Phase 13 Build RT Design Checksum: PlaceDB: 2f86ce5 ConstDB: 0 ShapeSum: 3643dd0 RouteDB: 2d005f8f Post Restoration Checksum: NetGraph: 41c390ec | NumContArr: d309c624 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 13 Build RT Design | Checksum: 29a1f4c4a Time (s): cpu = 00:36:29 ; elapsed = 00:36:35 . Memory (MB): peak = 10318.695 ; gain = 948.477 ; free physical = 14877 ; free virtual = 36520 Phase 14 Router Initialization Phase 14.1 Fix Topology Constraints Phase 14.1 Fix Topology Constraints | Checksum: 29a1f4c4a Time (s): cpu = 00:36:32 ; elapsed = 00:36:38 . Memory (MB): peak = 10318.695 ; gain = 948.477 ; free physical = 14877 ; free virtual = 36520 Phase 14.2 Pre Route Cleanup Phase 14.2 Pre Route Cleanup | Checksum: 1d5cd9d25 Time (s): cpu = 00:36:35 ; elapsed = 00:36:41 . Memory (MB): peak = 10318.695 ; gain = 948.477 ; free physical = 14887 ; free virtual = 36530 Number of Nodes with overlaps = 0 Phase 14.3 Update Timing Phase 14.3 Update Timing | Checksum: 1e0a07239 Time (s): cpu = 00:38:52 ; elapsed = 00:38:59 . Memory (MB): peak = 10318.695 ; gain = 948.477 ; free physical = 14867 ; free virtual = 36510 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.028 | TNS=-0.137 | WHS=-0.483 | THS=-11299.071| Phase 14.4 Update Timing for Bus Skew Phase 14.4.1 Update Timing Phase 14.4.1 Update Timing | Checksum: 1624c9f09 Time (s): cpu = 00:40:09 ; elapsed = 00:40:16 . Memory (MB): peak = 10372.695 ; gain = 1002.477 ; free physical = 14806 ; free virtual = 36450 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.028 | TNS=0.000 | WHS=-0.086 | THS=-0.498 | Phase 14.4 Update Timing for Bus Skew | Checksum: 17899431d Time (s): cpu = 00:40:11 ; elapsed = 00:40:17 . Memory (MB): peak = 10372.695 ; gain = 1002.477 ; free physical = 14806 ; free virtual = 36450 Router Utilization Summary Global Vertical Routing Utilization = 27.899 % Global Horizontal Routing Utilization = 28.1242 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 2923 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 2053 Number of Partially Routed Nets = 870 Number of Node Overlaps = 0 Phase 14 Router Initialization | Checksum: 24cadd634 Time (s): cpu = 00:40:17 ; elapsed = 00:40:23 . Memory (MB): peak = 10372.695 ; gain = 1002.477 ; free physical = 14810 ; free virtual = 36454 Phase 15 Global Routing Phase 15 Global Routing | Checksum: 24cadd634 Time (s): cpu = 00:40:18 ; elapsed = 00:40:24 . Memory (MB): peak = 10372.695 ; gain = 1002.477 ; free physical = 14810 ; free virtual = 36454 Phase 16 Initial Routing Phase 16.1 Initial Net Routing Pass Phase 16.1 Initial Net Routing Pass | Checksum: 219ee9142 Time (s): cpu = 00:40:26 ; elapsed = 00:40:32 . Memory (MB): peak = 10372.695 ; gain = 1002.477 ; free physical = 14815 ; free virtual = 36459 Phase 16 Initial Routing | Checksum: 219ee9142 Time (s): cpu = 00:40:28 ; elapsed = 00:40:34 . Memory (MB): peak = 10372.695 ; gain = 1002.477 ; free physical = 14815 ; free virtual = 36459 Phase 17 Rip-up And Reroute Phase 17.1 Global Iteration 0 Number of Nodes with overlaps = 2944 Number of Nodes with overlaps = 863 Number of Nodes with overlaps = 270 Number of Nodes with overlaps = 114 Number of Nodes with overlaps = 38 Number of Nodes with overlaps = 28 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.133 | TNS=-0.387 | WHS=N/A | THS=N/A | Phase 17.1 Global Iteration 0 | Checksum: 267690fd7 Time (s): cpu = 00:44:46 ; elapsed = 00:44:53 . Memory (MB): peak = 10516.062 ; gain = 1145.844 ; free physical = 14652 ; free virtual = 36299 Phase 17.2 Global Iteration 1 Number of Nodes with overlaps = 2628 Number of Nodes with overlaps = 822 Number of Nodes with overlaps = 325 Number of Nodes with overlaps = 167 Number of Nodes with overlaps = 73 Number of Nodes with overlaps = 56 Number of Nodes with overlaps = 24 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.037 | TNS=-0.105 | WHS=N/A | THS=N/A | Phase 17.2 Global Iteration 1 | Checksum: 293241f17 Time (s): cpu = 00:47:22 ; elapsed = 00:47:30 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14640 ; free virtual = 36290 Phase 17.3 Global Iteration 2 Number of Nodes with overlaps = 2370 Number of Nodes with overlaps = 589 Number of Nodes with overlaps = 216 Number of Nodes with overlaps = 72 Number of Nodes with overlaps = 40 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.069 | TNS=-0.201 | WHS=N/A | THS=N/A | Phase 17.3 Global Iteration 2 | Checksum: 2701a977a Time (s): cpu = 00:49:20 ; elapsed = 00:49:28 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14639 ; free virtual = 36290 Phase 17 Rip-up And Reroute | Checksum: 2701a977a Time (s): cpu = 00:49:21 ; elapsed = 00:49:29 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14639 ; free virtual = 36290 Phase 18 Delay and Skew Optimization Phase 18.1 Delay CleanUp Phase 18.1.1 Update Timing Phase 18.1.1 Update Timing | Checksum: 2332aae1e Time (s): cpu = 00:49:50 ; elapsed = 00:49:58 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14635 ; free virtual = 36286 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.038 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 18.1 Delay CleanUp | Checksum: 1b5dffebf Time (s): cpu = 00:49:52 ; elapsed = 00:49:59 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14635 ; free virtual = 36286 Phase 18.2 Clock Skew Optimization Phase 18.2 Clock Skew Optimization | Checksum: 1b5dffebf Time (s): cpu = 00:49:53 ; elapsed = 00:50:00 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14637 ; free virtual = 36288 Phase 18 Delay and Skew Optimization | Checksum: 1b5dffebf Time (s): cpu = 00:49:54 ; elapsed = 00:50:01 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14637 ; free virtual = 36288 Phase 19 Post Hold Fix Phase 19.1 Hold Fix Iter INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.038 | TNS=0.000 | WHS=0.026 | THS=0.000 | Phase 19.1 Hold Fix Iter | Checksum: 2450fa646 Time (s): cpu = 00:50:26 ; elapsed = 00:50:33 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14648 ; free virtual = 36299 Phase 19 Post Hold Fix | Checksum: 2450fa646 Time (s): cpu = 00:50:27 ; elapsed = 00:50:34 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14648 ; free virtual = 36299 Phase 20 Timing Verification Phase 20.1 Update Timing Phase 20.1 Update Timing | Checksum: 293a45bae Time (s): cpu = 00:51:10 ; elapsed = 00:51:18 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14650 ; free virtual = 36302 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.038 | TNS=0.000 | WHS=0.026 | THS=0.000 | Phase 20 Timing Verification | Checksum: 293a45bae Time (s): cpu = 00:51:11 ; elapsed = 00:51:19 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14650 ; free virtual = 36302 Phase 21 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 28.2447 % Global Horizontal Routing Utilization = 28.4343 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 21 Route finalize | Checksum: 293a45bae Time (s): cpu = 00:51:14 ; elapsed = 00:51:21 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14650 ; free virtual = 36301 Phase 22 Verifying routed nets Verification completed successfully Phase 22 Verifying routed nets | Checksum: 293a45bae Time (s): cpu = 00:51:15 ; elapsed = 00:51:23 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14649 ; free virtual = 36301 Phase 23 Depositing Routes Phase 23 Depositing Routes | Checksum: 27d80aa2d Time (s): cpu = 00:51:43 ; elapsed = 00:51:51 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14647 ; free virtual = 36299 Phase 24 Post Process Routing Phase 24 Post Process Routing | Checksum: 27d80aa2d Time (s): cpu = 00:51:45 ; elapsed = 00:51:52 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14647 ; free virtual = 36299 Phase 25 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.038 | TNS=0.000 | WHS=0.027 | THS=0.000 | Phase 25 Post Router Timing | Checksum: 1b2c94172 Time (s): cpu = 00:53:21 ; elapsed = 00:53:29 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14656 ; free virtual = 36308 INFO: [Route 35-61] The design met the timing requirement. Total Elapsed time in route_design: 3209.59 secs Phase 26 Post-Route Event Processing Phase 26 Post-Route Event Processing | Checksum: 84ebbbea Time (s): cpu = 00:53:25 ; elapsed = 00:53:33 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14654 ; free virtual = 36307 INFO: [Route 35-16] Router Completed Successfully Ending Routing Task | Checksum: 84ebbbea Time (s): cpu = 00:53:31 ; elapsed = 00:53:38 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14653 ; free virtual = 36305 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 536 Infos, 6 Warnings, 3 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:53:36 ; elapsed = 00:53:44 . Memory (MB): peak = 10532.430 ; gain = 1162.211 ; free physical = 14654 ; free virtual = 36307 INFO: [Vivado 12-24828] Executing command : report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx Command: report_drc -file top_efex_processor_drc_routed.rpt -pb top_efex_processor_drc_routed.pb -rpx top_efex_processor_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.4/efex_hi_processor.4.runs/impl_1/top_efex_processor_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:15 ; elapsed = 00:01:15 . Memory (MB): peak = 10532.430 ; gain = 0.000 ; free physical = 14627 ; free virtual = 36285 INFO: [Vivado 12-24828] Executing command : report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx Command: report_methodology -file top_efex_processor_methodology_drc_routed.rpt -pb top_efex_processor_methodology_drc_routed.pb -rpx top_efex_processor_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /builds/atlas-l1calo-efex/eFEXFirmware/Projects/efex_hi_processor.4/efex_hi_processor.4.runs/impl_1/top_efex_processor_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:52 ; elapsed = 00:02:53 . Memory (MB): peak = 10532.430 ; gain = 0.000 ; free physical = 14632 ; free virtual = 36291 INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_efex_processor_timing_summary_routed.rpt -pb top_efex_processor_timing_summary_routed.pb -rpx top_efex_processor_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:01:35 ; elapsed = 00:01:36 . Memory (MB): peak = 10532.430 ; gain = 0.000 ; free physical = 14539 ; free virtual = 36284 INFO: [Vivado 12-24828] Executing command : report_timing_summary -file top_efex_processor_timing_summary_routed_1.rpt -pb top_efex_processor_timing_summary_routed_1.pb -rpx top_efex_processor_timing_summary_routed_1.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 10532.430 ; gain = 0.000 ; free physical = 14531 ; free virtual = 36279 INFO: [Vivado 12-24828] Executing command : report_route_status -file top_efex_processor_route_status.rpt -pb top_efex_processor_route_status.pb report_route_status: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 10532.430 ; gain = 0.000 ; free physical = 14530 ; free virtual = 36278 INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_efex_processor_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [Vivado 12-24828] Executing command : report_utilization -file route_report_utilization_0.rpt -pb route_report_utilization_0.pb INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_efex_processor_bus_skew_routed.rpt -pb top_efex_processor_bus_skew_routed.pb -rpx top_efex_processor_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Vivado 12-24828] Executing command : report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx Command: report_power -file top_efex_processor_power_routed.rpt -pb top_efex_processor_power_summary_routed.pb -rpx top_efex_processor_power_routed.rpx INFO: [Power 33-23] Power model is not available for STARTUPE2_inst Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 555 Infos, 9 Warnings, 3 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:18 ; elapsed = 00:00:57 . Memory (MB): peak = 10676.434 ; gain = 144.004 ; free physical = 14430 ; free virtual = 36199 INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_efex_processor_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 10676.434 ; gain = 0.000 ; free physical = 14438 ; free virtual = 36207 generate_parallel_reports: Time (s): cpu = 00:07:49 ; elapsed = 00:07:34 . Memory (MB): peak = 10676.434 ; gain = 144.004 ; free physical = 14438 ; free virtual = 36207 source /builds/atlas-l1calo-efex/eFEXFirmware/Hog/Tcl/integrated/post-implementation.tcl INFO: [Hog:Msg-0] Evaluating Git sha for efex_hi_processor.4... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_hi_processor.4 clean. WARNING: [Hog:GetLinkedFile-0] ./list/efex_processor.ipb is a broken link, because the linked file: /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.4/efex_processor.1/list/efex_processor.ipb does not exist. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Evaluating last git SHA in which efex_hi_processor.4 was modified... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_hi_processor.4 clean. WARNING: [Hog:GetLinkedFile-0] ./list/efex_processor.ipb is a broken link, because the linked file: /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.4/efex_processor.1/list/efex_processor.ipb does not exist. INFO: [Hog:Msg-0] The git SHA value ea29254 will be embedded in the binary file. INFO: [Hog:Msg-0] Evaluating Git sha for efex_hi_processor.4... INFO: [Hog:GetRepoVersions-0] Hog submodule /builds/atlas-l1calo-efex/eFEXFirmware/Hog clean. INFO: [Hog:GetRepoVersions-0] Git working directory /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_hi_processor.4 clean. WARNING: [Hog:GetLinkedFile-0] ./list/efex_processor.ipb is a broken link, because the linked file: /builds/atlas-l1calo-efex/eFEXFirmware/Top/efex_processor.4/efex_processor.1/list/efex_processor.ipb does not exist. INFO: [Hog:Msg-0] Git describe set to: v1.7.3-EA29254 INFO: [Hog:Msg-0] Creating /builds/atlas-l1calo-efex/eFEXFirmware/bin/efex_hi_processor.4-v1.7.3-EA29254... INFO: [Hog:Msg-0] Evaluating differences with last commit... INFO: [Hog:Msg-0] No uncommitted changes found. report_utilization: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 10676.434 ; gain = 0.000 ; free physical = 14449 ; free virtual = 36225