CON_2Quads_6g4_CON_2Quads_6g4_GT Entity Reference

Collaboration diagram for CON_2Quads_6g4_CON_2Quads_6g4_GT:

Entities
STRUCTURE	architecture

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
VCOMPONENTS

Ports
gt0_drprdy_out	out STD_LOGIC
gt0_eyescandataerror_out	out STD_LOGIC
gt0_gtxtxn_out	out STD_LOGIC
gt0_gtxtxp_out	out STD_LOGIC
gt0_rxbyteisaligned_out	out STD_LOGIC
gt0_rxbyterealign_out	out STD_LOGIC
gt0_rxcommadet_out	out STD_LOGIC
gt0_rxdlysresetdone_out	out STD_LOGIC
gt0_rxoutclk_out	out STD_LOGIC
gt0_rxoutclkfabric_out	out STD_LOGIC
gt0_rxphaligndone_out	out STD_LOGIC
gt0_rxresetdone_out	out STD_LOGIC
gt0_txdlysresetdone_out	out STD_LOGIC
gt0_txoutclk_out	out STD_LOGIC
gt0_txoutclkfabric_out	out STD_LOGIC
gt0_txoutclkpcs_out	out STD_LOGIC
gt0_txphaligndone_out	out STD_LOGIC
gt0_txphinitdone_out	out STD_LOGIC
gt0_txresetdone_out	out STD_LOGIC
gt0_drpdo_out	out STD_LOGIC_VECTOR ( 15 downto 0 )
gt0_rxphmonitor_out	out STD_LOGIC_VECTOR ( 4 downto 0 )
gt0_rxphslipmonitor_out	out STD_LOGIC_VECTOR ( 4 downto 0 )
gt0_rxdata_out	out STD_LOGIC_VECTOR ( 31 downto 0 )
gt0_rxmonitorout_out	out STD_LOGIC_VECTOR ( 6 downto 0 )
gt0_dmonitorout_out	out STD_LOGIC_VECTOR ( 7 downto 0 )
gt0_rxcharisk_out	out STD_LOGIC_VECTOR ( 3 downto 0 )
gt0_rxdisperr_out	out STD_LOGIC_VECTOR ( 3 downto 0 )
gt0_rxnotintable_out	out STD_LOGIC_VECTOR ( 3 downto 0 )
gt0_drpclk_in_0	out STD_LOGIC
gt0_drpclk_in	in STD_LOGIC
gt0_drpen_in	in STD_LOGIC
gt0_drpwe_in	in STD_LOGIC
gt0_eyescanreset_in	in STD_LOGIC
gt0_eyescantrigger_in	in STD_LOGIC
gt0_gtrxreset_t	in STD_LOGIC
gt0_gttxreset_in	in STD_LOGIC
gt0_gtxrxn_in	in STD_LOGIC
gt0_gtxrxp_in	in STD_LOGIC
GT0_QPLLOUTCLK_IN	in STD_LOGIC
GT0_QPLLOUTREFCLK_IN	in STD_LOGIC
gt0_rxdfelpmreset_in	in STD_LOGIC
gt0_rxdlyen_in	in STD_LOGIC
U0_RXDLYSRESET	in STD_LOGIC_VECTOR ( 0 to 0 )
U0_RXPHALIGN	in STD_LOGIC_VECTOR ( 0 to 0 )
gt0_rxpmareset_in	in STD_LOGIC
gt0_rxuserrdy_in	in STD_LOGIC
gt0_rxusrclk_in	in STD_LOGIC
gt0_rxusrclk2_in	in STD_LOGIC
gt0_txdlyen_in	in STD_LOGIC
U0_TXDLYSRESET	in STD_LOGIC_VECTOR ( 0 to 0 )
U0_TXPHALIGN	in STD_LOGIC_VECTOR ( 0 to 0 )
U0_TXPHINIT	in STD_LOGIC_VECTOR ( 0 to 0 )
gt0_txuserrdy_in	in STD_LOGIC
gt0_txusrclk_in	in STD_LOGIC
gt0_txusrclk2_in	in STD_LOGIC
gt0_drpdi_in	in STD_LOGIC_VECTOR ( 15 downto 0 )
gt0_rxmonitorsel_in	in STD_LOGIC_VECTOR ( 1 downto 0 )
gt0_loopback_in	in STD_LOGIC_VECTOR ( 2 downto 0 )
gt0_txprbssel_in	in STD_LOGIC_VECTOR ( 2 downto 0 )
gt0_txdiffctrl_in	in STD_LOGIC_VECTOR ( 3 downto 0 )
gt0_txdata_in	in STD_LOGIC_VECTOR ( 31 downto 0 )
gt0_txcharisk_in	in STD_LOGIC_VECTOR ( 3 downto 0 )
gt0_drpaddr_in	in STD_LOGIC_VECTOR ( 8 downto 0 )

Attributes
ORIG_REF_NAME	string
ORIG_REF_NAME	CON_2Quads_6g4_CON_2Quads_6g4_GT : entity is " CON_2Quads_6g4_GT "

Member Data Documentation

gt0_dmonitorout_out

gt0_dmonitorout_out out STD_LOGIC_VECTOR ( 7 downto 0 )

Port

gt0_drpaddr_in

gt0_drpaddr_in in STD_LOGIC_VECTOR ( 8 downto 0 )

Port

gt0_drpclk_in

gt0_drpclk_in in STD_LOGIC

Port

gt0_drpclk_in_0

gt0_drpclk_in_0 out STD_LOGIC

Port

gt0_drpdi_in

gt0_drpdi_in in STD_LOGIC_VECTOR ( 15 downto 0 )

Port

gt0_drpdo_out

gt0_drpdo_out out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

gt0_drpen_in

gt0_drpen_in in STD_LOGIC

Port

gt0_drprdy_out

gt0_drprdy_out out STD_LOGIC

Port

gt0_drpwe_in

gt0_drpwe_in in STD_LOGIC

Port

gt0_eyescandataerror_out

gt0_eyescandataerror_out out STD_LOGIC

Port

gt0_eyescanreset_in

gt0_eyescanreset_in in STD_LOGIC

Port

gt0_eyescantrigger_in

gt0_eyescantrigger_in in STD_LOGIC

Port

gt0_gtrxreset_t

gt0_gtrxreset_t in STD_LOGIC

Port

gt0_gttxreset_in

gt0_gttxreset_in in STD_LOGIC

Port

gt0_gtxrxn_in

gt0_gtxrxn_in in STD_LOGIC

Port

gt0_gtxrxp_in

gt0_gtxrxp_in in STD_LOGIC

Port

gt0_gtxtxn_out

gt0_gtxtxn_out out STD_LOGIC

Port

gt0_gtxtxp_out

gt0_gtxtxp_out out STD_LOGIC

Port

gt0_loopback_in

gt0_loopback_in in STD_LOGIC_VECTOR ( 2 downto 0 )

Port

GT0_QPLLOUTCLK_IN

GT0_QPLLOUTCLK_IN in STD_LOGIC

Port

GT0_QPLLOUTREFCLK_IN

GT0_QPLLOUTREFCLK_IN in STD_LOGIC

Port

gt0_rxbyteisaligned_out

gt0_rxbyteisaligned_out out STD_LOGIC

Port

gt0_rxbyterealign_out

gt0_rxbyterealign_out out STD_LOGIC

Port

gt0_rxcharisk_out

gt0_rxcharisk_out out STD_LOGIC_VECTOR ( 3 downto 0 )

Port

gt0_rxcommadet_out

gt0_rxcommadet_out out STD_LOGIC

Port

gt0_rxdata_out

gt0_rxdata_out out STD_LOGIC_VECTOR ( 31 downto 0 )

Port

gt0_rxdfelpmreset_in

gt0_rxdfelpmreset_in in STD_LOGIC

Port

gt0_rxdisperr_out

gt0_rxdisperr_out out STD_LOGIC_VECTOR ( 3 downto 0 )

Port

gt0_rxdlyen_in

gt0_rxdlyen_in in STD_LOGIC

Port

gt0_rxdlysresetdone_out

gt0_rxdlysresetdone_out out STD_LOGIC

Port

gt0_rxmonitorout_out

gt0_rxmonitorout_out out STD_LOGIC_VECTOR ( 6 downto 0 )

Port

gt0_rxmonitorsel_in

gt0_rxmonitorsel_in in STD_LOGIC_VECTOR ( 1 downto 0 )

Port

gt0_rxnotintable_out

gt0_rxnotintable_out out STD_LOGIC_VECTOR ( 3 downto 0 )

Port

gt0_rxoutclk_out

gt0_rxoutclk_out out STD_LOGIC

Port

gt0_rxoutclkfabric_out

gt0_rxoutclkfabric_out out STD_LOGIC

Port

gt0_rxphaligndone_out

gt0_rxphaligndone_out out STD_LOGIC

Port

gt0_rxphmonitor_out

gt0_rxphmonitor_out out STD_LOGIC_VECTOR ( 4 downto 0 )

Port

gt0_rxphslipmonitor_out

gt0_rxphslipmonitor_out out STD_LOGIC_VECTOR ( 4 downto 0 )

Port

gt0_rxpmareset_in

gt0_rxpmareset_in in STD_LOGIC

Port

gt0_rxresetdone_out

gt0_rxresetdone_out out STD_LOGIC

Port

gt0_rxuserrdy_in

gt0_rxuserrdy_in in STD_LOGIC

Port

gt0_rxusrclk2_in

gt0_rxusrclk2_in in STD_LOGIC

Port

gt0_rxusrclk_in

gt0_rxusrclk_in in STD_LOGIC

Port

gt0_txcharisk_in

gt0_txcharisk_in in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

gt0_txdata_in

gt0_txdata_in in STD_LOGIC_VECTOR ( 31 downto 0 )

Port

gt0_txdiffctrl_in

gt0_txdiffctrl_in in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

gt0_txdlyen_in

gt0_txdlyen_in in STD_LOGIC

Port

gt0_txdlysresetdone_out

gt0_txdlysresetdone_out out STD_LOGIC

Port

gt0_txoutclk_out

gt0_txoutclk_out out STD_LOGIC

Port

gt0_txoutclkfabric_out

gt0_txoutclkfabric_out out STD_LOGIC

Port

gt0_txoutclkpcs_out

gt0_txoutclkpcs_out out STD_LOGIC

Port

gt0_txphaligndone_out

gt0_txphaligndone_out out STD_LOGIC

Port

gt0_txphinitdone_out

gt0_txphinitdone_out out STD_LOGIC

Port

gt0_txprbssel_in

gt0_txprbssel_in in STD_LOGIC_VECTOR ( 2 downto 0 )

Port

gt0_txresetdone_out

gt0_txresetdone_out out STD_LOGIC

Port

gt0_txuserrdy_in

gt0_txuserrdy_in in STD_LOGIC

Port

gt0_txusrclk2_in

gt0_txusrclk2_in in STD_LOGIC

Port

gt0_txusrclk_in

gt0_txusrclk_in in STD_LOGIC

Port

IEEE

IEEE

Library

ORIG_REF_NAME [1/2]

ORIG_REF_NAME string

Attribute

ORIG_REF_NAME [2/2]

ORIG_REF_NAME CON_2Quads_6g4_CON_2Quads_6g4_GT : entity is " CON_2Quads_6g4_GT "

Attribute

STD_LOGIC_1164

STD_LOGIC_1164

Package

U0_RXDLYSRESET

U0_RXDLYSRESET in STD_LOGIC_VECTOR ( 0 to 0 )

Port

U0_RXPHALIGN

U0_RXPHALIGN in STD_LOGIC_VECTOR ( 0 to 0 )

Port

U0_TXDLYSRESET

U0_TXDLYSRESET in STD_LOGIC_VECTOR ( 0 to 0 )

Port

U0_TXPHALIGN

U0_TXPHALIGN in STD_LOGIC_VECTOR ( 0 to 0 )

Port

U0_TXPHINIT

U0_TXPHINIT in STD_LOGIC_VECTOR ( 0 to 0 )

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• IP/CON_2Quads_6g4/CON_2Quads_6g4_sim_netlist.vhdl