CON_2Quads_6g4_GT Entity Reference

Inheritance diagram for CON_2Quads_6g4_GT:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
GT_SIM_GTRESET_SPEEDUP	string := " FALSE "
RX_DFE_KL_CFG2_IN	bit_vector := X " 301148AC "
SIM_CPLLREFCLK_SEL	bit_vector := " 001 "
PMA_RSV_IN	bit_vector := x " 00018480 "
PCS_RSVD_ATTR_IN	bit_vector := X " 000000000000 "

Ports
cpllrefclksel_in	in std_logic_vector ( 2 downto 0 )
drpaddr_in	in std_logic_vector ( 8 downto 0 )
drpclk_in	in std_logic
drpdi_in	in std_logic_vector ( 15 downto 0 )
drpdo_out	out std_logic_vector ( 15 downto 0 )
drpen_in	in std_logic
drprdy_out	out std_logic
drpwe_in	in std_logic
qpllclk_in	in std_logic
qpllrefclk_in	in std_logic
dmonitorout_out	out std_logic_vector ( 7 downto 0 )
loopback_in	in std_logic_vector ( 2 downto 0 )
eyescanreset_in	in std_logic
rxuserrdy_in	in std_logic
eyescandataerror_out	out std_logic
eyescantrigger_in	in std_logic
rxusrclk_in	in std_logic
rxusrclk2_in	in std_logic
rxdata_out	out std_logic_vector ( 31 downto 0 )
rxdisperr_out	out std_logic_vector ( 3 downto 0 )
rxnotintable_out	out std_logic_vector ( 3 downto 0 )
gtxrxp_in	in std_logic
gtxrxn_in	in std_logic
rxdlyen_in	in std_logic
rxdlysreset_in	in std_logic
rxdlysresetdone_out	out std_logic
rxphalign_in	in std_logic
rxphaligndone_out	out std_logic
rxphalignen_in	in std_logic
rxphdlyreset_in	in std_logic
rxphmonitor_out	out std_logic_vector ( 4 downto 0 )
rxphslipmonitor_out	out std_logic_vector ( 4 downto 0 )
rxbyteisaligned_out	out std_logic
rxbyterealign_out	out std_logic
rxcommadet_out	out std_logic
rxlpmhfhold_in	in std_logic
rxlpmlfhold_in	in std_logic
rxdfelpmreset_in	in std_logic
rxmonitorout_out	out std_logic_vector ( 6 downto 0 )
rxmonitorsel_in	in std_logic_vector ( 1 downto 0 )
rxoutclk_out	out std_logic
rxoutclkfabric_out	out std_logic
gtrxreset_in	in std_logic
rxpmareset_in	in std_logic
rxcharisk_out	out std_logic_vector ( 3 downto 0 )
rxresetdone_out	out std_logic
gttxreset_in	in std_logic
txuserrdy_in	in std_logic
txusrclk_in	in std_logic
txusrclk2_in	in std_logic
txdlyen_in	in std_logic
txdlysreset_in	in std_logic
txdlysresetdone_out	out std_logic
txphalign_in	in std_logic
txphaligndone_out	out std_logic
txphalignen_in	in std_logic
txphdlyreset_in	in std_logic
txphinit_in	in std_logic
txphinitdone_out	out std_logic
txdiffctrl_in	in std_logic_vector ( 3 downto 0 )
txdata_in	in std_logic_vector ( 31 downto 0 )
gtxtxn_out	out std_logic
gtxtxp_out	out std_logic
txoutclk_out	out std_logic
txoutclkfabric_out	out std_logic
txoutclkpcs_out	out std_logic
txcharisk_in	in std_logic_vector ( 3 downto 0 )
txresetdone_out	out std_logic
txprbssel_in	in std_logic_vector ( 2 downto 0 )

Member Data Documentation

cpllrefclksel_in

cpllrefclksel_in in std_logic_vector ( 2 downto 0 )

Port

dmonitorout_out

dmonitorout_out out std_logic_vector ( 7 downto 0 )

Port

drpaddr_in

drpaddr_in in std_logic_vector ( 8 downto 0 )

Port

drpclk_in

drpclk_in in std_logic

Port

drpdi_in

drpdi_in in std_logic_vector ( 15 downto 0 )

Port

drpdo_out

drpdo_out out std_logic_vector ( 15 downto 0 )

Port

drpen_in

drpen_in in std_logic

Port

drprdy_out

drprdy_out out std_logic

Port

drpwe_in

drpwe_in in std_logic

Port

eyescandataerror_out

eyescandataerror_out out std_logic

Port

eyescanreset_in

eyescanreset_in in std_logic

Port

eyescantrigger_in

eyescantrigger_in in std_logic

Port

GT_SIM_GTRESET_SPEEDUP

GT_SIM_GTRESET_SPEEDUP string := " FALSE "

Generic

gtrxreset_in

gtrxreset_in in std_logic

Port

gttxreset_in

gttxreset_in in std_logic

Port

gtxrxn_in

gtxrxn_in in std_logic

Port

gtxrxp_in

gtxrxp_in in std_logic

Port

gtxtxn_out

gtxtxn_out out std_logic

Port

gtxtxp_out

gtxtxp_out out std_logic

Port

ieee

ieee

Library

loopback_in

loopback_in in std_logic_vector ( 2 downto 0 )

Port

numeric_std

numeric_std

Package

PCS_RSVD_ATTR_IN

PCS_RSVD_ATTR_IN bit_vector := X " 000000000000 "

Generic

PMA_RSV_IN

PMA_RSV_IN bit_vector := x " 00018480 "

Generic

qpllclk_in

qpllclk_in in std_logic

Port

qpllrefclk_in

qpllrefclk_in in std_logic

Port

RX_DFE_KL_CFG2_IN

RX_DFE_KL_CFG2_IN bit_vector := X " 301148AC "

Generic

rxbyteisaligned_out

rxbyteisaligned_out out std_logic

Port

rxbyterealign_out

rxbyterealign_out out std_logic

Port

rxcharisk_out

rxcharisk_out out std_logic_vector ( 3 downto 0 )

Port

rxcommadet_out

rxcommadet_out out std_logic

Port

rxdata_out

rxdata_out out std_logic_vector ( 31 downto 0 )

Port

rxdfelpmreset_in

rxdfelpmreset_in in std_logic

Port

rxdisperr_out

rxdisperr_out out std_logic_vector ( 3 downto 0 )

Port

rxdlyen_in

rxdlyen_in in std_logic

Port

rxdlysreset_in

rxdlysreset_in in std_logic

Port

rxdlysresetdone_out

rxdlysresetdone_out out std_logic

Port

rxlpmhfhold_in

rxlpmhfhold_in in std_logic

Port

rxlpmlfhold_in

rxlpmlfhold_in in std_logic

Port

rxmonitorout_out

rxmonitorout_out out std_logic_vector ( 6 downto 0 )

Port

rxmonitorsel_in

rxmonitorsel_in in std_logic_vector ( 1 downto 0 )

Port

rxnotintable_out

rxnotintable_out out std_logic_vector ( 3 downto 0 )

Port

rxoutclk_out

rxoutclk_out out std_logic

Port

rxoutclkfabric_out

rxoutclkfabric_out out std_logic

Port

rxphalign_in

rxphalign_in in std_logic

Port

rxphaligndone_out

rxphaligndone_out out std_logic

Port

rxphalignen_in

rxphalignen_in in std_logic

Port

rxphdlyreset_in

rxphdlyreset_in in std_logic

Port

rxphmonitor_out

rxphmonitor_out out std_logic_vector ( 4 downto 0 )

Port

rxphslipmonitor_out

rxphslipmonitor_out out std_logic_vector ( 4 downto 0 )

Port

rxpmareset_in

rxpmareset_in in std_logic

Port

rxresetdone_out

rxresetdone_out out std_logic

Port

rxuserrdy_in

rxuserrdy_in in std_logic

Port

rxusrclk2_in

rxusrclk2_in in std_logic

Port

rxusrclk_in

rxusrclk_in in std_logic

Port

SIM_CPLLREFCLK_SEL

SIM_CPLLREFCLK_SEL bit_vector := " 001 "

Generic

std_logic_1164

std_logic_1164

Package

txcharisk_in

txcharisk_in in std_logic_vector ( 3 downto 0 )

Port

txdata_in

txdata_in in std_logic_vector ( 31 downto 0 )

Port

txdiffctrl_in

txdiffctrl_in in std_logic_vector ( 3 downto 0 )

Port

txdlyen_in

txdlyen_in in std_logic

Port

txdlysreset_in

txdlysreset_in in std_logic

Port

txdlysresetdone_out

txdlysresetdone_out out std_logic

Port

txoutclk_out

txoutclk_out out std_logic

Port

txoutclkfabric_out

txoutclkfabric_out out std_logic

Port

txoutclkpcs_out

txoutclkpcs_out out std_logic

Port

txphalign_in

txphalign_in in std_logic

Port

txphaligndone_out

txphaligndone_out out std_logic

Port

txphalignen_in

txphalignen_in in std_logic

Port

txphdlyreset_in

txphdlyreset_in in std_logic

Port

txphinit_in

txphinit_in in std_logic

Port

txphinitdone_out

txphinitdone_out out std_logic

Port

txprbssel_in

txprbssel_in in std_logic_vector ( 2 downto 0 )

Port

txresetdone_out

txresetdone_out out std_logic

Port

txuserrdy_in

txuserrdy_in in std_logic

Port

txusrclk2_in

txusrclk2_in in std_logic

Port

txusrclk_in

txusrclk_in in std_logic

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• IP/CON_2Quads_6g4/con_2quads_6g4_gt.vhd