CON_2Quads_6g4_RX_STARTUP_FSM Entity Reference

Inheritance diagram for CON_2Quads_6g4_RX_STARTUP_FSM:

Collaboration diagram for CON_2Quads_6g4_RX_STARTUP_FSM:

Entities
RTL	architecture

Libraries
IEEE
unisim

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
vcomponents

Generics
EXAMPLE_SIMULATION	integer := 0
EQ_MODE	string := " DFE "
STABLE_CLOCK_PERIOD	integer range 4 to 250 := 8
RETRY_COUNTER_BITWIDTH	integer range 2 to 8 := 8
TX_QPLL_USED	boolean := False
RX_QPLL_USED	boolean := False
PHASE_ALIGNMENT_MANUAL	boolean := True

Ports
STABLE_CLOCK	in STD_LOGIC
RXUSERCLK	in STD_LOGIC
SOFT_RESET	in STD_LOGIC
QPLLREFCLKLOST	in STD_LOGIC
CPLLREFCLKLOST	in STD_LOGIC
QPLLLOCK	in STD_LOGIC
CPLLLOCK	in STD_LOGIC
RXRESETDONE	in STD_LOGIC
MMCM_LOCK	in STD_LOGIC
RECCLK_STABLE	in STD_LOGIC
RECCLK_MONITOR_RESTART	in STD_LOGIC := ' 0 '
DATA_VALID	in STD_LOGIC
TXUSERRDY	in STD_LOGIC
DONT_RESET_ON_DATA_ERROR	in STD_LOGIC
GTRXRESET	out STD_LOGIC
MMCM_RESET	out STD_LOGIC
QPLL_RESET	out STD_LOGIC := ' 0 '
CPLL_RESET	out STD_LOGIC := ' 0 '
RX_FSM_RESET_DONE	out STD_LOGIC
RXUSERRDY	out STD_LOGIC := ' 0 '
RUN_PHALIGNMENT	out STD_LOGIC
PHALIGNMENT_DONE	in STD_LOGIC
RESET_PHALIGNMENT	out STD_LOGIC := ' 0 '
RXDFEAGCHOLD	out STD_LOGIC
RXDFELFHOLD	out STD_LOGIC
RXLPMLFHOLD	out STD_LOGIC
RXLPMHFHOLD	out STD_LOGIC
RETRY_COUNTER	out STD_LOGIC_VECTOR ( RETRY_COUNTER_BITWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Member Data Documentation

CPLL_RESET

CPLL_RESET out STD_LOGIC := ' 0 '

Port

CPLLLOCK

CPLLLOCK in STD_LOGIC

Port

CPLLREFCLKLOST

CPLLREFCLKLOST in STD_LOGIC

Port

DATA_VALID

DATA_VALID in STD_LOGIC

Port

DONT_RESET_ON_DATA_ERROR

DONT_RESET_ON_DATA_ERROR in STD_LOGIC

Port

EQ_MODE

EQ_MODE string := " DFE "

Generic

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

GTRXRESET

GTRXRESET out STD_LOGIC

Port

IEEE

IEEE

Library

MMCM_LOCK

MMCM_LOCK in STD_LOGIC

Port

MMCM_RESET

MMCM_RESET out STD_LOGIC

Port

NUMERIC_STD

NUMERIC_STD

Package

PHALIGNMENT_DONE

PHALIGNMENT_DONE in STD_LOGIC

Port

PHASE_ALIGNMENT_MANUAL

PHASE_ALIGNMENT_MANUAL boolean := True

Generic

QPLL_RESET

QPLL_RESET out STD_LOGIC := ' 0 '

Port

QPLLLOCK

QPLLLOCK in STD_LOGIC

Port

QPLLREFCLKLOST

QPLLREFCLKLOST in STD_LOGIC

Port

RECCLK_MONITOR_RESTART

RECCLK_MONITOR_RESTART in STD_LOGIC := ' 0 '

Port

RECCLK_STABLE

RECCLK_STABLE in STD_LOGIC

Port

RESET_PHALIGNMENT

RESET_PHALIGNMENT out STD_LOGIC := ' 0 '

Port

RETRY_COUNTER

RETRY_COUNTER out STD_LOGIC_VECTOR ( RETRY_COUNTER_BITWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Port

RETRY_COUNTER_BITWIDTH

RETRY_COUNTER_BITWIDTH integer range 2 to 8 := 8

Generic

RUN_PHALIGNMENT

RUN_PHALIGNMENT out STD_LOGIC

Port

RX_FSM_RESET_DONE

RX_FSM_RESET_DONE out STD_LOGIC

Port

RX_QPLL_USED

RX_QPLL_USED boolean := False

Generic

RXDFEAGCHOLD

RXDFEAGCHOLD out STD_LOGIC

Port

RXDFELFHOLD

RXDFELFHOLD out STD_LOGIC

Port

RXLPMHFHOLD

RXLPMHFHOLD out STD_LOGIC

Port

RXLPMLFHOLD

RXLPMLFHOLD out STD_LOGIC

Port

RXRESETDONE

RXRESETDONE in STD_LOGIC

Port

RXUSERCLK

RXUSERCLK in STD_LOGIC

Port

RXUSERRDY

RXUSERRDY out STD_LOGIC := ' 0 '

Port

SOFT_RESET

SOFT_RESET in STD_LOGIC

Port

STABLE_CLOCK

STABLE_CLOCK in STD_LOGIC

Port

STABLE_CLOCK_PERIOD

STABLE_CLOCK_PERIOD integer range 4 to 250 := 8

Generic

STD_LOGIC_1164

STD_LOGIC_1164

Package

TX_QPLL_USED

TX_QPLL_USED boolean := False

Generic

TXUSERRDY

TXUSERRDY in STD_LOGIC

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• IP/CON_2Quads_6g4/CON_2Quads_6g4/example_design/con_2quads_6g4_rx_startup_fsm.vhd