DSS_3Quads_11g2_GT_USRCLK_SOURCE Entity Reference

Inheritance diagram for DSS_3Quads_11g2_GT_USRCLK_SOURCE:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
VCOMPONENTS

Ports
GT0_TXUSRCLK_OUT	out std_logic
GT0_TXUSRCLK2_OUT	out std_logic
GT0_TXOUTCLK_IN	in std_logic
GT0_RXUSRCLK_OUT	out std_logic
GT0_RXUSRCLK2_OUT	out std_logic
GT0_RXOUTCLK_IN	in std_logic
GT1_TXUSRCLK_OUT	out std_logic
GT1_TXUSRCLK2_OUT	out std_logic
GT1_TXOUTCLK_IN	in std_logic
GT1_RXUSRCLK_OUT	out std_logic
GT1_RXUSRCLK2_OUT	out std_logic
GT1_RXOUTCLK_IN	in std_logic
GT2_TXUSRCLK_OUT	out std_logic
GT2_TXUSRCLK2_OUT	out std_logic
GT2_TXOUTCLK_IN	in std_logic
GT2_RXUSRCLK_OUT	out std_logic
GT2_RXUSRCLK2_OUT	out std_logic
GT2_RXOUTCLK_IN	in std_logic
GT3_TXUSRCLK_OUT	out std_logic
GT3_TXUSRCLK2_OUT	out std_logic
GT3_TXOUTCLK_IN	in std_logic
GT3_RXUSRCLK_OUT	out std_logic
GT3_RXUSRCLK2_OUT	out std_logic
GT3_RXOUTCLK_IN	in std_logic
GT4_TXUSRCLK_OUT	out std_logic
GT4_TXUSRCLK2_OUT	out std_logic
GT4_TXOUTCLK_IN	in std_logic
GT4_RXUSRCLK_OUT	out std_logic
GT4_RXUSRCLK2_OUT	out std_logic
GT4_RXOUTCLK_IN	in std_logic
GT5_TXUSRCLK_OUT	out std_logic
GT5_TXUSRCLK2_OUT	out std_logic
GT5_TXOUTCLK_IN	in std_logic
GT5_RXUSRCLK_OUT	out std_logic
GT5_RXUSRCLK2_OUT	out std_logic
GT5_RXOUTCLK_IN	in std_logic
GT6_TXUSRCLK_OUT	out std_logic
GT6_TXUSRCLK2_OUT	out std_logic
GT6_TXOUTCLK_IN	in std_logic
GT6_RXUSRCLK_OUT	out std_logic
GT6_RXUSRCLK2_OUT	out std_logic
GT6_RXOUTCLK_IN	in std_logic
GT7_TXUSRCLK_OUT	out std_logic
GT7_TXUSRCLK2_OUT	out std_logic
GT7_TXOUTCLK_IN	in std_logic
GT7_RXUSRCLK_OUT	out std_logic
GT7_RXUSRCLK2_OUT	out std_logic
GT7_RXOUTCLK_IN	in std_logic
GT8_TXUSRCLK_OUT	out std_logic
GT8_TXUSRCLK2_OUT	out std_logic
GT8_TXOUTCLK_IN	in std_logic
GT8_RXUSRCLK_OUT	out std_logic
GT8_RXUSRCLK2_OUT	out std_logic
GT8_RXOUTCLK_IN	in std_logic
GT9_TXUSRCLK_OUT	out std_logic
GT9_TXUSRCLK2_OUT	out std_logic
GT9_TXOUTCLK_IN	in std_logic
GT9_RXUSRCLK_OUT	out std_logic
GT9_RXUSRCLK2_OUT	out std_logic
GT9_RXOUTCLK_IN	in std_logic
GT10_TXUSRCLK_OUT	out std_logic
GT10_TXUSRCLK2_OUT	out std_logic
GT10_TXOUTCLK_IN	in std_logic
GT10_RXUSRCLK_OUT	out std_logic
GT10_RXUSRCLK2_OUT	out std_logic
GT10_RXOUTCLK_IN	in std_logic
GT11_TXUSRCLK_OUT	out std_logic
GT11_TXUSRCLK2_OUT	out std_logic
GT11_TXOUTCLK_IN	in std_logic
GT11_RXUSRCLK_OUT	out std_logic
GT11_RXUSRCLK2_OUT	out std_logic
GT11_RXOUTCLK_IN	in std_logic
Q0_CLK1_GTREFCLK_PAD_N_IN	in std_logic
Q0_CLK1_GTREFCLK_PAD_P_IN	in std_logic
Q0_CLK1_GTREFCLK_OUT	out std_logic
Q1_CLK1_GTREFCLK_PAD_N_IN	in std_logic
Q1_CLK1_GTREFCLK_PAD_P_IN	in std_logic
Q1_CLK1_GTREFCLK_OUT	out std_logic
Q2_CLK1_GTREFCLK_PAD_N_IN	in std_logic
Q2_CLK1_GTREFCLK_PAD_P_IN	in std_logic
Q2_CLK1_GTREFCLK_OUT	out std_logic

Member Data Documentation

GT0_RXOUTCLK_IN

GT0_RXOUTCLK_IN in std_logic

Port

GT0_RXUSRCLK2_OUT

GT0_RXUSRCLK2_OUT out std_logic

Port

GT0_RXUSRCLK_OUT

GT0_RXUSRCLK_OUT out std_logic

Port

GT0_TXOUTCLK_IN

GT0_TXOUTCLK_IN in std_logic

Port

GT0_TXUSRCLK2_OUT

GT0_TXUSRCLK2_OUT out std_logic

Port

GT0_TXUSRCLK_OUT

GT0_TXUSRCLK_OUT out std_logic

Port

GT10_RXOUTCLK_IN

GT10_RXOUTCLK_IN in std_logic

Port

GT10_RXUSRCLK2_OUT

GT10_RXUSRCLK2_OUT out std_logic

Port

GT10_RXUSRCLK_OUT

GT10_RXUSRCLK_OUT out std_logic

Port

GT10_TXOUTCLK_IN

GT10_TXOUTCLK_IN in std_logic

Port

GT10_TXUSRCLK2_OUT

GT10_TXUSRCLK2_OUT out std_logic

Port

GT10_TXUSRCLK_OUT

GT10_TXUSRCLK_OUT out std_logic

Port

GT11_RXOUTCLK_IN

GT11_RXOUTCLK_IN in std_logic

Port

GT11_RXUSRCLK2_OUT

GT11_RXUSRCLK2_OUT out std_logic

Port

GT11_RXUSRCLK_OUT

GT11_RXUSRCLK_OUT out std_logic

Port

GT11_TXOUTCLK_IN

GT11_TXOUTCLK_IN in std_logic

Port

GT11_TXUSRCLK2_OUT

GT11_TXUSRCLK2_OUT out std_logic

Port

GT11_TXUSRCLK_OUT

GT11_TXUSRCLK_OUT out std_logic

Port

GT1_RXOUTCLK_IN

GT1_RXOUTCLK_IN in std_logic

Port

GT1_RXUSRCLK2_OUT

GT1_RXUSRCLK2_OUT out std_logic

Port

GT1_RXUSRCLK_OUT

GT1_RXUSRCLK_OUT out std_logic

Port

GT1_TXOUTCLK_IN

GT1_TXOUTCLK_IN in std_logic

Port

GT1_TXUSRCLK2_OUT

GT1_TXUSRCLK2_OUT out std_logic

Port

GT1_TXUSRCLK_OUT

GT1_TXUSRCLK_OUT out std_logic

Port

GT2_RXOUTCLK_IN

GT2_RXOUTCLK_IN in std_logic

Port

GT2_RXUSRCLK2_OUT

GT2_RXUSRCLK2_OUT out std_logic

Port

GT2_RXUSRCLK_OUT

GT2_RXUSRCLK_OUT out std_logic

Port

GT2_TXOUTCLK_IN

GT2_TXOUTCLK_IN in std_logic

Port

GT2_TXUSRCLK2_OUT

GT2_TXUSRCLK2_OUT out std_logic

Port

GT2_TXUSRCLK_OUT

GT2_TXUSRCLK_OUT out std_logic

Port

GT3_RXOUTCLK_IN

GT3_RXOUTCLK_IN in std_logic

Port

GT3_RXUSRCLK2_OUT

GT3_RXUSRCLK2_OUT out std_logic

Port

GT3_RXUSRCLK_OUT

GT3_RXUSRCLK_OUT out std_logic

Port

GT3_TXOUTCLK_IN

GT3_TXOUTCLK_IN in std_logic

Port

GT3_TXUSRCLK2_OUT

GT3_TXUSRCLK2_OUT out std_logic

Port

GT3_TXUSRCLK_OUT

GT3_TXUSRCLK_OUT out std_logic

Port

GT4_RXOUTCLK_IN

GT4_RXOUTCLK_IN in std_logic

Port

GT4_RXUSRCLK2_OUT

GT4_RXUSRCLK2_OUT out std_logic

Port

GT4_RXUSRCLK_OUT

GT4_RXUSRCLK_OUT out std_logic

Port

GT4_TXOUTCLK_IN

GT4_TXOUTCLK_IN in std_logic

Port

GT4_TXUSRCLK2_OUT

GT4_TXUSRCLK2_OUT out std_logic

Port

GT4_TXUSRCLK_OUT

GT4_TXUSRCLK_OUT out std_logic

Port

GT5_RXOUTCLK_IN

GT5_RXOUTCLK_IN in std_logic

Port

GT5_RXUSRCLK2_OUT

GT5_RXUSRCLK2_OUT out std_logic

Port

GT5_RXUSRCLK_OUT

GT5_RXUSRCLK_OUT out std_logic

Port

GT5_TXOUTCLK_IN

GT5_TXOUTCLK_IN in std_logic

Port

GT5_TXUSRCLK2_OUT

GT5_TXUSRCLK2_OUT out std_logic

Port

GT5_TXUSRCLK_OUT

GT5_TXUSRCLK_OUT out std_logic

Port

GT6_RXOUTCLK_IN

GT6_RXOUTCLK_IN in std_logic

Port

GT6_RXUSRCLK2_OUT

GT6_RXUSRCLK2_OUT out std_logic

Port

GT6_RXUSRCLK_OUT

GT6_RXUSRCLK_OUT out std_logic

Port

GT6_TXOUTCLK_IN

GT6_TXOUTCLK_IN in std_logic

Port

GT6_TXUSRCLK2_OUT

GT6_TXUSRCLK2_OUT out std_logic

Port

GT6_TXUSRCLK_OUT

GT6_TXUSRCLK_OUT out std_logic

Port

GT7_RXOUTCLK_IN

GT7_RXOUTCLK_IN in std_logic

Port

GT7_RXUSRCLK2_OUT

GT7_RXUSRCLK2_OUT out std_logic

Port

GT7_RXUSRCLK_OUT

GT7_RXUSRCLK_OUT out std_logic

Port

GT7_TXOUTCLK_IN

GT7_TXOUTCLK_IN in std_logic

Port

GT7_TXUSRCLK2_OUT

GT7_TXUSRCLK2_OUT out std_logic

Port

GT7_TXUSRCLK_OUT

GT7_TXUSRCLK_OUT out std_logic

Port

GT8_RXOUTCLK_IN

GT8_RXOUTCLK_IN in std_logic

Port

GT8_RXUSRCLK2_OUT

GT8_RXUSRCLK2_OUT out std_logic

Port

GT8_RXUSRCLK_OUT

GT8_RXUSRCLK_OUT out std_logic

Port

GT8_TXOUTCLK_IN

GT8_TXOUTCLK_IN in std_logic

Port

GT8_TXUSRCLK2_OUT

GT8_TXUSRCLK2_OUT out std_logic

Port

GT8_TXUSRCLK_OUT

GT8_TXUSRCLK_OUT out std_logic

Port

GT9_RXOUTCLK_IN

GT9_RXOUTCLK_IN in std_logic

Port

GT9_RXUSRCLK2_OUT

GT9_RXUSRCLK2_OUT out std_logic

Port

GT9_RXUSRCLK_OUT

GT9_RXUSRCLK_OUT out std_logic

Port

GT9_TXOUTCLK_IN

GT9_TXOUTCLK_IN in std_logic

Port

GT9_TXUSRCLK2_OUT

GT9_TXUSRCLK2_OUT out std_logic

Port

GT9_TXUSRCLK_OUT

GT9_TXUSRCLK_OUT out std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

Q0_CLK1_GTREFCLK_OUT

Q0_CLK1_GTREFCLK_OUT out std_logic

Port

Q0_CLK1_GTREFCLK_PAD_N_IN

Q0_CLK1_GTREFCLK_PAD_N_IN in std_logic

Port

Q0_CLK1_GTREFCLK_PAD_P_IN

Q0_CLK1_GTREFCLK_PAD_P_IN in std_logic

Port

Q1_CLK1_GTREFCLK_OUT

Q1_CLK1_GTREFCLK_OUT out std_logic

Port

Q1_CLK1_GTREFCLK_PAD_N_IN

Q1_CLK1_GTREFCLK_PAD_N_IN in std_logic

Port

Q1_CLK1_GTREFCLK_PAD_P_IN

Q1_CLK1_GTREFCLK_PAD_P_IN in std_logic

Port

Q2_CLK1_GTREFCLK_OUT

Q2_CLK1_GTREFCLK_OUT out std_logic

Port

Q2_CLK1_GTREFCLK_PAD_N_IN

Q2_CLK1_GTREFCLK_PAD_N_IN in std_logic

Port

Q2_CLK1_GTREFCLK_PAD_P_IN

Q2_CLK1_GTREFCLK_PAD_P_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• FTM/DSS/mgts/dss_3quads_11g2_gt_usrclk_source.vhd