RTL Architecture Reference

Processes
PROCESS_514	( STABLE_CLOCK , SOFT_RESET )
PROCESS_515	( STABLE_CLOCK )
PROCESS_516	( STABLE_CLOCK )
PROCESS_517	( RXOUTCLK , gtrxreset_s )
retries_recclk_monitor	( STABLE_CLOCK )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( STABLE_CLOCK )
PROCESS_518	( STABLE_CLOCK )
PROCESS_519	( RXUSERCLK )
PROCESS_520	( STABLE_CLOCK )
PROCESS_521	( STABLE_CLOCK )
PROCESS_522	( STABLE_CLOCK )
timeout_buffer_bypass	( RXUSERCLK )
timeout_max	( STABLE_CLOCK )
reset_fsm	( STABLE_CLOCK )

Components
DSS_3Quads_11g2_sync_block	<Entity DSS_3Quads_11g2_sync_block>

Constants
MMCM_LOCK_CNT_MAX	integer := 256
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES + 10
WAIT_TIMEOUT_2ms	integer := 2000000 / STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_1us	integer := 1000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_100us	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIME_ADAPT	integer := ( 37000000 / integer ( 11 . 2 ) ) / STABLE_CLOCK_PERIOD
WAIT_TIME_MAX	integer := 100
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH - 1
MAX_WAIT_BYPASS	integer := 5000

Types
rx_rst_fsm_type	( INIT , ASSERT_ALL_RESETS , WAIT_FOR_PLL_LOCK , RELEASE_PLL_RESET , VERIFY_RECCLK_STABLE , RELEASE_MMCM_RESET , WAIT_FOR_RXUSRCLK , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , MONITOR_DATA_VALID , FSM_DONE )

Signals
rx_state	rx_rst_fsm_type := INIT
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
rx_fsm_reset_done_int	std_logic := ' 0 '
rx_fsm_reset_done_int_s2	std_logic := ' 0 '
rx_fsm_reset_done_int_s3	std_logic := ' 0 '
rxresetdone_s2	std_logic := ' 0 '
rxresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES := 0
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
recclk_mon_restart_count	integer range 0 to 3 := 0
recclk_mon_count_reset	std_logic := ' 0 '
reset_time_out	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
time_out_1us	std_logic := ' 0 '
time_out_100us	std_logic := ' 0 '
check_tlock_max	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_i	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic := ' 0 '
gtrxreset_i	std_logic := ' 0 '
gtrxreset_tx_i	std_logic := ' 0 '
gtrxreset_rx_i	std_logic := ' 0 '
mmcm_reset_i	std_logic := ' 1 '
rxpmaresetdone_i	std_logic := ' 0 '
txpmaresetdone_i	std_logic := ' 0 '
rxpmaresetdone_ss	std_logic := ' 0 '
rxpmaresetdone_sync	std_logic
txpmaresetdone_sync	std_logic
rxpmaresetdone_s	std_logic
rxpmaresetdone_rx_s	std_logic
pmaresetdone_fallingedge_detect	std_logic
pmaresetdone_fallingedge_detect_s	std_logic
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s2	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS - 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s2	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
refclk_lost	std_logic
time_out_adapt	std_logic := ' 0 '
adapt_count_reset	std_logic := ' 0 '
adapt_count	integer range 0 to WAIT_TIME_ADAPT - 1
data_valid_sync	std_logic := ' 0 '
cplllock_sync	std_logic := ' 0 '
qplllock_sync	std_logic := ' 0 '
cplllock_prev	std_logic := ' 0 '
qplllock_prev	std_logic := ' 0 '
cplllock_ris_edge	std_logic := ' 0 '
qplllock_ris_edge	std_logic := ' 0 '
wait_time_cnt	integer range 0 to WAIT_TIME_MAX
wait_time_done	std_logic
reset_sync_reg1_tx	std_logic
reset_sync_reg1	std_logic
gtrxreset_s	std_logic
gtrxreset_tx_s	std_logic
txpmaresetdone_s	std_logic
PHALIGNMENT_DONE_i	std_logic := ' 0 '

Attributes
shreg_extract	string
ASYNC_REG	string
KEEP	string
ASYNC_REG	reset_sync1_rx : label is " true "
ASYNC_REG	reset_sync2_rx : label is " true "
shreg_extract	reset_sync1_rx : label is " no "
shreg_extract	reset_sync2_rx : label is " no "
KEEP	PHALIGNMENT_DONE_i : signal is " true "

Instantiations
reset_sync1_rx	fdp
reset_sync2_rx	fdp
sync_pmaresetdone_fallingedge_detect	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_rxpmaresetdone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_rxpmaresetdone_rx_s	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_run_phase_alignment_int	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_rx_fsm_reset_done_int	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_rxresetdone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_time_out_wait_bypass	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_mmcm_lock_reclocked	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_data_valid	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_cplllock	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_qplllock	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>

Member Function Documentation

mmcm_lock_wait()

mmcm_lock_wait (   STABLE_CLOCK   )

Process

PROCESS_514()

PROCESS_514 (   STABLE_CLOCK ,   SOFT_RESET   )

Process

PROCESS_515()

PROCESS_515 (   STABLE_CLOCK   )

Process

PROCESS_516()

PROCESS_516 (   STABLE_CLOCK   )

Process

PROCESS_517()

PROCESS_517	(		RXOUTCLK,
			gtrxreset_s
	)

PROCESS_518()

PROCESS_518

(

STABLE_CLOCK

)

PROCESS_519()

PROCESS_519

(

RXUSERCLK

)

PROCESS_520()

PROCESS_520

(

STABLE_CLOCK

)

PROCESS_521()

PROCESS_521

(

STABLE_CLOCK

)

PROCESS_522()

PROCESS_522 (   STABLE_CLOCK   )

Process

reset_fsm()

reset_fsm (   STABLE_CLOCK   )

Process

retries_recclk_monitor()

retries_recclk_monitor

(

STABLE_CLOCK

)

timeout_buffer_bypass()

timeout_buffer_bypass (   RXUSERCLK   )

Process

timeout_max()

timeout_max (   STABLE_CLOCK   )

Process

timeouts()

timeouts (   STABLE_CLOCK   )

Process

Member Data Documentation

adapt_count

adapt_count integer range 0 to WAIT_TIME_ADAPT - 1

Signal

adapt_count_reset

adapt_count_reset std_logic := ' 0 '

Signal

ASYNC_REG [1/3]

ASYNC_REG string

Attribute

ASYNC_REG [2/3]

ASYNC_REG reset_sync1_rx : label is " true "

Attribute

ASYNC_REG [3/3]

ASYNC_REG reset_sync2_rx : label is " true "

Attribute

check_tlock_max

check_tlock_max std_logic := ' 0 '

Signal

cplllock_prev

cplllock_prev std_logic := ' 0 '

Signal

cplllock_ris_edge

cplllock_ris_edge std_logic := ' 0 '

Signal

cplllock_sync

cplllock_sync std_logic := ' 0 '

Signal

data_valid_sync

data_valid_sync std_logic := ' 0 '

Signal

DSS_3Quads_11g2_sync_block

DSS_3Quads_11g2_sync_block

Component

gtrxreset_i

gtrxreset_i std_logic := ' 0 '

Signal

gtrxreset_rx_i

gtrxreset_rx_i std_logic := ' 0 '

Signal

gtrxreset_s

gtrxreset_s std_logic

Signal

gtrxreset_tx_i

gtrxreset_tx_i std_logic := ' 0 '

Signal

gtrxreset_tx_s

gtrxreset_tx_s std_logic

Signal

init_wait_count

init_wait_count integer range 0 to WAIT_MAX := 0

Signal

init_wait_done

init_wait_done std_logic := ' 0 '

Signal

KEEP [1/2]

KEEP string

Attribute

KEEP [2/2]

KEEP PHALIGNMENT_DONE_i : signal is " true "

Attribute

MAX_RETRIES

MAX_RETRIES integer := 2 ** RETRY_COUNTER_BITWIDTH - 1

Constant

MAX_WAIT_BYPASS

MAX_WAIT_BYPASS integer := 5000

Constant

MMCM_LOCK_CNT_MAX

MMCM_LOCK_CNT_MAX integer := 256

Constant

mmcm_lock_count

mmcm_lock_count integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0

Signal

mmcm_lock_i

mmcm_lock_i std_logic := ' 0 '

Signal

mmcm_lock_int

mmcm_lock_int std_logic := ' 0 '

Signal

mmcm_lock_reclocked

mmcm_lock_reclocked std_logic := ' 0 '

Signal

mmcm_reset_i

mmcm_reset_i std_logic := ' 1 '

Signal

PHALIGNMENT_DONE_i

PHALIGNMENT_DONE_i std_logic := ' 0 '

Signal

pll_reset_asserted

pll_reset_asserted std_logic := ' 0 '

Signal

pmaresetdone_fallingedge_detect

pmaresetdone_fallingedge_detect std_logic

Signal

pmaresetdone_fallingedge_detect_s

pmaresetdone_fallingedge_detect_s std_logic

Signal

qplllock_prev

qplllock_prev std_logic := ' 0 '

Signal

qplllock_ris_edge

qplllock_ris_edge std_logic := ' 0 '

Signal

qplllock_sync

qplllock_sync std_logic := ' 0 '

Signal

recclk_mon_count_reset

recclk_mon_count_reset std_logic := ' 0 '

Signal

recclk_mon_restart_count

recclk_mon_restart_count integer range 0 to 3 := 0

Signal

refclk_lost

refclk_lost std_logic

Signal

reset_sync1_rx

reset_sync1_rx fdp

Instantiation

reset_sync2_rx

reset_sync2_rx fdp

Instantiation

reset_sync_reg1

reset_sync_reg1 std_logic

Signal

reset_sync_reg1_tx

reset_sync_reg1_tx std_logic

Signal

reset_time_out

reset_time_out std_logic := ' 0 '

Signal

retry_counter_int

retry_counter_int integer range 0 to MAX_RETRIES := 0

Signal

run_phase_alignment_int

run_phase_alignment_int std_logic := ' 0 '

Signal

run_phase_alignment_int_s2

run_phase_alignment_int_s2 std_logic := ' 0 '

Signal

run_phase_alignment_int_s3

run_phase_alignment_int_s3 std_logic := ' 0 '

Signal

rx_fsm_reset_done_int

rx_fsm_reset_done_int std_logic := ' 0 '

Signal

rx_fsm_reset_done_int_s2

rx_fsm_reset_done_int_s2 std_logic := ' 0 '

Signal

rx_fsm_reset_done_int_s3

rx_fsm_reset_done_int_s3 std_logic := ' 0 '

Signal

rx_rst_fsm_type

rx_rst_fsm_type ( INIT , ASSERT_ALL_RESETS , WAIT_FOR_PLL_LOCK , RELEASE_PLL_RESET , VERIFY_RECCLK_STABLE , RELEASE_MMCM_RESET , WAIT_FOR_RXUSRCLK , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , MONITOR_DATA_VALID , FSM_DONE )

Type

rx_state

rx_state rx_rst_fsm_type := INIT

Signal

rxpmaresetdone_i

rxpmaresetdone_i std_logic := ' 0 '

Signal

rxpmaresetdone_rx_s

rxpmaresetdone_rx_s std_logic

Signal

rxpmaresetdone_s

rxpmaresetdone_s std_logic

Signal

rxpmaresetdone_ss

rxpmaresetdone_ss std_logic := ' 0 '

Signal

rxpmaresetdone_sync

rxpmaresetdone_sync std_logic

Signal

rxresetdone_s2

rxresetdone_s2 std_logic := ' 0 '

Signal

rxresetdone_s3

rxresetdone_s3 std_logic := ' 0 '

Signal

shreg_extract [1/3]

shreg_extract string

Attribute

shreg_extract [2/3]

shreg_extract reset_sync1_rx : label is " no "

Attribute

shreg_extract [3/3]

shreg_extract reset_sync2_rx : label is " no "

Attribute

STARTUP_DELAY

STARTUP_DELAY integer := 500

Constant

sync_cplllock

sync_cplllock DSS_3Quads_11g2_sync_block

Instantiation

sync_data_valid

sync_data_valid DSS_3Quads_11g2_sync_block

Instantiation

sync_mmcm_lock_reclocked

sync_mmcm_lock_reclocked DSS_3Quads_11g2_sync_block

Instantiation

sync_pmaresetdone_fallingedge_detect

sync_pmaresetdone_fallingedge_detect DSS_3Quads_11g2_sync_block

Instantiation

sync_qplllock

sync_qplllock DSS_3Quads_11g2_sync_block

Instantiation

sync_run_phase_alignment_int

sync_run_phase_alignment_int DSS_3Quads_11g2_sync_block

Instantiation

sync_rx_fsm_reset_done_int

sync_rx_fsm_reset_done_int DSS_3Quads_11g2_sync_block

Instantiation

sync_rxpmaresetdone

sync_rxpmaresetdone DSS_3Quads_11g2_sync_block

Instantiation

sync_rxpmaresetdone_rx_s

sync_rxpmaresetdone_rx_s DSS_3Quads_11g2_sync_block

Instantiation

sync_rxresetdone

sync_rxresetdone DSS_3Quads_11g2_sync_block

Instantiation

sync_time_out_wait_bypass

sync_time_out_wait_bypass DSS_3Quads_11g2_sync_block

Instantiation

time_out_100us

time_out_100us std_logic := ' 0 '

Signal

time_out_1us

time_out_1us std_logic := ' 0 '

Signal

time_out_2ms

time_out_2ms std_logic := ' 0 '

Signal

time_out_500us

time_out_500us std_logic := ' 0 '

Signal

time_out_adapt

time_out_adapt std_logic := ' 0 '

Signal

time_out_counter

time_out_counter integer range 0 to WAIT_TIMEOUT_2ms := 0

Signal

time_out_wait_bypass

time_out_wait_bypass std_logic := ' 0 '

Signal

time_out_wait_bypass_s2

time_out_wait_bypass_s2 std_logic := ' 0 '

Signal

time_out_wait_bypass_s3

time_out_wait_bypass_s3 std_logic := ' 0 '

Signal

time_tlock_max

time_tlock_max std_logic := ' 0 '

Signal

txpmaresetdone_i

txpmaresetdone_i std_logic := ' 0 '

Signal

txpmaresetdone_s

txpmaresetdone_s std_logic

Signal

txpmaresetdone_sync

txpmaresetdone_sync std_logic

Signal

wait_bypass_count

wait_bypass_count integer range 0 to MAX_WAIT_BYPASS - 1

Signal

WAIT_CYCLES

WAIT_CYCLES integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD

Constant

WAIT_MAX

WAIT_MAX integer := WAIT_CYCLES + 10

Constant

WAIT_TIME_ADAPT

WAIT_TIME_ADAPT integer := ( 37000000 / integer ( 11 . 2 ) ) / STABLE_CLOCK_PERIOD

Constant

wait_time_cnt

wait_time_cnt integer range 0 to WAIT_TIME_MAX

Signal

wait_time_done

wait_time_done std_logic

Signal

WAIT_TIME_MAX

WAIT_TIME_MAX integer := 100

Constant

WAIT_TIMEOUT_100us

WAIT_TIMEOUT_100us integer := 100000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TIMEOUT_1us

WAIT_TIMEOUT_1us integer := 1000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TIMEOUT_2ms

WAIT_TIMEOUT_2ms integer := 2000000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TIMEOUT_500us

WAIT_TIMEOUT_500us integer := 500000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TLOCK_MAX

WAIT_TLOCK_MAX integer := 100000 / STABLE_CLOCK_PERIOD

Constant

---

The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_startup_fsm.vhd