RTL Architecture Reference

Processes
PROCESS_443	( STABLE_CLOCK )
PROCESS_444	( STABLE_CLOCK )

Constants
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES + 10

Types
rst_type	( INIT , ASSERT_COMMON_RESET )

Signals
init_wait_count	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
init_wait_done	std_logic := ' 0 '
common_reset_asserted	std_logic := ' 0 '
common_reset_i	std_logic
state	rst_type := INIT

Member Function Documentation

PROCESS_443()

PROCESS_443 (   STABLE_CLOCK   )

Process

PROCESS_444()

PROCESS_444 (   STABLE_CLOCK   )

Process

Member Data Documentation

common_reset_asserted

common_reset_asserted std_logic := ' 0 '

Signal

common_reset_i

common_reset_i std_logic

Signal

init_wait_count

init_wait_count std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

init_wait_done

init_wait_done std_logic := ' 0 '

Signal

rst_type

rst_type ( INIT , ASSERT_COMMON_RESET )

Type

STARTUP_DELAY

STARTUP_DELAY integer := 500

Constant

state

state rst_type := INIT

Signal

WAIT_CYCLES

WAIT_CYCLES integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD

Constant

WAIT_MAX

WAIT_MAX integer := WAIT_CYCLES + 10

Constant

---

The documentation for this class was generated from the following file:

• FTM/DSS/mgts/dss_3quads_11g2_common_reset.vhd