RTL Architecture Reference

Collaboration diagram for RTL:

Components
DSS_3Quads_11g2_GT	<Entity DSS_3Quads_11g2_GT>

Constants
DLY	time := 1 ns

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
gt0_qplloutclk_i	std_logic
gt0_qplloutrefclk_i	std_logic
gt1_qplloutclk_i	std_logic
gt1_qplloutrefclk_i	std_logic
gt2_qplloutclk_i	std_logic
gt2_qplloutrefclk_i	std_logic
gt0_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt0_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt1_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt1_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt2_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt2_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt3_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt3_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt4_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt4_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt5_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt5_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt6_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt6_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt7_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt7_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt8_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt8_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt9_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt9_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt10_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt10_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt11_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt11_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt0_qpllclk_i	std_logic
gt0_qpllrefclk_i	std_logic
gt1_qpllclk_i	std_logic
gt1_qpllrefclk_i	std_logic
gt2_qpllclk_i	std_logic
gt2_qpllrefclk_i	std_logic
gt3_qpllclk_i	std_logic
gt3_qpllrefclk_i	std_logic
gt4_qpllclk_i	std_logic
gt4_qpllrefclk_i	std_logic
gt5_qpllclk_i	std_logic
gt5_qpllrefclk_i	std_logic
gt6_qpllclk_i	std_logic
gt6_qpllrefclk_i	std_logic
gt7_qpllclk_i	std_logic
gt7_qpllrefclk_i	std_logic
gt8_qpllclk_i	std_logic
gt8_qpllrefclk_i	std_logic
gt9_qpllclk_i	std_logic
gt9_qpllrefclk_i	std_logic
gt10_qpllclk_i	std_logic
gt10_qpllrefclk_i	std_logic
gt11_qpllclk_i	std_logic
gt11_qpllrefclk_i	std_logic
gt0_cpllreset_i	std_logic
gt0_cpllpd_i	std_logic
gt1_cpllreset_i	std_logic
gt1_cpllpd_i	std_logic
gt2_cpllreset_i	std_logic
gt2_cpllpd_i	std_logic
gt3_cpllreset_i	std_logic
gt3_cpllpd_i	std_logic
gt4_cpllreset_i	std_logic
gt4_cpllpd_i	std_logic
gt5_cpllreset_i	std_logic
gt5_cpllpd_i	std_logic
gt6_cpllreset_i	std_logic
gt6_cpllpd_i	std_logic
gt7_cpllreset_i	std_logic
gt7_cpllpd_i	std_logic
gt8_cpllreset_i	std_logic
gt8_cpllpd_i	std_logic
gt9_cpllreset_i	std_logic
gt9_cpllpd_i	std_logic
gt10_cpllreset_i	std_logic
gt10_cpllpd_i	std_logic
gt11_cpllreset_i	std_logic
gt11_cpllpd_i	std_logic

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	RTL : architecture is " yes "
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	RTL : architecture is " DSS_3Quads_11g2_multi_gt , gtwizard_v3_6_11 , {protocol_file = Start_from_scratch} "

Instantiations
gt0_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt1_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt2_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt3_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt4_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt5_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt6_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt7_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt8_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt9_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt10_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>
gt11_dss_3quads_11g2_i	DSS_3Quads_11g2_GT <Entity DSS_3Quads_11g2_GT>

Member Data Documentation

CORE_GENERATION_INFO [1/2]

CORE_GENERATION_INFO string

Attribute

CORE_GENERATION_INFO [2/2]

CORE_GENERATION_INFO RTL : architecture is " DSS_3Quads_11g2_multi_gt , gtwizard_v3_6_11 , {protocol_file = Start_from_scratch} "

Attribute

DLY

DLY time := 1 ns

Constant

DowngradeIPIdentifiedWarnings [1/2]

DowngradeIPIdentifiedWarnings string

Attribute

DowngradeIPIdentifiedWarnings [2/2]

DowngradeIPIdentifiedWarnings RTL : architecture is " yes "

Attribute

DSS_3Quads_11g2_GT

DSS_3Quads_11g2_GT

Component

gt0_cpllpd_i

gt0_cpllpd_i std_logic

Signal

gt0_cpllreset_i

gt0_cpllreset_i std_logic

Signal

gt0_dss_3quads_11g2_i

gt0_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt0_mgtrefclkrx_i

gt0_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt0_mgtrefclktx_i

gt0_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt0_qpllclk_i

gt0_qpllclk_i std_logic

Signal

gt0_qplloutclk_i

gt0_qplloutclk_i std_logic

Signal

gt0_qplloutrefclk_i

gt0_qplloutrefclk_i std_logic

Signal

gt0_qpllrefclk_i

gt0_qpllrefclk_i std_logic

Signal

gt10_cpllpd_i

gt10_cpllpd_i std_logic

Signal

gt10_cpllreset_i

gt10_cpllreset_i std_logic

Signal

gt10_dss_3quads_11g2_i

gt10_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt10_mgtrefclkrx_i

gt10_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt10_mgtrefclktx_i

gt10_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt10_qpllclk_i

gt10_qpllclk_i std_logic

Signal

gt10_qpllrefclk_i

gt10_qpllrefclk_i std_logic

Signal

gt11_cpllpd_i

gt11_cpllpd_i std_logic

Signal

gt11_cpllreset_i

gt11_cpllreset_i std_logic

Signal

gt11_dss_3quads_11g2_i

gt11_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt11_mgtrefclkrx_i

gt11_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt11_mgtrefclktx_i

gt11_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt11_qpllclk_i

gt11_qpllclk_i std_logic

Signal

gt11_qpllrefclk_i

gt11_qpllrefclk_i std_logic

Signal

gt1_cpllpd_i

gt1_cpllpd_i std_logic

Signal

gt1_cpllreset_i

gt1_cpllreset_i std_logic

Signal

gt1_dss_3quads_11g2_i

gt1_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt1_mgtrefclkrx_i

gt1_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt1_mgtrefclktx_i

gt1_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt1_qpllclk_i

gt1_qpllclk_i std_logic

Signal

gt1_qplloutclk_i

gt1_qplloutclk_i std_logic

Signal

gt1_qplloutrefclk_i

gt1_qplloutrefclk_i std_logic

Signal

gt1_qpllrefclk_i

gt1_qpllrefclk_i std_logic

Signal

gt2_cpllpd_i

gt2_cpllpd_i std_logic

Signal

gt2_cpllreset_i

gt2_cpllreset_i std_logic

Signal

gt2_dss_3quads_11g2_i

gt2_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt2_mgtrefclkrx_i

gt2_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt2_mgtrefclktx_i

gt2_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt2_qpllclk_i

gt2_qpllclk_i std_logic

Signal

gt2_qplloutclk_i

gt2_qplloutclk_i std_logic

Signal

gt2_qplloutrefclk_i

gt2_qplloutrefclk_i std_logic

Signal

gt2_qpllrefclk_i

gt2_qpllrefclk_i std_logic

Signal

gt3_cpllpd_i

gt3_cpllpd_i std_logic

Signal

gt3_cpllreset_i

gt3_cpllreset_i std_logic

Signal

gt3_dss_3quads_11g2_i

gt3_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt3_mgtrefclkrx_i

gt3_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt3_mgtrefclktx_i

gt3_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt3_qpllclk_i

gt3_qpllclk_i std_logic

Signal

gt3_qpllrefclk_i

gt3_qpllrefclk_i std_logic

Signal

gt4_cpllpd_i

gt4_cpllpd_i std_logic

Signal

gt4_cpllreset_i

gt4_cpllreset_i std_logic

Signal

gt4_dss_3quads_11g2_i

gt4_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt4_mgtrefclkrx_i

gt4_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt4_mgtrefclktx_i

gt4_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt4_qpllclk_i

gt4_qpllclk_i std_logic

Signal

gt4_qpllrefclk_i

gt4_qpllrefclk_i std_logic

Signal

gt5_cpllpd_i

gt5_cpllpd_i std_logic

Signal

gt5_cpllreset_i

gt5_cpllreset_i std_logic

Signal

gt5_dss_3quads_11g2_i

gt5_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt5_mgtrefclkrx_i

gt5_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt5_mgtrefclktx_i

gt5_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt5_qpllclk_i

gt5_qpllclk_i std_logic

Signal

gt5_qpllrefclk_i

gt5_qpllrefclk_i std_logic

Signal

gt6_cpllpd_i

gt6_cpllpd_i std_logic

Signal

gt6_cpllreset_i

gt6_cpllreset_i std_logic

Signal

gt6_dss_3quads_11g2_i

gt6_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt6_mgtrefclkrx_i

gt6_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt6_mgtrefclktx_i

gt6_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt6_qpllclk_i

gt6_qpllclk_i std_logic

Signal

gt6_qpllrefclk_i

gt6_qpllrefclk_i std_logic

Signal

gt7_cpllpd_i

gt7_cpllpd_i std_logic

Signal

gt7_cpllreset_i

gt7_cpllreset_i std_logic

Signal

gt7_dss_3quads_11g2_i

gt7_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt7_mgtrefclkrx_i

gt7_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt7_mgtrefclktx_i

gt7_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt7_qpllclk_i

gt7_qpllclk_i std_logic

Signal

gt7_qpllrefclk_i

gt7_qpllrefclk_i std_logic

Signal

gt8_cpllpd_i

gt8_cpllpd_i std_logic

Signal

gt8_cpllreset_i

gt8_cpllreset_i std_logic

Signal

gt8_dss_3quads_11g2_i

gt8_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt8_mgtrefclkrx_i

gt8_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt8_mgtrefclktx_i

gt8_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt8_qpllclk_i

gt8_qpllclk_i std_logic

Signal

gt8_qpllrefclk_i

gt8_qpllrefclk_i std_logic

Signal

gt9_cpllpd_i

gt9_cpllpd_i std_logic

Signal

gt9_cpllreset_i

gt9_cpllreset_i std_logic

Signal

gt9_dss_3quads_11g2_i

gt9_dss_3quads_11g2_i DSS_3Quads_11g2_GT

Instantiation

gt9_mgtrefclkrx_i

gt9_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt9_mgtrefclktx_i

gt9_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt9_qpllclk_i

gt9_qpllclk_i std_logic

Signal

gt9_qpllrefclk_i

gt9_qpllrefclk_i std_logic

Signal

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_ground_vec_i

tied_to_ground_vec_i std_logic_vector ( 63 downto 0 )

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

---

The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/dss_3quads_11g2_multi_gt.vhd