DSS_3quads_11g2_mgts Entity Reference

Inheritance diagram for DSS_3quads_11g2_mgts:

Collaboration diagram for DSS_3quads_11g2_mgts:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS
ftm	Package <ftm>

Generics
EXAMPLE_CONFIG_INDEPENDENT_LANES	integer := 1
EXAMPLE_LANE_WITH_START_CHAR	integer := 0
EXAMPLE_WORDS_IN_BRAM	integer := 512
EXAMPLE_SIM_GTRESET_SPEEDUP	string := " TRUE "
STABLE_CLOCK_PERIOD	integer := 8
EXAMPLE_USE_CHIPSCOPE	integer := 0
Q2_REFCLK1_Q1	boolean := FALSE

Ports
Q0_CLK1_GTREFCLK_PAD_N_IN	in std_logic
Q0_CLK1_GTREFCLK_PAD_P_IN	in std_logic
Q1_CLK1_GTREFCLK_PAD_N_IN	in std_logic
Q1_CLK1_GTREFCLK_PAD_P_IN	in std_logic
Q2_CLK1_GTREFCLK_PAD_N_IN	in std_logic
Q2_CLK1_GTREFCLK_PAD_P_IN	in std_logic
DRP_CLK_IN	in std_logic
RXN_IN	in std_logic_vector ( 11 downto 0 )
RXP_IN	in std_logic_vector ( 11 downto 0 )
mgt_source_data	in mgt_data_array ( 11 downto 0 )
mgt_source_clk2	out std_logic_vector ( 11 downto 0 )
mgt_sink_data	out mgt_data_array ( 11 downto 0 )
mgt_sink_clk2	out std_logic_vector ( 11 downto 0 )
mgt_control	in mgt_control
mgt_status	out mgt_status
v1_txpolarity_fix	in std_logic := ' 0 '
TXN_OUT	out std_logic_vector ( 11 downto 0 )
TXP_OUT	out std_logic_vector ( 11 downto 0 )
bc_clk_in	in std_logic := ' 0 '

Member Data Documentation

bc_clk_in

bc_clk_in in std_logic := ' 0 '

Port

DRP_CLK_IN

DRP_CLK_IN in std_logic

Port

EXAMPLE_CONFIG_INDEPENDENT_LANES

EXAMPLE_CONFIG_INDEPENDENT_LANES integer := 1

Generic

EXAMPLE_LANE_WITH_START_CHAR

EXAMPLE_LANE_WITH_START_CHAR integer := 0

Generic

EXAMPLE_SIM_GTRESET_SPEEDUP

EXAMPLE_SIM_GTRESET_SPEEDUP string := " TRUE "

Generic

EXAMPLE_USE_CHIPSCOPE

EXAMPLE_USE_CHIPSCOPE integer := 0

Generic

EXAMPLE_WORDS_IN_BRAM

EXAMPLE_WORDS_IN_BRAM integer := 512

Generic

ftm

ftm

Package

ieee

ieee

Library

mgt_control

mgt_control in mgt_control

Port

mgt_sink_clk2

mgt_sink_clk2 out std_logic_vector ( 11 downto 0 )

Port

mgt_sink_data

mgt_sink_data out mgt_data_array ( 11 downto 0 )

Port

mgt_source_clk2

mgt_source_clk2 out std_logic_vector ( 11 downto 0 )

Port

mgt_source_data

mgt_source_data in mgt_data_array ( 11 downto 0 )

Port

mgt_status

mgt_status out mgt_status

Port

numeric_std

numeric_std

Package

Q0_CLK1_GTREFCLK_PAD_N_IN

Q0_CLK1_GTREFCLK_PAD_N_IN in std_logic

Port

Q0_CLK1_GTREFCLK_PAD_P_IN

Q0_CLK1_GTREFCLK_PAD_P_IN in std_logic

Port

Q1_CLK1_GTREFCLK_PAD_N_IN

Q1_CLK1_GTREFCLK_PAD_N_IN in std_logic

Port

Q1_CLK1_GTREFCLK_PAD_P_IN

Q1_CLK1_GTREFCLK_PAD_P_IN in std_logic

Port

Q2_CLK1_GTREFCLK_PAD_N_IN

Q2_CLK1_GTREFCLK_PAD_N_IN in std_logic

Port

Q2_CLK1_GTREFCLK_PAD_P_IN

Q2_CLK1_GTREFCLK_PAD_P_IN in std_logic

Port

Q2_REFCLK1_Q1

Q2_REFCLK1_Q1 boolean := FALSE

Generic

RXN_IN

RXN_IN in std_logic_vector ( 11 downto 0 )

Port

RXP_IN

RXP_IN in std_logic_vector ( 11 downto 0 )

Port

STABLE_CLOCK_PERIOD

STABLE_CLOCK_PERIOD integer := 8

Generic

std_logic_1164

std_logic_1164

Package

TXN_OUT

TXN_OUT out std_logic_vector ( 11 downto 0 )

Port

TXP_OUT

TXP_OUT out std_logic_vector ( 11 downto 0 )

Port

UNISIM

UNISIM

Library

v1_txpolarity_fix

v1_txpolarity_fix in std_logic := ' 0 '

Port

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• FTM/DSS/mgts/dss_3quads_11g2_mgts.vhd