FLASH_SPI Entity Reference

Inheritance diagram for FLASH_SPI:

Entities
Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_unsigned

Ports
CPLD_CLK	in std_logic
CONTROL_CSn	in std_logic
CONTROL_ENAB	in std_logic
CONTROL_MOSI	in std_logic
CONTROL_MISO	out std_logic
CONTROL_CLK	in std_logic
CONTROL_ADR	in std_logic_vector ( 1 downto 0 )
CABLE_PRESENT_n	in std_logic
CABLE_CLK	in std_logic
CABLE_MOSI	in std_logic
CABLE_MISO	out std_logic := ' Z '
CABLE_CSn	in std_logic
CABLE_ADR	in std_logic_vector ( 3 downto 0 )
C_DONE	in std_logic
RPI_CE1N	in std_logic
RPI_GPIO6	in std_logic
RPI_MISO	out std_logic := ' Z '
RPI_GPIO5	in std_logic
RPI_ON	in std_logic
CFLASH_SELn	out std_logic
D1FLASH_SELn	out std_logic
D2FLASH_SELn	out std_logic
FLASH_SPI_CLK	out std_logic
FLASH_SPI_MOSI	out std_logic
FLASH_SPI_MISO	in std_logic
FLASH_SPI_CSn	out std_logic

Member Data Documentation

C_DONE

C_DONE in std_logic

Port

CABLE_ADR

CABLE_ADR in std_logic_vector ( 3 downto 0 )

Port

CABLE_CLK

CABLE_CLK in std_logic

Port

CABLE_CSn

CABLE_CSn in std_logic

Port

CABLE_MISO

CABLE_MISO out std_logic := ' Z '

Port

CABLE_MOSI

CABLE_MOSI in std_logic

Port

CABLE_PRESENT_n

CABLE_PRESENT_n in std_logic

Port

CFLASH_SELn

CFLASH_SELn out std_logic

Port

CONTROL_ADR

CONTROL_ADR in std_logic_vector ( 1 downto 0 )

Port

CONTROL_CLK

CONTROL_CLK in std_logic

Port

CONTROL_CSn

CONTROL_CSn in std_logic

Port

CONTROL_ENAB

CONTROL_ENAB in std_logic

Port

CONTROL_MISO

CONTROL_MISO out std_logic

Port

CONTROL_MOSI

CONTROL_MOSI in std_logic

Port

CPLD_CLK

CPLD_CLK in std_logic

Port

D1FLASH_SELn

D1FLASH_SELn out std_logic

Port

D2FLASH_SELn

D2FLASH_SELn out std_logic

Port

FLASH_SPI_CLK

FLASH_SPI_CLK out std_logic

Port

FLASH_SPI_CSn

FLASH_SPI_CSn out std_logic

Port

FLASH_SPI_MISO

FLASH_SPI_MISO in std_logic

Port

FLASH_SPI_MOSI

FLASH_SPI_MOSI out std_logic

Port

IEEE

IEEE

Library

RPI_CE1N

RPI_CE1N in std_logic

Port

RPI_GPIO5

RPI_GPIO5 in std_logic

Port

RPI_GPIO6

RPI_GPIO6 in std_logic

Port

RPI_MISO

RPI_MISO out std_logic := ' Z '

Port

RPI_ON

RPI_ON in std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

---

The documentation for this class was generated from the following file:

• FTM/CPLDs/FLASH_SPI/FLASH_SPI.vhd