GTX_dual_1000X Entity Reference

Inheritance diagram for GTX_dual_1000X:

Collaboration diagram for GTX_dual_1000X:

Entities
structural	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
Vcomponents

Ports
RESETDONE_0	out std_logic
ENMCOMMAALIGN_0	in std_logic
ENPCOMMAALIGN_0	in std_logic
LOOPBACK_0	in std_logic
POWERDOWN_0	in std_logic
RXUSRCLK_0	in std_logic
RXUSRCLK2_0	in std_logic
RXRESET_0	in std_logic
TXCHARDISPMODE_0	in std_logic
TXCHARDISPVAL_0	in std_logic
TXCHARISK_0	in std_logic
TXDATA_0	in std_logic_vector ( 7 downto 0 )
TXUSRCLK_0	in std_logic
TXUSRCLK2_0	in std_logic
TXRESET_0	in std_logic
RXCHARISCOMMA_0	out std_logic
RXCHARISK_0	out std_logic
RXCLKCORCNT_0	out std_logic_vector ( 2 downto 0 )
RXDATA_0	out std_logic_vector ( 7 downto 0 )
RXDISPERR_0	out std_logic
RXNOTINTABLE_0	out std_logic
RXRUNDISP_0	out std_logic
RXBUFERR_0	out std_logic
TXBUFERR_0	out std_logic
PLLLKDET_0	out std_logic
TXOUTCLK_0	out std_logic
RXELECIDLE_0	out std_logic
TX1N_0	out std_logic
TX1P_0	out std_logic
RX1N_0	in std_logic
RX1P_0	in std_logic
TX1N_1_UNUSED	out std_logic
TX1P_1_UNUSED	out std_logic
RX1N_1_UNUSED	in std_logic
RX1P_1_UNUSED	in std_logic
CLK_DS	in std_logic
REFCLKOUT	out std_logic
GTRESET	in std_logic
PMARESET	in std_logic
DCM_LOCKED	in std_logic
rxpolarity	in std_logic_vector ( 1 downto 0 )
txpolarity	in std_logic_vector ( 1 downto 0 )

Member Data Documentation

CLK_DS

CLK_DS in std_logic

Port

DCM_LOCKED

DCM_LOCKED in std_logic

Port

ENMCOMMAALIGN_0

ENMCOMMAALIGN_0 in std_logic

Port

ENPCOMMAALIGN_0

ENPCOMMAALIGN_0 in std_logic

Port

GTRESET

GTRESET in std_logic

Port

ieee

ieee

Library

LOOPBACK_0

LOOPBACK_0 in std_logic

Port

numeric_std

numeric_std

Package

PLLLKDET_0

PLLLKDET_0 out std_logic

Port

PMARESET

PMARESET in std_logic

Port

POWERDOWN_0

POWERDOWN_0 in std_logic

Port

REFCLKOUT

REFCLKOUT out std_logic

Port

RESETDONE_0

RESETDONE_0 out std_logic

Port

RX1N_0

RX1N_0 in std_logic

Port

RX1N_1_UNUSED

RX1N_1_UNUSED in std_logic

Port

RX1P_0

RX1P_0 in std_logic

Port

RX1P_1_UNUSED

RX1P_1_UNUSED in std_logic

Port

RXBUFERR_0

RXBUFERR_0 out std_logic

Port

RXCHARISCOMMA_0

RXCHARISCOMMA_0 out std_logic

Port

RXCHARISK_0

RXCHARISK_0 out std_logic

Port

RXCLKCORCNT_0

RXCLKCORCNT_0 out std_logic_vector ( 2 downto 0 )

Port

RXDATA_0

RXDATA_0 out std_logic_vector ( 7 downto 0 )

Port

RXDISPERR_0

RXDISPERR_0 out std_logic

Port

RXELECIDLE_0

RXELECIDLE_0 out std_logic

Port

RXNOTINTABLE_0

RXNOTINTABLE_0 out std_logic

Port

rxpolarity

rxpolarity in std_logic_vector ( 1 downto 0 )

Port

RXRESET_0

RXRESET_0 in std_logic

Port

RXRUNDISP_0

RXRUNDISP_0 out std_logic

Port

RXUSRCLK2_0

RXUSRCLK2_0 in std_logic

Port

RXUSRCLK_0

RXUSRCLK_0 in std_logic

Port

std_logic_1164

std_logic_1164

Package

TX1N_0

TX1N_0 out std_logic

Port

TX1N_1_UNUSED

TX1N_1_UNUSED out std_logic

Port

TX1P_0

TX1P_0 out std_logic

Port

TX1P_1_UNUSED

TX1P_1_UNUSED out std_logic

Port

TXBUFERR_0

TXBUFERR_0 out std_logic

Port

TXCHARDISPMODE_0

TXCHARDISPMODE_0 in std_logic

Port

TXCHARDISPVAL_0

TXCHARDISPVAL_0 in std_logic

Port

TXCHARISK_0

TXCHARISK_0 in std_logic

Port

TXDATA_0

TXDATA_0 in std_logic_vector ( 7 downto 0 )

Port

TXOUTCLK_0

TXOUTCLK_0 out std_logic

Port

txpolarity

txpolarity in std_logic_vector ( 1 downto 0 )

Port

TXRESET_0

TXRESET_0 in std_logic

Port

TXUSRCLK2_0

TXUSRCLK2_0 in std_logic

Port

TXUSRCLK_0

TXUSRCLK_0 in std_logic

Port

UNISIM

UNISIM

Library

Vcomponents

Vcomponents

Package

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The documentation for this class was generated from the following files:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/gtx_dual_1000X.vhd
• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/gtx_dual_1000X_ch1.vhd