PLL_SPI Entity Reference

Inheritance diagram for PLL_SPI:

Entities
Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_unsigned

Ports
CPLD_CLK	in std_logic
CONTROL_CSn	in std_logic
CONTROL_ENAB	in std_logic
CONTROL_MOSI	in std_logic
CONTROL_MISO	out std_logic
CONTROL_CLK	in std_logic
CONTROL_ADR	in std_logic_vector ( 1 downto 0 )
CABLE_PRESENT_n	in std_logic
CABLE_CLK	in std_logic
CABLE_MOSI	in std_logic
CABLE_MISO	out std_logic := ' Z '
CABLE_CSn	in std_logic
CABLE_ADR	in std_logic_vector ( 3 downto 0 )
PLL_SPI_CLK	out std_logic
PLL_SPI_MOSI	out std_logic
PLL_SPI_MISO	in std_logic
PLL_SPI_LE	out std_logic_vector ( 3 downto 0 )

Member Data Documentation

CABLE_ADR

CABLE_ADR in std_logic_vector ( 3 downto 0 )

Port

CABLE_CLK

CABLE_CLK in std_logic

Port

CABLE_CSn

CABLE_CSn in std_logic

Port

CABLE_MISO

CABLE_MISO out std_logic := ' Z '

Port

CABLE_MOSI

CABLE_MOSI in std_logic

Port

CABLE_PRESENT_n

CABLE_PRESENT_n in std_logic

Port

CONTROL_ADR

CONTROL_ADR in std_logic_vector ( 1 downto 0 )

Port

CONTROL_CLK

CONTROL_CLK in std_logic

Port

CONTROL_CSn

CONTROL_CSn in std_logic

Port

CONTROL_ENAB

CONTROL_ENAB in std_logic

Port

CONTROL_MISO

CONTROL_MISO out std_logic

Port

CONTROL_MOSI

CONTROL_MOSI in std_logic

Port

CPLD_CLK

CPLD_CLK in std_logic

Port

IEEE

IEEE

Library

PLL_SPI_CLK

PLL_SPI_CLK out std_logic

Port

PLL_SPI_LE

PLL_SPI_LE out std_logic_vector ( 3 downto 0 )

Port

PLL_SPI_MISO

PLL_SPI_MISO in std_logic

Port

PLL_SPI_MOSI

PLL_SPI_MOSI out std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

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The documentation for this class was generated from the following file:

• FTM/CPLDs/PLL_SPI/PLL_SPI.vhd