ROCKETIO_WRAPPER_GTX Entity Reference

Inheritance diagram for ROCKETIO_WRAPPER_GTX:

Collaboration diagram for ROCKETIO_WRAPPER_GTX:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
WRAPPER_SIM_GTXRESET_SPEEDUP	integer := 0
WRAPPER_SIM_PLL_PERDIV2	bit_vector := x " 0c8 "

Ports
TILE0_LOOPBACK0_IN	in std_logic_vector ( 2 downto 0 )
TILE0_LOOPBACK1_IN	in std_logic_vector ( 2 downto 0 )
TILE0_RXPOWERDOWN0_IN	in std_logic_vector ( 1 downto 0 )
TILE0_TXPOWERDOWN0_IN	in std_logic_vector ( 1 downto 0 )
TILE0_RXPOWERDOWN1_IN	in std_logic_vector ( 1 downto 0 )
TILE0_TXPOWERDOWN1_IN	in std_logic_vector ( 1 downto 0 )
TILE0_RXCHARISCOMMA0_OUT	out std_logic
TILE0_RXCHARISK0_OUT	out std_logic
TILE0_RXDISPERR0_OUT	out std_logic
TILE0_RXNOTINTABLE0_OUT	out std_logic
TILE0_RXRUNDISP0_OUT	out std_logic
TILE0_RXCHARISCOMMA1_OUT	out std_logic
TILE0_RXCHARISK1_OUT	out std_logic
TILE0_RXDISPERR1_OUT	out std_logic
TILE0_RXNOTINTABLE1_OUT	out std_logic
TILE0_RXRUNDISP1_OUT	out std_logic
TILE0_RXCLKCORCNT0_OUT	out std_logic_vector ( 2 downto 0 )
TILE0_RXCLKCORCNT1_OUT	out std_logic_vector ( 2 downto 0 )
TILE0_RXENMCOMMAALIGN0_IN	in std_logic
TILE0_RXENMCOMMAALIGN1_IN	in std_logic
TILE0_RXENPCOMMAALIGN0_IN	in std_logic
TILE0_RXENPCOMMAALIGN1_IN	in std_logic
TILE0_RXDATA0_OUT	out std_logic_vector ( 7 downto 0 )
TILE0_RXDATA1_OUT	out std_logic_vector ( 7 downto 0 )
TILE0_RXRECCLK0_OUT	out std_logic
TILE0_RXRECCLK1_OUT	out std_logic
TILE0_RXRESET0_IN	in std_logic
TILE0_RXRESET1_IN	in std_logic
TILE0_RXUSRCLK0_IN	in std_logic
TILE0_RXUSRCLK1_IN	in std_logic
TILE0_RXUSRCLK20_IN	in std_logic
TILE0_RXUSRCLK21_IN	in std_logic
TILE0_RXELECIDLE0_OUT	out std_logic
TILE0_RXELECIDLE1_OUT	out std_logic
TILE0_RXN0_IN	in std_logic
TILE0_RXN1_IN	in std_logic
TILE0_RXP0_IN	in std_logic
TILE0_RXP1_IN	in std_logic
TILE0_RXBUFRESET0_IN	in std_logic
TILE0_RXBUFRESET1_IN	in std_logic
TILE0_RXBUFSTATUS0_OUT	out std_logic_vector ( 2 downto 0 )
TILE0_RXBUFSTATUS1_OUT	out std_logic_vector ( 2 downto 0 )
TILE0_CLKIN_IN	in std_logic
TILE0_GTXRESET_IN	in std_logic
TILE0_PLLLKDET_OUT	out std_logic
TILE0_REFCLKOUT_OUT	out std_logic
TILE0_RESETDONE0_OUT	out std_logic
TILE0_RESETDONE1_OUT	out std_logic
TILE0_TXCHARDISPMODE0_IN	in std_logic
TILE0_TXCHARDISPMODE1_IN	in std_logic
TILE0_TXCHARDISPVAL0_IN	in std_logic
TILE0_TXCHARDISPVAL1_IN	in std_logic
TILE0_TXCHARISK0_IN	in std_logic
TILE0_TXCHARISK1_IN	in std_logic
TILE0_TXBUFSTATUS0_OUT	out std_logic_vector ( 1 downto 0 )
TILE0_TXBUFSTATUS1_OUT	out std_logic_vector ( 1 downto 0 )
TILE0_TXDATA0_IN	in std_logic_vector ( 7 downto 0 )
TILE0_TXDATA1_IN	in std_logic_vector ( 7 downto 0 )
TILE0_TXOUTCLK0_OUT	out std_logic
TILE0_TXOUTCLK1_OUT	out std_logic
TILE0_TXRESET0_IN	in std_logic
TILE0_TXRESET1_IN	in std_logic
TILE0_TXUSRCLK0_IN	in std_logic
TILE0_TXUSRCLK1_IN	in std_logic
TILE0_TXUSRCLK20_IN	in std_logic
TILE0_TXUSRCLK21_IN	in std_logic
TILE0_TXN0_OUT	out std_logic
TILE0_TXN1_OUT	out std_logic
TILE0_TXP0_OUT	out std_logic
TILE0_TXP1_OUT	out std_logic
rxpolarity	in std_logic_vector ( 1 downto 0 )
txpolarity	in std_logic_vector ( 1 downto 0 )

Member Data Documentation

ieee

ieee

Library

numeric_std

numeric_std

Package

rxpolarity

rxpolarity in std_logic_vector ( 1 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

TILE0_CLKIN_IN

TILE0_CLKIN_IN in std_logic

Port

TILE0_GTXRESET_IN

TILE0_GTXRESET_IN in std_logic

Port

TILE0_LOOPBACK0_IN

TILE0_LOOPBACK0_IN in std_logic_vector ( 2 downto 0 )

Port

TILE0_LOOPBACK1_IN

TILE0_LOOPBACK1_IN in std_logic_vector ( 2 downto 0 )

Port

TILE0_PLLLKDET_OUT

TILE0_PLLLKDET_OUT out std_logic

Port

TILE0_REFCLKOUT_OUT

TILE0_REFCLKOUT_OUT out std_logic

Port

TILE0_RESETDONE0_OUT

TILE0_RESETDONE0_OUT out std_logic

Port

TILE0_RESETDONE1_OUT

TILE0_RESETDONE1_OUT out std_logic

Port

TILE0_RXBUFRESET0_IN

TILE0_RXBUFRESET0_IN in std_logic

Port

TILE0_RXBUFRESET1_IN

TILE0_RXBUFRESET1_IN in std_logic

Port

TILE0_RXBUFSTATUS0_OUT

TILE0_RXBUFSTATUS0_OUT out std_logic_vector ( 2 downto 0 )

Port

TILE0_RXBUFSTATUS1_OUT

TILE0_RXBUFSTATUS1_OUT out std_logic_vector ( 2 downto 0 )

Port

TILE0_RXCHARISCOMMA0_OUT

TILE0_RXCHARISCOMMA0_OUT out std_logic

Port

TILE0_RXCHARISCOMMA1_OUT

TILE0_RXCHARISCOMMA1_OUT out std_logic

Port

TILE0_RXCHARISK0_OUT

TILE0_RXCHARISK0_OUT out std_logic

Port

TILE0_RXCHARISK1_OUT

TILE0_RXCHARISK1_OUT out std_logic

Port

TILE0_RXCLKCORCNT0_OUT

TILE0_RXCLKCORCNT0_OUT out std_logic_vector ( 2 downto 0 )

Port

TILE0_RXCLKCORCNT1_OUT

TILE0_RXCLKCORCNT1_OUT out std_logic_vector ( 2 downto 0 )

Port

TILE0_RXDATA0_OUT

TILE0_RXDATA0_OUT out std_logic_vector ( 7 downto 0 )

Port

TILE0_RXDATA1_OUT

TILE0_RXDATA1_OUT out std_logic_vector ( 7 downto 0 )

Port

TILE0_RXDISPERR0_OUT

TILE0_RXDISPERR0_OUT out std_logic

Port

TILE0_RXDISPERR1_OUT

TILE0_RXDISPERR1_OUT out std_logic

Port

TILE0_RXELECIDLE0_OUT

TILE0_RXELECIDLE0_OUT out std_logic

Port

TILE0_RXELECIDLE1_OUT

TILE0_RXELECIDLE1_OUT out std_logic

Port

TILE0_RXENMCOMMAALIGN0_IN

TILE0_RXENMCOMMAALIGN0_IN in std_logic

Port

TILE0_RXENMCOMMAALIGN1_IN

TILE0_RXENMCOMMAALIGN1_IN in std_logic

Port

TILE0_RXENPCOMMAALIGN0_IN

TILE0_RXENPCOMMAALIGN0_IN in std_logic

Port

TILE0_RXENPCOMMAALIGN1_IN

TILE0_RXENPCOMMAALIGN1_IN in std_logic

Port

TILE0_RXN0_IN

TILE0_RXN0_IN in std_logic

Port

TILE0_RXN1_IN

TILE0_RXN1_IN in std_logic

Port

TILE0_RXNOTINTABLE0_OUT

TILE0_RXNOTINTABLE0_OUT out std_logic

Port

TILE0_RXNOTINTABLE1_OUT

TILE0_RXNOTINTABLE1_OUT out std_logic

Port

TILE0_RXP0_IN

TILE0_RXP0_IN in std_logic

Port

TILE0_RXP1_IN

TILE0_RXP1_IN in std_logic

Port

TILE0_RXPOWERDOWN0_IN

TILE0_RXPOWERDOWN0_IN in std_logic_vector ( 1 downto 0 )

Port

TILE0_RXPOWERDOWN1_IN

TILE0_RXPOWERDOWN1_IN in std_logic_vector ( 1 downto 0 )

Port

TILE0_RXRECCLK0_OUT

TILE0_RXRECCLK0_OUT out std_logic

Port

TILE0_RXRECCLK1_OUT

TILE0_RXRECCLK1_OUT out std_logic

Port

TILE0_RXRESET0_IN

TILE0_RXRESET0_IN in std_logic

Port

TILE0_RXRESET1_IN

TILE0_RXRESET1_IN in std_logic

Port

TILE0_RXRUNDISP0_OUT

TILE0_RXRUNDISP0_OUT out std_logic

Port

TILE0_RXRUNDISP1_OUT

TILE0_RXRUNDISP1_OUT out std_logic

Port

TILE0_RXUSRCLK0_IN

TILE0_RXUSRCLK0_IN in std_logic

Port

TILE0_RXUSRCLK1_IN

TILE0_RXUSRCLK1_IN in std_logic

Port

TILE0_RXUSRCLK20_IN

TILE0_RXUSRCLK20_IN in std_logic

Port

TILE0_RXUSRCLK21_IN

TILE0_RXUSRCLK21_IN in std_logic

Port

TILE0_TXBUFSTATUS0_OUT

TILE0_TXBUFSTATUS0_OUT out std_logic_vector ( 1 downto 0 )

Port

TILE0_TXBUFSTATUS1_OUT

TILE0_TXBUFSTATUS1_OUT out std_logic_vector ( 1 downto 0 )

Port

TILE0_TXCHARDISPMODE0_IN

TILE0_TXCHARDISPMODE0_IN in std_logic

Port

TILE0_TXCHARDISPMODE1_IN

TILE0_TXCHARDISPMODE1_IN in std_logic

Port

TILE0_TXCHARDISPVAL0_IN

TILE0_TXCHARDISPVAL0_IN in std_logic

Port

TILE0_TXCHARDISPVAL1_IN

TILE0_TXCHARDISPVAL1_IN in std_logic

Port

TILE0_TXCHARISK0_IN

TILE0_TXCHARISK0_IN in std_logic

Port

TILE0_TXCHARISK1_IN

TILE0_TXCHARISK1_IN in std_logic

Port

TILE0_TXDATA0_IN

TILE0_TXDATA0_IN in std_logic_vector ( 7 downto 0 )

Port

TILE0_TXDATA1_IN

TILE0_TXDATA1_IN in std_logic_vector ( 7 downto 0 )

Port

TILE0_TXN0_OUT

TILE0_TXN0_OUT out std_logic

Port

TILE0_TXN1_OUT

TILE0_TXN1_OUT out std_logic

Port

TILE0_TXOUTCLK0_OUT

TILE0_TXOUTCLK0_OUT out std_logic

Port

TILE0_TXOUTCLK1_OUT

TILE0_TXOUTCLK1_OUT out std_logic

Port

TILE0_TXP0_OUT

TILE0_TXP0_OUT out std_logic

Port

TILE0_TXP1_OUT

TILE0_TXP1_OUT out std_logic

Port

TILE0_TXPOWERDOWN0_IN

TILE0_TXPOWERDOWN0_IN in std_logic_vector ( 1 downto 0 )

Port

TILE0_TXPOWERDOWN1_IN

TILE0_TXPOWERDOWN1_IN in std_logic_vector ( 1 downto 0 )

Port

TILE0_TXRESET0_IN

TILE0_TXRESET0_IN in std_logic

Port

TILE0_TXRESET1_IN

TILE0_TXRESET1_IN in std_logic

Port

TILE0_TXUSRCLK0_IN

TILE0_TXUSRCLK0_IN in std_logic

Port

TILE0_TXUSRCLK1_IN

TILE0_TXUSRCLK1_IN in std_logic

Port

TILE0_TXUSRCLK20_IN

TILE0_TXUSRCLK20_IN in std_logic

Port

TILE0_TXUSRCLK21_IN

TILE0_TXUSRCLK21_IN in std_logic

Port

txpolarity

txpolarity in std_logic_vector ( 1 downto 0 )

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

WRAPPER_SIM_GTXRESET_SPEEDUP

WRAPPER_SIM_GTXRESET_SPEEDUP integer := 0

Generic

WRAPPER_SIM_PLL_PERDIV2

WRAPPER_SIM_PLL_PERDIV2 bit_vector := x " 0c8 "

Generic

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx.vhd