UDP_master_fifo Entity Reference

Inheritance diagram for UDP_master_fifo:

Entities
Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
BUFWIDTH	positive := 5

Ports
mac_clk	in STD_LOGIC
rst_macclk	in STD_LOGIC
FIFO_WriteEn	in STD_LOGIC
FIFO_Data	in STD_LOGIC_VECTOR ( 9 downto 0 )
FIFO_Full	out STD_LOGIC
master_tx_pause	out STD_LOGIC
mac_tx_ready	in STD_LOGIC
mac_tx_data	out STD_LOGIC_VECTOR ( 7 downto 0 )
mac_tx_error	out STD_LOGIC
mac_tx_last	out STD_LOGIC
mac_tx_valid	out STD_LOGIC

Member Data Documentation

BUFWIDTH

BUFWIDTH positive := 5

Generic

FIFO_Data

FIFO_Data in STD_LOGIC_VECTOR ( 9 downto 0 )

Port

FIFO_Full

FIFO_Full out STD_LOGIC

Port

FIFO_WriteEn

FIFO_WriteEn in STD_LOGIC

Port

IEEE

IEEE

Library

mac_clk

mac_clk in STD_LOGIC

Port

mac_tx_data

mac_tx_data out STD_LOGIC_VECTOR ( 7 downto 0 )

Port

mac_tx_error

mac_tx_error out STD_LOGIC

Port

mac_tx_last

mac_tx_last out STD_LOGIC

Port

mac_tx_ready

mac_tx_ready in STD_LOGIC

Port

mac_tx_valid

mac_tx_valid out STD_LOGIC

Port

master_tx_pause

master_tx_pause out STD_LOGIC

Port

NUMERIC_STD

NUMERIC_STD

Package

rst_macclk

rst_macclk in STD_LOGIC

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_master_fifo.vhd