UDP_slave_if Entity Reference

Inheritance diagram for UDP_slave_if:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
mac_rx_data	out std_logic_vector ( 7 DOWNTO 0 )
mac_rx_error	out std_logic
mac_rx_last	out std_logic
mac_rx_valid	out std_logic
Got_IP_addr	in std_logic
mac_tx_ready	out std_logic
mac_tx_data	in std_logic_vector ( 7 DOWNTO 0 )
mac_tx_error	in std_logic
mac_tx_last	in std_logic
mac_tx_valid	in std_logic
slave_rx_data	in std_logic_vector ( 8 DOWNTO 0 )
slave_rx_err	in std_logic
slave_tx_pause	in std_logic
slave_tx_data	out std_logic_vector ( 8 DOWNTO 0 )

Member Data Documentation

Got_IP_addr

Got_IP_addr in std_logic

Port

ieee

ieee

Library

mac_clk

mac_clk in std_logic

Port

mac_rx_data

mac_rx_data out std_logic_vector ( 7 DOWNTO 0 )

Port

mac_rx_error

mac_rx_error out std_logic

Port

mac_rx_last

mac_rx_last out std_logic

Port

mac_rx_valid

mac_rx_valid out std_logic

Port

mac_tx_data

mac_tx_data in std_logic_vector ( 7 DOWNTO 0 )

Port

mac_tx_error

mac_tx_error in std_logic

Port

mac_tx_last

mac_tx_last in std_logic

Port

mac_tx_ready

mac_tx_ready out std_logic

Port

mac_tx_valid

mac_tx_valid in std_logic

Port

numeric_std

numeric_std

Package

rst_macclk

rst_macclk in std_logic

Port

slave_rx_data

slave_rx_data in std_logic_vector ( 8 DOWNTO 0 )

Port

slave_rx_err

slave_rx_err in std_logic

Port

slave_tx_data

slave_tx_data out std_logic_vector ( 8 DOWNTO 0 )

Port

slave_tx_pause

slave_tx_pause in std_logic

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_slave_if.vhd