axi_lite_ipif Entity Reference

Inheritance diagram for axi_lite_ipif:

Collaboration diagram for axi_lite_ipif:

Entities
imp	architecture

Libraries
ieee
axi_lite_ipif_v3_0_4

Use Clauses
std_logic_1164
std_logic_unsigned
numeric_std
std_logic_misc
ipif_pkg	Package <ipif_pkg>

Generics
C_S_AXI_DATA_WIDTH	integer range 32 to 32 := 32
C_S_AXI_ADDR_WIDTH	integer := 32
C_S_AXI_MIN_SIZE	std_logic_vector ( 31 downto 0 ) := X " 000001FF "
C_USE_WSTRB	integer := 0
C_DPHASE_TIMEOUT	integer range 0 to 512 := 8
C_ARD_ADDR_RANGE_ARRAY	SLV64_ARRAY_TYPE := ( X " 0000_0000_7000_0000 " , X " 0000_0000_7000_00FF " , X " 0000_0000_7000_0100 " , X " 0000_0000_7000_01FF " )
C_ARD_NUM_CE_ARRAY	INTEGER_ARRAY_TYPE := ( 4 , 12 )
C_FAMILY	string := " virtex6 "

Ports
S_AXI_ACLK	in std_logic
S_AXI_ARESETN	in std_logic
S_AXI_AWADDR	in std_logic_vector ( C_S_AXI_ADDR_WIDTH - 1 downto 0 )
S_AXI_AWVALID	in std_logic
S_AXI_AWREADY	out std_logic
S_AXI_WDATA	in std_logic_vector ( C_S_AXI_DATA_WIDTH - 1 downto 0 )
S_AXI_WSTRB	in std_logic_vector ( ( C_S_AXI_DATA_WIDTH / 8 ) - 1 downto 0 )
S_AXI_WVALID	in std_logic
S_AXI_WREADY	out std_logic
S_AXI_BRESP	out std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out std_logic
S_AXI_BREADY	in std_logic
S_AXI_ARADDR	in std_logic_vector ( C_S_AXI_ADDR_WIDTH - 1 downto 0 )
S_AXI_ARVALID	in std_logic
S_AXI_ARREADY	out std_logic
S_AXI_RDATA	out std_logic_vector ( C_S_AXI_DATA_WIDTH - 1 downto 0 )
S_AXI_RRESP	out std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out std_logic
S_AXI_RREADY	in std_logic
Bus2IP_Clk	out std_logic
Bus2IP_Resetn	out std_logic
Bus2IP_Addr	out std_logic_vector ( ( C_S_AXI_ADDR_WIDTH - 1 ) downto 0 )
Bus2IP_RNW	out std_logic
Bus2IP_BE	out std_logic_vector ( ( ( C_S_AXI_DATA_WIDTH / 8 ) - 1 ) downto 0 )
Bus2IP_CS	out std_logic_vector ( ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 - 1 ) downto 0 )
Bus2IP_RdCE	out std_logic_vector ( ( calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 ) downto 0 )
Bus2IP_WrCE	out std_logic_vector ( ( calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 ) downto 0 )
Bus2IP_Data	out std_logic_vector ( ( C_S_AXI_DATA_WIDTH - 1 ) downto 0 )
IP2Bus_Data	in std_logic_vector ( ( C_S_AXI_DATA_WIDTH - 1 ) downto 0 )
IP2Bus_WrAck	in std_logic
IP2Bus_RdAck	in std_logic
IP2Bus_Error	in std_logic

Member Data Documentation

axi_lite_ipif_v3_0_4

axi_lite_ipif_v3_0_4

Library

Bus2IP_Addr

Bus2IP_Addr out std_logic_vector ( ( C_S_AXI_ADDR_WIDTH - 1 ) downto 0 )

Port

Bus2IP_BE

Bus2IP_BE out std_logic_vector ( ( ( C_S_AXI_DATA_WIDTH / 8 ) - 1 ) downto 0 )

Port

Bus2IP_Clk

Bus2IP_Clk out std_logic

Port

Bus2IP_CS

Bus2IP_CS out std_logic_vector ( ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 - 1 ) downto 0 )

Port

Bus2IP_Data

Bus2IP_Data out std_logic_vector ( ( C_S_AXI_DATA_WIDTH - 1 ) downto 0 )

Port

Bus2IP_RdCE

Bus2IP_RdCE out std_logic_vector ( ( calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 ) downto 0 )

Port

Bus2IP_Resetn

Bus2IP_Resetn out std_logic

Port

Bus2IP_RNW

Bus2IP_RNW out std_logic

Port

Bus2IP_WrCE

Bus2IP_WrCE out std_logic_vector ( ( calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 ) downto 0 )

Port

C_ARD_ADDR_RANGE_ARRAY

C_ARD_ADDR_RANGE_ARRAY SLV64_ARRAY_TYPE := ( X " 0000_0000_7000_0000 " , X " 0000_0000_7000_00FF " , X " 0000_0000_7000_0100 " , X " 0000_0000_7000_01FF " )

Generic

C_ARD_NUM_CE_ARRAY

C_ARD_NUM_CE_ARRAY INTEGER_ARRAY_TYPE := ( 4 , 12 )

Generic

C_DPHASE_TIMEOUT

C_DPHASE_TIMEOUT integer range 0 to 512 := 8

Generic

C_FAMILY

C_FAMILY string := " virtex6 "

Generic

C_S_AXI_ADDR_WIDTH

C_S_AXI_ADDR_WIDTH integer := 32

Generic

C_S_AXI_DATA_WIDTH

C_S_AXI_DATA_WIDTH integer range 32 to 32 := 32

Generic

C_S_AXI_MIN_SIZE

C_S_AXI_MIN_SIZE std_logic_vector ( 31 downto 0 ) := X " 000001FF "

Generic

C_USE_WSTRB

C_USE_WSTRB integer := 0

Generic

ieee

ieee

Library

IP2Bus_Data

IP2Bus_Data in std_logic_vector ( ( C_S_AXI_DATA_WIDTH - 1 ) downto 0 )

Port

IP2Bus_Error

IP2Bus_Error in std_logic

Port

IP2Bus_RdAck

IP2Bus_RdAck in std_logic

Port

IP2Bus_WrAck

IP2Bus_WrAck in std_logic

Port

ipif_pkg

ipif_pkg

Package

numeric_std

numeric_std

Package

S_AXI_ACLK

S_AXI_ACLK in std_logic

Port

S_AXI_ARADDR

S_AXI_ARADDR in std_logic_vector ( C_S_AXI_ADDR_WIDTH - 1 downto 0 )

Port

S_AXI_ARESETN

S_AXI_ARESETN in std_logic

Port

S_AXI_ARREADY

S_AXI_ARREADY out std_logic

Port

S_AXI_ARVALID

S_AXI_ARVALID in std_logic

Port

S_AXI_AWADDR

S_AXI_AWADDR in std_logic_vector ( C_S_AXI_ADDR_WIDTH - 1 downto 0 )

Port

S_AXI_AWREADY

S_AXI_AWREADY out std_logic

Port

S_AXI_AWVALID

S_AXI_AWVALID in std_logic

Port

S_AXI_BREADY

S_AXI_BREADY in std_logic

Port

S_AXI_BRESP

S_AXI_BRESP out std_logic_vector ( 1 downto 0 )

Port

S_AXI_BVALID

S_AXI_BVALID out std_logic

Port

S_AXI_RDATA

S_AXI_RDATA out std_logic_vector ( C_S_AXI_DATA_WIDTH - 1 downto 0 )

Port

S_AXI_RREADY

S_AXI_RREADY in std_logic

Port

S_AXI_RRESP

S_AXI_RRESP out std_logic_vector ( 1 downto 0 )

Port

S_AXI_RVALID

S_AXI_RVALID out std_logic

Port

S_AXI_WDATA

S_AXI_WDATA in std_logic_vector ( C_S_AXI_DATA_WIDTH - 1 downto 0 )

Port

S_AXI_WREADY

S_AXI_WREADY out std_logic

Port

S_AXI_WSTRB

S_AXI_WSTRB in std_logic_vector ( ( C_S_AXI_DATA_WIDTH / 8 ) - 1 downto 0 )

Port

S_AXI_WVALID

S_AXI_WVALID in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_misc

std_logic_misc

Package

std_logic_unsigned

std_logic_unsigned

Package

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd