clock_div Entity Reference

Inheritance diagram for clock_div:

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
VComponents

Ports
clk	in std_logic
d17	out std_logic
d25	out std_logic
d28	out std_logic

Member Data Documentation

clk

clk in std_logic

Port

d17

d17 out std_logic

Port

d25

d25 out std_logic

Port

d28

d28 out std_logic

Port

ieee

ieee

Library

std_logic_1164

std_logic_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/clock_div.vhd