clocks_7s_extphy Entity Reference

Inheritance diagram for clocks_7s_extphy:

Collaboration diagram for clocks_7s_extphy:

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
VComponents
numeric_std

Ports
sysclk_p	in std_logic
sysclk_n	in std_logic
clko_125	out std_logic
clko_200	out std_logic
clko_ipb	out std_logic
locked	out std_logic
nuke	in std_logic
rsto_125	out std_logic
rsto_ipb	out std_logic
onehz	out std_logic
clko_spi	out std_logic
soft_rst	in std_logic
rsto_ipb_ctrl	out std_logic

Member Data Documentation

clko_125

clko_125 out std_logic

Port

clko_200

clko_200 out std_logic

Port

clko_ipb

clko_ipb out std_logic

Port

clko_spi

clko_spi out std_logic

Port

ieee

ieee

Library

locked

locked out std_logic

Port

nuke

nuke in std_logic

Port

numeric_std

numeric_std

Package

onehz

onehz out std_logic

Port

rsto_125

rsto_125 out std_logic

Port

rsto_ipb

rsto_ipb out std_logic

Port

rsto_ipb_ctrl

rsto_ipb_ctrl out std_logic

Port

soft_rst

soft_rst in std_logic

Port

std_logic_1164

std_logic_1164

Package

sysclk_n

sysclk_n in std_logic

Port

sysclk_p

sysclk_p in std_logic

Port

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following files:

• components/ipbus_util/firmware/hdl/clocks_7s_extphy.vhd
• FTM/Control/hdl/clocks_7s_ftm.vhd