rtl Architecture Reference

Processes
PROCESS_337	( sysclk )
PROCESS_338	( clk_ipb_b )
PROCESS_339	( clk_125_b )
PROCESS_561	( sysclk )
PROCESS_562	( clk_ipb_b )
PROCESS_563	( clk_125_b )
PROCESS_899	( sysclk )
PROCESS_900	( clk_ipb_b )
PROCESS_901	( clk_125_b )

Components
clock_divider_s6

Signals
locked_int	std_logic
sysclk	std_logic
clk_ipb_i	std_logic
clk_125_i	std_logic
clkfb	std_logic
clk_ipb_b	std_logic
clk_125_b	std_logic
rst	std_logic := ' 1 '
d17	std_logic
d17_d	std_logic

Instantiations
ibufgds0	ibufgds
bufg125	bufg
bufgipb	bufg
mmcm	mmcm_base
clkdiv	clock_divider_s6
ibufgds0	ibufgds
bufg125	bufg
bufgipb	bufg
mmcm	mmcm_base
clkdiv	clock_divider_s6
ibufgds0	ibufgds
bufg125	bufg
bufgipb	bufg
mmcm	mmcm_base
clkdiv	clock_divider_s6

Member Function Documentation

PROCESS_337()

PROCESS_337

(

sysclk

)

PROCESS_338()

PROCESS_338 (   clk_ipb_b   )

Process

PROCESS_339()

PROCESS_339 (   clk_125_b   )

Process

PROCESS_561()

PROCESS_561

(

sysclk

)

PROCESS_562()

PROCESS_562 (   clk_ipb_b   )

Process

PROCESS_563()

PROCESS_563 (   clk_125_b   )

Process

PROCESS_899()

PROCESS_899

(

sysclk

)

PROCESS_900()

PROCESS_900 (   clk_ipb_b   )

Process

PROCESS_901()

PROCESS_901 (   clk_125_b   )

Process

Member Data Documentation

bufg125 [1/3]

bufg125 bufg

Instantiation

bufg125 [2/3]

bufg125 bufg

Instantiation

bufg125 [3/3]

bufg125 bufg

Instantiation

bufgipb [1/3]

bufgipb bufg

Instantiation

bufgipb [2/3]

bufgipb bufg

Instantiation

bufgipb [3/3]

bufgipb bufg

Instantiation

clk_125_b

clk_125_b std_logic

Signal

clk_125_i

clk_125_i std_logic

Signal

clk_ipb_b

clk_ipb_b std_logic

Signal

clk_ipb_i

clk_ipb_i std_logic

Signal

clkdiv [1/3]

clkdiv clock_divider_s6

Instantiation

clkdiv [2/3]

clkdiv clock_divider_s6

Instantiation

clkdiv [3/3]

clkdiv clock_divider_s6

Instantiation

clkfb

clkfb std_logic

Signal

clock_divider_s6

clock_divider_s6

Component

d17

d17 std_logic

Signal

d17_d

d17_d std_logic

Signal

ibufgds0 [1/3]

ibufgds0 ibufgds

Instantiation

ibufgds0 [2/3]

ibufgds0 ibufgds

Instantiation

ibufgds0 [3/3]

ibufgds0 ibufgds

Instantiation

locked_int

locked_int std_logic

Signal

mmcm [1/3]

mmcm mmcm_base

Instantiation

mmcm [2/3]

mmcm mmcm_base

Instantiation

mmcm [3/3]

mmcm mmcm_base

Instantiation

rst

rst std_logic := ' 1 '

Signal

sysclk

sysclk std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/hdl/clocks_v6_extphy.vhd