My Project
v0.0.16
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Entities | |
rtl | architecture |
Libraries | |
IEEE | |
unisim |
Use Clauses | |
STD_LOGIC_1164 | |
numeric_std | |
VComponents | |
ftm | Package <ftm> |
Generics | |
N_TXS | positive |
Ports | |
mgt_data | in mgt_data_array ( N_TXS - 1 downto 0 ) |
mgt_clock | in std_logic_vector ( N_TXS - 1 downto 0 ) |
select_tx | in std_logic_vector ( 5 downto 0 ) |
monitor | out std_logic |
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Generic |
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