My Project
v0.0.16
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Entities | |
rtl | architecture |
Libraries | |
IEEE |
Use Clauses | |
std_logic_1164 | |
std_logic_arith | |
std_logic_unsigned |
Ports | |
ipb_clk | in std_logic |
out_clk | in std_logic |
reset | in std_logic |
req | in std_logic |
ack | in std_logic |
kick | out std_logic := ' 0 ' |
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Port |
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Library |
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Port |
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Port |
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Port |
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Port |
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Port |
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Package |
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Package |
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Package |