Inheritance diagram for con_2quads_6g4_mgts:
Collaboration diagram for con_2quads_6g4_mgts:
Entities | |
| RTL | architecture |
Libraries | |
| ieee | |
| UNISIM | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| std_logic_unsigned | |
| std_logic_misc | |
| VCOMPONENTS | |
| ftm | Package <ftm> |
| ftm_mgt | Package <ftm_mgt> |
Generics | |
| EXAMPLE_CONFIG_INDEPENDENT_LANES | integer := 1 |
| EXAMPLE_LANE_WITH_START_CHAR | integer := 0 |
| EXAMPLE_WORDS_IN_BRAM | integer := 512 |
| EXAMPLE_SIM_GTRESET_SPEEDUP | string := " TRUE " |
| STABLE_CLOCK_PERIOD | integer := 8 |
| EXAMPLE_USE_CHIPSCOPE | integer := 0 |
Ports | |
| Q0_CLK1_GTREFCLK_PAD_N_IN | in std_logic |
| Q0_CLK1_GTREFCLK_PAD_P_IN | in std_logic |
| Q1_CLK1_GTREFCLK_PAD_N_IN | in std_logic |
| Q1_CLK1_GTREFCLK_PAD_P_IN | in std_logic |
| DRPCLK_IN | in std_logic |
| TRACK_DATA_OUT | out std_logic |
| mgt_source_data | in mgt_data_array ( 7 downto 0 ) |
| mgt_source_clk2 | out std_logic_vector ( 7 downto 0 ) |
| mgt_sink_data | out mgt_data_array ( 7 downto 0 ) |
| mgt_sink_clk2 | out std_logic_vector ( 7 downto 0 ) |
| mgt_control | in mgt_2quad_control |
| mgt_status | out mgt_2quad_status |
| RXN_IN | in std_logic_vector ( 7 downto 0 ) |
| RXP_IN | in std_logic_vector ( 7 downto 0 ) |
| TXN_OUT | out std_logic_vector ( 7 downto 0 ) |
| TXP_OUT | out std_logic_vector ( 7 downto 0 ) |
Member Data Documentation
◆ DRPCLK_IN
|
Port |
◆ EXAMPLE_CONFIG_INDEPENDENT_LANES
|
Generic |
◆ EXAMPLE_LANE_WITH_START_CHAR
|
Generic |
◆ EXAMPLE_SIM_GTRESET_SPEEDUP
|
Generic |
◆ EXAMPLE_USE_CHIPSCOPE
|
Generic |
◆ EXAMPLE_WORDS_IN_BRAM
|
Generic |
◆ ftm
|
Package |
◆ ftm_mgt
|
Package |
◆ ieee
|
Library |
◆ mgt_control
|
Port |
◆ mgt_sink_clk2
|
Port |
◆ mgt_sink_data
|
Port |
◆ mgt_source_clk2
|
Port |
◆ mgt_source_data
|
Port |
◆ mgt_status
|
Port |
◆ numeric_std
|
Package |
◆ Q0_CLK1_GTREFCLK_PAD_N_IN
|
Port |
◆ Q0_CLK1_GTREFCLK_PAD_P_IN
|
Port |
◆ Q1_CLK1_GTREFCLK_PAD_N_IN
|
Port |
◆ Q1_CLK1_GTREFCLK_PAD_P_IN
|
Port |
◆ RXN_IN
|
Port |
◆ RXP_IN
|
Port |
◆ STABLE_CLOCK_PERIOD
|
Generic |
◆ std_logic_1164
|
Package |
◆ std_logic_misc
|
Package |
◆ std_logic_unsigned
|
Package |
◆ TRACK_DATA_OUT
|
Port |
◆ TXN_OUT
|
Port |
◆ TXP_OUT
|
Port |
◆ UNISIM
|
Library |
◆ VCOMPONENTS
|
Package |
The documentation for this class was generated from the following file:
- FTM/Control/mgts/con_2quads_6g4_mgts.vhd
