behavioral Architecture Reference

Processes
PROCESS_18	( clock )

Signals
crc_r	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
crc_s	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Member Function Documentation

PROCESS_18()

PROCESS_18 (   clock   )

Process

Member Data Documentation

crc_r

crc_r std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

crc_s

crc_s std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this class was generated from the following file:

• common/Misc/hdl/crc9d32.vhd