decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem Entity Reference

Entities
STRUCTURE	architecture

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
VCOMPONENTS

Ports
dout	out STD_LOGIC_VECTOR ( 15 downto 0 )
wr_clk	in STD_LOGIC
EN	in STD_LOGIC
din	in STD_LOGIC_VECTOR ( 15 downto 0 )
Q	in STD_LOGIC_VECTOR ( 3 downto 0 )
\gpr1.dout_i_reg[1]_0\	in STD_LOGIC_VECTOR ( 3 downto 0 )
E	in STD_LOGIC_VECTOR ( 0 to 0 )
rd_clk	in STD_LOGIC

Member Data Documentation

\gpr1.dout_i_reg[1]_0\

\gpr1.dout_i_reg[1]_0\ in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

din

din in STD_LOGIC_VECTOR ( 15 downto 0 )

Port

dout

dout out STD_LOGIC_VECTOR ( 15 downto 0 )

Port

E

E in STD_LOGIC_VECTOR ( 0 to 0 )

Port

EN

EN in STD_LOGIC

Port

IEEE

IEEE

Library

Q

Q in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

rd_clk

rd_clk in STD_LOGIC

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

wr_clk

wr_clk in STD_LOGIC

Port

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The documentation for this class was generated from the following file:

• VivadoProject/FTM_Control/FTM_Control.cache/ip/2019.2/2ff3bb9ee2a7821a/dbg_hub_sim_netlist.vhdl