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My Project
v0.0.16
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Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| VComponents | |
Generics | |
| DWIDTH | positive |
| DELAY | integer |
Ports | |
| clk | in std_logic |
| d | in std_logic_vector ( DWIDTH - 1 downto 0 ) |
| q | out std_logic_vector ( DWIDTH - 1 downto 0 ) |
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Port |
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Generic |
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Generic |
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Library |
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Package |
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Package |
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Library |
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Package |
1.8.13