My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
del_array Entity Reference

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
VComponents 

Generics

DWIDTH  positive
DELAY  integer

Ports

clk   in std_logic
d   in std_logic_vector ( DWIDTH - 1 downto 0 )
q   out std_logic_vector ( DWIDTH - 1 downto 0 )

Member Data Documentation

◆ clk

clk in std_logic
Port

◆ d

d in std_logic_vector ( DWIDTH - 1 downto 0 )
Port

◆ DELAY

DELAY integer
Generic

◆ DWIDTH

DWIDTH positive
Generic

◆ ieee

ieee
Library

◆ q

q out std_logic_vector ( DWIDTH - 1 downto 0 )
Port

◆ std_logic_1164

std_logic_1164
Package

◆ std_logic_unsigned

◆ unisim

unisim
Library

◆ VComponents

VComponents
Package

The documentation for this class was generated from the following file: