delay_128 Entity Reference

Inheritance diagram for delay_128:

Entities
rtl	architecture

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
numeric_std
vcomponents

Ports
ttc_clk	in std_logic
input	in std_logic := ' 0 '
set_delay	in std_logic_vector ( 6 downto 0 )
output	out std_logic

Member Data Documentation

IEEE

IEEE

Library

input

input in std_logic := ' 0 '

Port

numeric_std

numeric_std

Package

output

output out std_logic

Port

set_delay

set_delay in std_logic_vector ( 6 downto 0 )

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

ttc_clk

ttc_clk in std_logic

Port

UNISIM

UNISIM

Library

vcomponents

vcomponents

Package

---

The documentation for this class was generated from the following file:

• common/Misc/hdl/delay_128.vhd