rtl Architecture Reference

Processes
bc_count	( data_clk , eof , bc_counter )
word_count	( data_clk , eof )
retime_select	( data_clk , frame_type )

Constants
REVERSE_BIT_ORDER	boolean := TRUE
K28_0	std_logic_vector ( 7 downto 0 ) := x " 1C "
K28_1	std_logic_vector ( 7 downto 0 ) := x " 3C "
K28_5	std_logic_vector ( 7 downto 0 ) := x " BC "
NULL_WORD	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signals
bc_counter	natural range 0 to N_BCS_ORBIT
frame_index	natural range 0 to FRAME_SIZE - 1
mgtdata	mgt_data
efexdata	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
efexalign	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
jfexdata	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
jfexalign	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
gfexdata	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
gfexalign	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
crc_start	std_logic := ' 0 '
crc_in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
crc9	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
crc_9d32	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
masked_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcid	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
data_int	mgt_data
frame_type_int	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
rodata	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Member Function Documentation

bc_count()

bc_count (   data_clk ,   eof ,   bc_counter   )

Process

retime_select()

retime_select (   data_clk ,   frame_type   )

Process

word_count()

word_count (   data_clk ,   eof   )

Process

Member Data Documentation

bc_counter

bc_counter natural range 0 to N_BCS_ORBIT

Signal

bcid

bcid std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )

Signal

crc9

crc9 std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

crc_9d32

crc_9d32 std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

crc_in

crc_in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

crc_start

crc_start std_logic := ' 0 '

Signal

data_int

data_int mgt_data

Signal

efexalign

efexalign mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

efexdata

efexdata mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

frame_index

frame_index natural range 0 to FRAME_SIZE - 1

Signal

frame_type_int

frame_type_int std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Signal

gfexalign

gfexalign mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

gfexdata

gfexdata mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

jfexalign

jfexalign mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

jfexdata

jfexdata mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

K28_0

K28_0 std_logic_vector ( 7 downto 0 ) := x " 1C "

Constant

K28_1

K28_1 std_logic_vector ( 7 downto 0 ) := x " 3C "

Constant

K28_5

K28_5 std_logic_vector ( 7 downto 0 ) := x " BC "

Constant

masked_data

masked_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

mgtdata

mgtdata mgt_data

Signal

NULL_WORD

NULL_WORD std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Constant

REVERSE_BIT_ORDER

REVERSE_BIT_ORDER boolean := TRUE

Constant

rodata

rodata mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

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The documentation for this class was generated from the following files:

• common/DSS_buffer/hdl/dummy_frame_generator.vhd
• FTM/Control/hdl/dummy_frame_generator_c.vhd